X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FPowerPC%2FPPCHazardRecognizers.cpp;h=7234e30fa73e612639df90297904a19490534025;hb=51b079cd28aacf110bf1b53c89bca4a2b23c4d22;hp=852b9c8e32dfd46101db518fb023772153bc4533;hpb=b84225b080a6ad72c4eecececc0a4fdffc9455a8;p=oota-llvm.git

diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
index 852b9c8e32d..7234e30fa73 100644
--- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp
+++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by Chris Lattner and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -11,27 +11,240 @@
 //
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "sched"
 #include "PPCHazardRecognizers.h"
 #include "PPC.h"
+#include "PPCInstrInfo.h"
+#include "PPCTargetMachine.h"
+#include "llvm/CodeGen/ScheduleDAG.h"
 #include "llvm/Support/Debug.h"
-#include <iostream>
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
+#define DEBUG_TYPE "pre-RA-sched"
+
+bool PPCDispatchGroupSBHazardRecognizer::isLoadAfterStore(SUnit *SU) {
+  // FIXME: Move this.
+  if (isBCTRAfterSet(SU))
+    return true;
+
+  const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
+  if (!MCID)
+    return false;
+
+  if (!MCID->mayLoad())
+    return false;
+
+  // SU is a load; for any predecessors in this dispatch group, that are stores,
+  // and with which we have an ordering dependency, return true.
+  for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) {
+    const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit());
+    if (!PredMCID || !PredMCID->mayStore())
+      continue;
+
+    if (!SU->Preds[i].isNormalMemory() && !SU->Preds[i].isBarrier())
+      continue;
+
+    for (unsigned j = 0, je = CurGroup.size(); j != je; ++j)
+      if (SU->Preds[i].getSUnit() == CurGroup[j])
+        return true;
+  }
+
+  return false; 
+}
+
+bool PPCDispatchGroupSBHazardRecognizer::isBCTRAfterSet(SUnit *SU) {
+  const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
+  if (!MCID)
+    return false;
+
+  if (!MCID->isBranch())
+    return false;
+
+  // SU is a branch; for any predecessors in this dispatch group, with which we
+  // have a data dependence and set the counter register, return true.
+  for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) {
+    const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit());
+    if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR)
+      continue;
+
+    if (SU->Preds[i].isCtrl())
+      continue;
+
+    for (unsigned j = 0, je = CurGroup.size(); j != je; ++j)
+      if (SU->Preds[i].getSUnit() == CurGroup[j])
+        return true;
+  }
+
+  return false; 
+}
+
+// FIXME: Remove this when we don't need this:
+namespace llvm { namespace PPC { extern int getNonRecordFormOpcode(uint16_t); } }
+
+// FIXME: A lot of code in PPCDispatchGroupSBHazardRecognizer is P7 specific.
+
+bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID,
+                                                       unsigned &NSlots) {
+  // FIXME: Indirectly, this information is contained in the itinerary, and
+  // we should derive it from there instead of separately specifying it
+  // here.
+  unsigned IIC = MCID->getSchedClass();
+  switch (IIC) {
+  default:
+    NSlots = 1;
+    break;
+  case PPC::Sched::IIC_IntDivW:
+  case PPC::Sched::IIC_IntDivD:
+  case PPC::Sched::IIC_LdStLoadUpd:
+  case PPC::Sched::IIC_LdStLDU:
+  case PPC::Sched::IIC_LdStLFDU:
+  case PPC::Sched::IIC_LdStLFDUX:
+  case PPC::Sched::IIC_LdStLHA:
+  case PPC::Sched::IIC_LdStLHAU:
+  case PPC::Sched::IIC_LdStLWA:
+  case PPC::Sched::IIC_LdStSTDU:
+  case PPC::Sched::IIC_LdStSTFDU:
+    NSlots = 2;
+    break;
+  case PPC::Sched::IIC_LdStLoadUpdX:
+  case PPC::Sched::IIC_LdStLDUX:
+  case PPC::Sched::IIC_LdStLHAUX:
+  case PPC::Sched::IIC_LdStLWARX:
+  case PPC::Sched::IIC_LdStLDARX:
+  case PPC::Sched::IIC_LdStSTDUX:
+  case PPC::Sched::IIC_LdStSTDCX:
+  case PPC::Sched::IIC_LdStSTWCX:
+  case PPC::Sched::IIC_BrMCRX: // mtcr
+  // FIXME: Add sync/isync (here and in the itinerary).
+    NSlots = 4;
+    break;
+  }
+
+  // FIXME: record-form instructions need a different itinerary class.
+  if (NSlots == 1 && PPC::getNonRecordFormOpcode(MCID->getOpcode()) != -1)
+    NSlots = 2;
+
+  switch (IIC) {
+  default:
+    // All multi-slot instructions must come first.
+    return NSlots > 1;
+  case PPC::Sched::IIC_BrCR: // cr logicals
+  case PPC::Sched::IIC_SprMFCR:
+  case PPC::Sched::IIC_SprMFCRF:
+  case PPC::Sched::IIC_SprMTSPR:
+    return true;
+  }
+}
+
+ScheduleHazardRecognizer::HazardType
+PPCDispatchGroupSBHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
+  if (Stalls == 0 && isLoadAfterStore(SU))
+    return NoopHazard;
+
+  return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
+}
+
+bool PPCDispatchGroupSBHazardRecognizer::ShouldPreferAnother(SUnit *SU) {
+  const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
+  unsigned NSlots;
+  if (MCID && mustComeFirst(MCID, NSlots) && CurSlots)
+    return true;
+
+  return ScoreboardHazardRecognizer::ShouldPreferAnother(SU);
+}
+
+unsigned PPCDispatchGroupSBHazardRecognizer::PreEmitNoops(SUnit *SU) {
+  // We only need to fill out a maximum of 5 slots here: The 6th slot could
+  // only be a second branch, and otherwise the next instruction will start a
+  // new group.
+  if (isLoadAfterStore(SU) && CurSlots < 6) {
+    unsigned Directive =
+        DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
+    // If we're using a special group-terminating nop, then we need only one.
+    if (Directive == PPC::DIR_PWR6 || Directive == PPC::DIR_PWR7 ||
+        Directive == PPC::DIR_PWR8 )
+      return 1;
+
+    return 5 - CurSlots;
+  }
+
+  return ScoreboardHazardRecognizer::PreEmitNoops(SU);
+}
+
+void PPCDispatchGroupSBHazardRecognizer::EmitInstruction(SUnit *SU) {
+  const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
+  if (MCID) {
+    if (CurSlots == 5 || (MCID->isBranch() && CurBranches == 1)) {
+      CurGroup.clear();
+      CurSlots = CurBranches = 0;
+    } else {
+      DEBUG(dbgs() << "**** Adding to dispatch group: SU(" <<
+                      SU->NodeNum << "): ");
+      DEBUG(DAG->dumpNode(SU));
+
+      unsigned NSlots;
+      bool MustBeFirst = mustComeFirst(MCID, NSlots);
+
+      // If this instruction must come first, but does not, then it starts a
+      // new group.
+      if (MustBeFirst && CurSlots) {
+        CurSlots = CurBranches = 0;
+        CurGroup.clear();
+      }
+
+      CurSlots += NSlots;
+      CurGroup.push_back(SU);
+
+      if (MCID->isBranch())
+        ++CurBranches;
+    }
+  }
+
+  return ScoreboardHazardRecognizer::EmitInstruction(SU);
+}
+
+void PPCDispatchGroupSBHazardRecognizer::AdvanceCycle() {
+  return ScoreboardHazardRecognizer::AdvanceCycle();
+}
+
+void PPCDispatchGroupSBHazardRecognizer::RecedeCycle() {
+  llvm_unreachable("Bottom-up scheduling not supported");
+}
+
+void PPCDispatchGroupSBHazardRecognizer::Reset() {
+  CurGroup.clear();
+  CurSlots = CurBranches = 0;
+  return ScoreboardHazardRecognizer::Reset();
+}
+
+void PPCDispatchGroupSBHazardRecognizer::EmitNoop() {
+  unsigned Directive =
+      DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
+  // If the group has now filled all of its slots, or if we're using a special
+  // group-terminating nop, the group is complete.
+  if (Directive == PPC::DIR_PWR6 || Directive == PPC::DIR_PWR7 ||
+      Directive == PPC::DIR_PWR8 || CurSlots == 6)  {
+    CurGroup.clear();
+    CurSlots = CurBranches = 0;
+  } else {
+    CurGroup.push_back(nullptr);
+    ++CurSlots;
+  }
+}
 
 //===----------------------------------------------------------------------===//
 // PowerPC 970 Hazard Recognizer
 //
 // This models the dispatch group formation of the PPC970 processor.  Dispatch
-// groups are bundles of up to five instructions that can contain up to two ALU
-// (aka FXU) ops, two FPU ops, two Load/Store ops, one CR op, one VALU op, one
-// VPERM op, and one BRANCH op.  If the code contains more instructions in a
-// sequence than the dispatch group can contain (e.g. three loads in a row) the
-// processor terminates the dispatch group early, wasting execution resources.
+// groups are bundles of up to five instructions that can contain various mixes
+// of instructions.  The PPC970 can dispatch a peak of 4 non-branch and one
+// branch instruction per-cycle.
 //
-// In addition to these restrictions, there are a number of other restrictions:
-// some instructions, e.g. branches, are required to be the last instruction in
-// a group.  Additionally, only branches can issue in the 5th (last) slot.
+// There are a number of restrictions to dispatch group formation: some
+// instructions can only be issued in the first slot of a dispatch group, & some
+// instructions fill an entire dispatch group.  Additionally, only branches can
+// issue in the 5th (last) slot.
 //
 // Finally, there are a number of "structural" hazards on the PPC970.  These
 // conditions cause large performance penalties due to misprediction, recovery,
@@ -41,218 +254,168 @@ using namespace llvm;
 // conditions, we insert no-op instructions when appropriate.
 //
 // FIXME: This is missing some significant cases:
-//  -1. Handle all of the instruction types in GetInstrType.
-//   0. Handling of instructions that must be the first/last in a group.
 //   1. Modeling of microcoded instructions.
-//   2. Handling of cracked instructions.
-//   3. Handling of serialized operations.
-//   4. Handling of the esoteric cases in "Resource-based Instruction Grouping",
-//      e.g. integer divides that only execute in the second slot.
+//   2. Handling of serialized operations.
+//   3. Handling of the esoteric cases in "Resource-based Instruction Grouping".
 //
 
+PPCHazardRecognizer970::PPCHazardRecognizer970(const ScheduleDAG &DAG)
+    : DAG(DAG) {
+  EndDispatchGroup();
+}
+
 void PPCHazardRecognizer970::EndDispatchGroup() {
-  DEBUG(std::cerr << "=== Start of dispatch group\n");
-  // Pipeline units.
-  NumFXU = NumLSU = NumFPU = 0;
-  HasCR = HasSPR = HasVALU = HasVPERM = false;
+  DEBUG(errs() << "=== Start of dispatch group\n");
   NumIssued = 0;
-  
+
   // Structural hazard info.
   HasCTRSet = false;
-  StorePtr1 = StorePtr2 = SDOperand();
-  StoreSize = 0;
+  NumStores = 0;
 }
 
 
-PPCHazardRecognizer970::PPC970InstrType
-PPCHazardRecognizer970::GetInstrType(unsigned Opcode) {
-  if (Opcode < ISD::BUILTIN_OP_END)
-    return PseudoInst;
-  Opcode -= ISD::BUILTIN_OP_END;
-  
-  switch (Opcode) {
-  case PPC::FMRSD: return PseudoInst;  // Usually coallesced away.
-  case PPC::BCTRL:
-  case PPC::BL:
-  case PPC::BLA:
-    return BR;
-  case PPC::MCRF:
-  case PPC::MFCR:
-  case PPC::MFOCRF:
-    return CR;
-  case PPC::MFLR:
-  case PPC::MFCTR:
-  case PPC::MTLR:
-  case PPC::MTCTR:
-    return SPR;
-  case PPC::LFS:
-  case PPC::LFD:
-  case PPC::LWZ:
-  case PPC::LFSX:
-  case PPC::LWZX:
-  case PPC::LBZ:
-  case PPC::LHA:
-  case PPC::LHZ:
-  case PPC::LWZU:
-    return LSU_LD;
-  case PPC::STFS:
-  case PPC::STFD:
-  case PPC::STW:
-  case PPC::STB:
-  case PPC::STH:
-  case PPC::STWU:
-    return LSU_ST;
-  case PPC::DIVW:
-  case PPC::DIVWU:
-  case PPC::DIVD:
-  case PPC::DIVDU:
-    return FXU_FIRST;
-  case PPC::FADDS:
-  case PPC::FCTIWZ:
-  case PPC::FRSP:
-  case PPC::FSUB:
-    return FPU;
-  }
-  
-  return FXU;
-}
+PPCII::PPC970_Unit
+PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
+                                     bool &isFirst, bool &isSingle,
+                                     bool &isCracked,
+                                     bool &isLoad, bool &isStore) {
+  const MCInstrDesc &MCID = DAG.TII->get(Opcode);
 
+  isLoad  = MCID.mayLoad();
+  isStore = MCID.mayStore();
 
-/// StartBasicBlock - Initiate a new dispatch group.
-void PPCHazardRecognizer970::StartBasicBlock() {
-  EndDispatchGroup();
+  uint64_t TSFlags = MCID.TSFlags;
+
+  isFirst   = TSFlags & PPCII::PPC970_First;
+  isSingle  = TSFlags & PPCII::PPC970_Single;
+  isCracked = TSFlags & PPCII::PPC970_Cracked;
+  return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask);
 }
 
 /// isLoadOfStoredAddress - If we have a load from the previously stored pointer
 /// as indicated by StorePtr1/StorePtr2/StoreSize, return true.
 bool PPCHazardRecognizer970::
-isLoadOfStoredAddress(unsigned LoadSize, SDOperand Ptr1, SDOperand Ptr2) const {
-  // Handle exact and commuted addresses.
-  if (Ptr1 == StorePtr1 && Ptr2 == StorePtr2)
-    return true;
-  if (Ptr2 == StorePtr1 && Ptr1 == StorePtr2)
-    return true;
-  
-  // Okay, we don't have an exact match, if this is an indexed offset, see if we
-  // have overlap (which happens during fp->int conversion for example).
-  if (StorePtr2 == Ptr2) {
-    if (ConstantSDNode *StoreOffset = dyn_cast<ConstantSDNode>(StorePtr1))
-      if (ConstantSDNode *LoadOffset = dyn_cast<ConstantSDNode>(Ptr1)) {
-        // Okay the base pointers match, so we have [c1+r] vs [c2+r].  Check to
-        // see if the load and store actually overlap.
-        int StoreOffs = StoreOffset->getValue();
-        int LoadOffs  = LoadOffset->getValue();
-        if (StoreOffs < LoadOffs) {
-          if (int(StoreOffs+StoreSize) > LoadOffs) return true;
-        } else {
-          if (int(LoadOffs+LoadSize) > StoreOffs) return true;
-        }
+isLoadOfStoredAddress(uint64_t LoadSize, int64_t LoadOffset,
+  const Value *LoadValue) const {
+  for (unsigned i = 0, e = NumStores; i != e; ++i) {
+    // Handle exact and commuted addresses.
+    if (LoadValue == StoreValue[i] && LoadOffset == StoreOffset[i])
+      return true;
+
+    // Okay, we don't have an exact match, if this is an indexed offset, see if
+    // we have overlap (which happens during fp->int conversion for example).
+    if (StoreValue[i] == LoadValue) {
+      // Okay the base pointers match, so we have [c1+r] vs [c2+r].  Check
+      // to see if the load and store actually overlap.
+      if (StoreOffset[i] < LoadOffset) {
+        if (int64_t(StoreOffset[i]+StoreSize[i]) > LoadOffset) return true;
+      } else {
+        if (int64_t(LoadOffset+LoadSize) > StoreOffset[i]) return true;
       }
+    }
   }
   return false;
 }
 
 /// getHazardType - We return hazard for any non-branch instruction that would
-/// terminate terminate the dispatch group.  We turn NoopHazard for any
+/// terminate the dispatch group.  We turn NoopHazard for any
 /// instructions that wouldn't terminate the dispatch group that would cause a
 /// pipeline flush.
-HazardRecognizer::HazardType PPCHazardRecognizer970::
-getHazardType(SDNode *Node) {
-  PPC970InstrType InstrType = GetInstrType(Node->getOpcode());
-  if (InstrType == PseudoInst) return NoHazard;  
-  unsigned Opcode = Node->getOpcode()-ISD::BUILTIN_OP_END;
+ScheduleHazardRecognizer::HazardType PPCHazardRecognizer970::
+getHazardType(SUnit *SU, int Stalls) {
+  assert(Stalls == 0 && "PPC hazards don't support scoreboard lookahead");
 
-  switch (InstrType) {
-  default: assert(0 && "Unknown instruction type!");
-  case FXU:
-  case FXU_FIRST: if (NumFXU  == 2) return Hazard;
-  case LSU_ST:
-  case LSU_LD:    if (NumLSU  == 2) return Hazard;
-  case FPU:       if (NumFPU  == 2) return Hazard;
-  case CR:        if (HasCR) return Hazard;
-  case SPR:       if (HasSPR) return Hazard;
-  case VALU:      if (HasVALU) return Hazard;
-  case VPERM:     if (HasVPERM) return Hazard;
-  case BR:  break;
-  }
-  
-  // We can only issue a CR or SPR instruction, or an FXU instruction that needs
-  // to lead a dispatch group as the first instruction in the group.
-  if (NumIssued != 0 && 
-      (InstrType == CR || InstrType == SPR || InstrType == FXU_FIRST))
+  MachineInstr *MI = SU->getInstr();
+
+  if (MI->isDebugValue())
+    return NoHazard;
+
+  unsigned Opcode = MI->getOpcode();
+  bool isFirst, isSingle, isCracked, isLoad, isStore;
+  PPCII::PPC970_Unit InstrType =
+    GetInstrType(Opcode, isFirst, isSingle, isCracked,
+                 isLoad, isStore);
+  if (InstrType == PPCII::PPC970_Pseudo) return NoHazard;
+
+  // We can only issue a PPC970_First/PPC970_Single instruction (such as
+  // crand/mtspr/etc) if this is the first cycle of the dispatch group.
+  if (NumIssued != 0 && (isFirst || isSingle))
     return Hazard;
-  
-  // We can only issue a branch as the last instruction in a group.
-  if (NumIssued == 4 && InstrType != BR)
+
+  // If this instruction is cracked into two ops by the decoder, we know that
+  // it is not a branch and that it cannot issue if 3 other instructions are
+  // already in the dispatch group.
+  if (isCracked && NumIssued > 2)
     return Hazard;
-  
+
+  switch (InstrType) {
+  default: llvm_unreachable("Unknown instruction type!");
+  case PPCII::PPC970_FXU:
+  case PPCII::PPC970_LSU:
+  case PPCII::PPC970_FPU:
+  case PPCII::PPC970_VALU:
+  case PPCII::PPC970_VPERM:
+    // We can only issue a branch as the last instruction in a group.
+    if (NumIssued == 4) return Hazard;
+    break;
+  case PPCII::PPC970_CRU:
+    // We can only issue a CR instruction in the first two slots.
+    if (NumIssued >= 2) return Hazard;
+    break;
+  case PPCII::PPC970_BRU:
+    break;
+  }
+
   // Do not allow MTCTR and BCTRL to be in the same dispatch group.
   if (HasCTRSet && Opcode == PPC::BCTRL)
     return NoopHazard;
-  
+
   // If this is a load following a store, make sure it's not to the same or
   // overlapping address.
-  if (InstrType == LSU_LD && StoreSize) {
-    unsigned LoadSize;
-    switch (Opcode) {
-    default: assert(0 && "Unknown load!");
-    case PPC::LBZ: LoadSize = 1; break;
-    case PPC::LHA:
-    case PPC::LHZ: LoadSize = 2; break;
-    case PPC::LWZU:
-    case PPC::LFSX:
-    case PPC::LFS:
-    case PPC::LWZX:
-    case PPC::LWZ: LoadSize = 4; break;
-    case PPC::LFD: LoadSize = 8; break;
-    }
-    
-    if (isLoadOfStoredAddress(LoadSize, 
-                              Node->getOperand(0), Node->getOperand(1)))
+  if (isLoad && NumStores && !MI->memoperands_empty()) {
+    MachineMemOperand *MO = *MI->memoperands_begin();
+    if (isLoadOfStoredAddress(MO->getSize(),
+                              MO->getOffset(), MO->getValue()))
       return NoopHazard;
   }
-  
+
   return NoHazard;
 }
 
-void PPCHazardRecognizer970::EmitInstruction(SDNode *Node) {
-  PPC970InstrType InstrType = GetInstrType(Node->getOpcode());
-  if (InstrType == PseudoInst) return;
-  unsigned Opcode = Node->getOpcode()-ISD::BUILTIN_OP_END;
+void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) {
+  MachineInstr *MI = SU->getInstr();
+
+  if (MI->isDebugValue())
+    return;
+
+  unsigned Opcode = MI->getOpcode();
+  bool isFirst, isSingle, isCracked, isLoad, isStore;
+  PPCII::PPC970_Unit InstrType =
+    GetInstrType(Opcode, isFirst, isSingle, isCracked,
+                 isLoad, isStore);
+  if (InstrType == PPCII::PPC970_Pseudo) return;
 
   // Update structural hazard information.
-  if (Opcode == PPC::MTCTR) HasCTRSet = true;
-  
+  if (Opcode == PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet = true;
+
   // Track the address stored to.
-  if (InstrType == LSU_ST) {
-    StorePtr1 = Node->getOperand(1);
-    StorePtr2 = Node->getOperand(2);
-    switch (Opcode) {
-    default: assert(0 && "Unknown store instruction!");
-    case PPC::STB:  StoreSize = 1; break;
-    case PPC::STH:  StoreSize = 2; break;
-    case PPC::STFS:
-    case PPC::STWU:
-    case PPC::STW:  StoreSize = 4; break;
-    case PPC::STFD: StoreSize = 8; break;
-    }
-  }
-  
-  switch (InstrType) {
-  default: assert(0 && "Unknown instruction type!");
-  case FXU:
-  case FXU_FIRST: ++NumFXU; break;
-  case LSU_LD:
-  case LSU_ST:    ++NumLSU; break;
-  case FPU:       ++NumFPU; break;
-  case CR:        HasCR    = true; break;
-  case SPR:       HasSPR   = true; break;
-  case VALU:      HasVALU  = true; break;
-  case VPERM:     HasVPERM = true; break;
-  case BR:        NumIssued = 4; return;  // ends a d-group.
+  if (isStore && NumStores < 4 && !MI->memoperands_empty()) {
+    MachineMemOperand *MO = *MI->memoperands_begin();
+    StoreSize[NumStores] = MO->getSize();
+    StoreOffset[NumStores] = MO->getOffset();
+    StoreValue[NumStores] = MO->getValue();
+    ++NumStores;
   }
+
+  if (InstrType == PPCII::PPC970_BRU || isSingle)
+    NumIssued = 4;  // Terminate a d-group.
   ++NumIssued;
-  
+
+  // If this instruction is cracked into two ops by the decoder, remember that
+  // we issued two pieces.
+  if (isCracked)
+    ++NumIssued;
+
   if (NumIssued == 5)
     EndDispatchGroup();
 }
@@ -264,6 +427,7 @@ void PPCHazardRecognizer970::AdvanceCycle() {
     EndDispatchGroup();
 }
 
-void PPCHazardRecognizer970::EmitNoop() {
-  AdvanceCycle();
+void PPCHazardRecognizer970::Reset() {
+  EndDispatchGroup();
 }
+