X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FPowerPC%2FPPCISelDAGToDAG.cpp;h=475bde18efb7ac92445cf45f51fb89e276b72224;hb=9bb6c81683393363ed1ff8c66397f2d944c0966b;hp=a00812017380efea463c8b8f848e979a6e690aa0;hpb=c08f902bb7bfcc8a97a4c7c9eb9187882dc2d6d7;p=oota-llvm.git diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index a0081201738..475bde18efb 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by Chris Lattner and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -12,243 +12,197 @@ // //===----------------------------------------------------------------------===// +#define DEBUG_TYPE "ppc-codegen" #include "PPC.h" +#include "MCTargetDesc/PPCPredicates.h" #include "PPCTargetMachine.h" -#include "PPCISelLowering.h" -#include "PPCHazardRecognizers.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" -#include "llvm/Target/TargetOptions.h" -#include "llvm/ADT/Statistic.h" -#include "llvm/Constants.h" -#include "llvm/GlobalValue.h" -#include "llvm/Intrinsics.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/GlobalAlias.h" +#include "llvm/IR/GlobalValue.h" +#include "llvm/IR/GlobalVariable.h" +#include "llvm/IR/Intrinsics.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" -#include -#include +#include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetOptions.h" using namespace llvm; +namespace llvm { + void initializePPCDAGToDAGISelPass(PassRegistry&); +} + namespace { - Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed"); - //===--------------------------------------------------------------------===// /// PPCDAGToDAGISel - PPC specific code to select PPC machine /// instructions for SelectionDAG operations. /// class PPCDAGToDAGISel : public SelectionDAGISel { - PPCTargetMachine &TM; - PPCTargetLowering PPCLowering; + const PPCTargetMachine &TM; + const PPCTargetLowering &PPCLowering; + const PPCSubtarget &PPCSubTarget; unsigned GlobalBaseReg; public: - PPCDAGToDAGISel(PPCTargetMachine &tm) - : SelectionDAGISel(PPCLowering), TM(tm), - PPCLowering(*TM.getTargetLowering()) {} - - virtual bool runOnFunction(Function &Fn) { + explicit PPCDAGToDAGISel(PPCTargetMachine &tm) + : SelectionDAGISel(tm), TM(tm), + PPCLowering(*TM.getTargetLowering()), + PPCSubTarget(*TM.getSubtargetImpl()) { + initializePPCDAGToDAGISelPass(*PassRegistry::getPassRegistry()); + } + + virtual bool runOnMachineFunction(MachineFunction &MF) { // Make sure we re-emit a set of the global base reg if necessary GlobalBaseReg = 0; - SelectionDAGISel::runOnFunction(Fn); - - InsertVRSaveCode(Fn); + SelectionDAGISel::runOnMachineFunction(MF); + + if (!PPCSubTarget.isSVR4ABI()) + InsertVRSaveCode(MF); + return true; } - + + virtual void PostprocessISelDAG(); + /// getI32Imm - Return a target constant with the specified value, of type /// i32. - inline SDOperand getI32Imm(unsigned Imm) { + inline SDValue getI32Imm(unsigned Imm) { return CurDAG->getTargetConstant(Imm, MVT::i32); } /// getI64Imm - Return a target constant with the specified value, of type /// i64. - inline SDOperand getI64Imm(uint64_t Imm) { + inline SDValue getI64Imm(uint64_t Imm) { return CurDAG->getTargetConstant(Imm, MVT::i64); } - + /// getSmallIPtrImm - Return a target constant of pointer type. - inline SDOperand getSmallIPtrImm(unsigned Imm) { + inline SDValue getSmallIPtrImm(unsigned Imm) { return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy()); } - - + + /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s + /// with any number of 0s on either side. The 1s are allowed to wrap from + /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. + /// 0x0F0F0000 is not, since all 1s are not contiguous. + static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME); + + + /// isRotateAndMask - Returns true if Mask and Shift can be folded into a + /// rotate and mask opcode and mask operation. + static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask, + unsigned &SH, unsigned &MB, unsigned &ME); + /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC /// base register. Return the virtual register that holds this value. - SDOperand getGlobalBaseReg(); - + SDNode *getGlobalBaseReg(); + // Select - Convert the specified operand from a target-independent to a // target-specific node if it hasn't already been changed. - void Select(SDOperand &Result, SDOperand Op); - + SDNode *Select(SDNode *N); + SDNode *SelectBitfieldInsert(SDNode *N); /// SelectCC - Select a comparison of the specified values with the /// specified condition code, returning the CR# of the expression. - SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC); + SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl); /// SelectAddrImm - Returns true if the address N can be represented by /// a base register plus a signed 16-bit displacement [r+imm]. - bool SelectAddrImm(SDOperand N, SDOperand &Disp, SDOperand &Base); - + bool SelectAddrImm(SDValue N, SDValue &Disp, + SDValue &Base) { + return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG, false); + } + + /// SelectAddrImmOffs - Return true if the operand is valid for a preinc + /// immediate field. Note that the operand at this point is already the + /// result of a prior SelectAddressRegImm call. + bool SelectAddrImmOffs(SDValue N, SDValue &Out) const { + if (N.getOpcode() == ISD::TargetConstant || + N.getOpcode() == ISD::TargetGlobalAddress) { + Out = N; + return true; + } + + return false; + } + /// SelectAddrIdx - Given the specified addressed, check to see if it can be /// represented as an indexed [r+r] operation. Returns false if it can /// be represented by [r+imm], which are preferred. - bool SelectAddrIdx(SDOperand N, SDOperand &Base, SDOperand &Index); - + bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) { + return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG); + } + /// SelectAddrIdxOnly - Given the specified addressed, force it to be /// represented as an indexed [r+r] operation. - bool SelectAddrIdxOnly(SDOperand N, SDOperand &Base, SDOperand &Index); + bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) { + return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG); + } + + /// SelectAddrImmX4 - Returns true if the address N can be represented by + /// a base register plus a signed 16-bit displacement that is a multiple of 4. + /// Suitable for use by STD and friends. + bool SelectAddrImmX4(SDValue N, SDValue &Disp, SDValue &Base) { + return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG, true); + } + + // Select an address into a single register. + bool SelectAddr(SDValue N, SDValue &Base) { + Base = N; + return true; + } - /// SelectAddrImmShift - Returns true if the address N can be represented by - /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable - /// for use by STD and friends. - bool SelectAddrImmShift(SDOperand N, SDOperand &Disp, SDOperand &Base); - /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for - /// inline asm expressions. - virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op, + /// inline asm expressions. It is always correct to compute the value into + /// a register. The case of adding a (possibly relocatable) constant to a + /// register can be improved, but it is wrong to substitute Reg+Reg for + /// Reg in an asm, because the load or store opcode would have to change. + virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, - std::vector &OutOps, - SelectionDAG &DAG) { - SDOperand Op0, Op1; - switch (ConstraintCode) { - default: return true; - case 'm': // memory - if (!SelectAddrIdx(Op, Op0, Op1)) - SelectAddrImm(Op, Op0, Op1); - break; - case 'o': // offsetable - if (!SelectAddrImm(Op, Op0, Op1)) { - Select(Op0, Op); // r+0. - Op1 = getSmallIPtrImm(0); - } - break; - case 'v': // not offsetable - SelectAddrIdxOnly(Op, Op0, Op1); - break; - } - - OutOps.push_back(Op0); - OutOps.push_back(Op1); + std::vector &OutOps) { + OutOps.push_back(Op); return false; } - - SDOperand BuildSDIVSequence(SDNode *N); - SDOperand BuildUDIVSequence(SDNode *N); - - /// InstructionSelectBasicBlock - This callback is invoked by - /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. - virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); - - void InsertVRSaveCode(Function &Fn); + + void InsertVRSaveCode(MachineFunction &MF); virtual const char *getPassName() const { return "PowerPC DAG->DAG Pattern Instruction Selection"; - } - - /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for - /// this target when scheduling the DAG. - virtual HazardRecognizer *CreateTargetHazardRecognizer() { - // Should use subtarget info to pick the right hazard recognizer. For - // now, always return a PPC970 recognizer. - const TargetInstrInfo *II = PPCLowering.getTargetMachine().getInstrInfo(); - assert(II && "No InstrInfo?"); - return new PPCHazardRecognizer970(*II); } // Include the pieces autogenerated from the target description. #include "PPCGenDAGISel.inc" - + private: - SDOperand SelectSETCC(SDOperand Op); - void MySelect_PPCbctrl(SDOperand &Result, SDOperand N); - void MySelect_PPCcall(SDOperand &Result, SDOperand N); + SDNode *SelectSETCC(SDNode *N); }; } -/// InstructionSelectBasicBlock - This callback is invoked by -/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. -void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { - DEBUG(BB->dump()); - - // The selection process is inherently a bottom-up recursive process (users - // select their uses before themselves). Given infinite stack space, we - // could just start selecting on the root and traverse the whole graph. In - // practice however, this causes us to run out of stack space on large basic - // blocks. To avoid this problem, select the entry node, then all its uses, - // iteratively instead of recursively. - std::vector Worklist; - Worklist.push_back(DAG.getEntryNode()); - - // Note that we can do this in the PPC target (scanning forward across token - // chain edges) because no nodes ever get folded across these edges. On a - // target like X86 which supports load/modify/store operations, this would - // have to be more careful. - while (!Worklist.empty()) { - SDOperand Node = Worklist.back(); - Worklist.pop_back(); - - // Chose from the least deep of the top two nodes. - if (!Worklist.empty() && - Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth()) - std::swap(Worklist.back(), Node); - - if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END && - Node.Val->getOpcode() < PPCISD::FIRST_NUMBER) || - CodeGenMap.count(Node)) continue; - - for (SDNode::use_iterator UI = Node.Val->use_begin(), - E = Node.Val->use_end(); UI != E; ++UI) { - // Scan the values. If this use has a value that is a token chain, add it - // to the worklist. - SDNode *User = *UI; - for (unsigned i = 0, e = User->getNumValues(); i != e; ++i) - if (User->getValueType(i) == MVT::Other) { - Worklist.push_back(SDOperand(User, i)); - break; - } - } - - // Finally, legalize this node. - SDOperand Dummy; - Select(Dummy, Node); - } - - // Select target instructions for the DAG. - DAG.setRoot(SelectRoot(DAG.getRoot())); - assert(InFlightSet.empty() && "ISel InFlightSet has not been emptied!"); - CodeGenMap.clear(); - HandleMap.clear(); - ReplaceMap.clear(); - DAG.RemoveDeadNodes(); - - // Emit machine code to BB. - ScheduleAndEmitDAG(DAG); -} - /// InsertVRSaveCode - Once the entire function has been instruction selected, /// all virtual registers are created and all machine instructions are built, /// check to see if we need to save/restore VRSAVE. If so, do it. -void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) { +void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) { // Check to see if this function uses vector registers, which means we have to - // save and restore the VRSAVE register and update it with the regs we use. + // save and restore the VRSAVE register and update it with the regs we use. // - // In this case, there will be virtual registers of vector type type created + // In this case, there will be virtual registers of vector type created // by the scheduler. Detect them now. - MachineFunction &Fn = MachineFunction::get(&F); - SSARegMap *RegMap = Fn.getSSARegMap(); bool HasVectorVReg = false; - for (unsigned i = MRegisterInfo::FirstVirtualRegister, - e = RegMap->getLastVirtReg()+1; i != e; ++i) - if (RegMap->getRegClass(i) == &PPC::VRRCRegClass) { + for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) { + unsigned Reg = TargetRegisterInfo::index2VirtReg(i); + if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) { HasVectorVReg = true; break; } + } if (!HasVectorVReg) return; // nothing to do. - + // If we have a vector register, we want to emit code into the entry and exit // blocks to save and restore the VRSAVE register. We do this here (instead // of marking all vector instructions as clobbering VRSAVE) for two reasons: @@ -261,34 +215,36 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) { // Create two vregs - one to hold the VRSAVE register that is live-in to the // function and one for the value after having bits or'd into it. - unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass); - unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass); - + unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); + unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); + + const TargetInstrInfo &TII = *TM.getInstrInfo(); MachineBasicBlock &EntryBB = *Fn.begin(); + DebugLoc dl; // Emit the following code into the entry block: // InVRSAVE = MFVRSAVE // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE // MTVRSAVE UpdatedVRSAVE MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point - BuildMI(EntryBB, IP, PPC::MFVRSAVE, 0, InVRSAVE); - BuildMI(EntryBB, IP, PPC::UPDATE_VRSAVE, 1, UpdatedVRSAVE).addReg(InVRSAVE); - BuildMI(EntryBB, IP, PPC::MTVRSAVE, 1).addReg(UpdatedVRSAVE); - + BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE); + BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE), + UpdatedVRSAVE).addReg(InVRSAVE); + BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE); + // Find all return blocks, outputting a restore in each epilog. - const TargetInstrInfo &TII = *TM.getInstrInfo(); for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { - if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) { + if (!BB->empty() && BB->back().isReturn()) { IP = BB->end(); --IP; - + // Skip over all terminator instructions, which are part of the return // sequence. MachineBasicBlock::iterator I2 = IP; - while (I2 != BB->begin() && TII.isTerminatorInstr((--I2)->getOpcode())) + while (I2 != BB->begin() && (--I2)->isTerminator()) IP = I2; - + // Emit: MTVRSAVE InVRSave - BuildMI(*BB, IP, PPC::MTVRSAVE, 1).addReg(InVRSAVE); - } + BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE); + } } } @@ -296,22 +252,26 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) { /// getGlobalBaseReg - Output the instructions required to put the /// base address to use for accessing globals into a register. /// -SDOperand PPCDAGToDAGISel::getGlobalBaseReg() { +SDNode *PPCDAGToDAGISel::getGlobalBaseReg() { if (!GlobalBaseReg) { + const TargetInstrInfo &TII = *TM.getInstrInfo(); // Insert the set of GlobalBaseReg into the first MBB of the function - MachineBasicBlock &FirstMBB = BB->getParent()->front(); + MachineBasicBlock &FirstMBB = MF->front(); MachineBasicBlock::iterator MBBI = FirstMBB.begin(); - SSARegMap *RegMap = BB->getParent()->getSSARegMap(); + DebugLoc dl; - if (PPCLowering.getPointerTy() == MVT::i32) - GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass); - else - GlobalBaseReg = RegMap->createVirtualRegister(PPC::G8RCRegisterClass); - - BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR); - BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg); + if (PPCLowering.getPointerTy() == MVT::i32) { + GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); + BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR)); + BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); + } else { + GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RCRegClass); + BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8)); + BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg); + } } - return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy()); + return CurDAG->getRegister(GlobalBaseReg, + PPCLowering.getPointerTy()).getNode(); } /// isIntS16Immediate - This method tests to see if the node is either a 32-bit @@ -322,15 +282,15 @@ static bool isIntS16Immediate(SDNode *N, short &Imm) { if (N->getOpcode() != ISD::Constant) return false; - Imm = (short)cast(N)->getValue(); + Imm = (short)cast(N)->getZExtValue(); if (N->getValueType(0) == MVT::i32) - return Imm == (int32_t)cast(N)->getValue(); + return Imm == (int32_t)cast(N)->getZExtValue(); else - return Imm == (int64_t)cast(N)->getValue(); + return Imm == (int64_t)cast(N)->getZExtValue(); } -static bool isIntS16Immediate(SDOperand Op, short &Imm) { - return isIntS16Immediate(Op.Val, Imm); +static bool isIntS16Immediate(SDValue Op, short &Imm) { + return isIntS16Immediate(Op.getNode(), Imm); } @@ -338,7 +298,7 @@ static bool isIntS16Immediate(SDOperand Op, short &Imm) { /// operand. If so Imm will receive the 32-bit value. static bool isInt32Immediate(SDNode *N, unsigned &Imm) { if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { - Imm = cast(N)->getValue(); + Imm = cast(N)->getZExtValue(); return true; } return false; @@ -347,8 +307,8 @@ static bool isInt32Immediate(SDNode *N, unsigned &Imm) { /// isInt64Immediate - This method tests to see if the node is a 64-bit constant /// operand. If so Imm will receive the 64-bit value. static bool isInt64Immediate(SDNode *N, uint64_t &Imm) { - if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { - Imm = cast(N)->getValue(); + if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { + Imm = cast(N)->getZExtValue(); return true; } return false; @@ -356,8 +316,8 @@ static bool isInt64Immediate(SDNode *N, uint64_t &Imm) { // isInt32Immediate - This method tests to see if a constant operand. // If so Imm will receive the 32 bit value. -static bool isInt32Immediate(SDOperand N, unsigned &Imm) { - return isInt32Immediate(N.Val, Imm); +static bool isInt32Immediate(SDValue N, unsigned &Imm) { + return isInt32Immediate(N.getNode(), Imm); } @@ -365,28 +325,27 @@ static bool isInt32Immediate(SDOperand N, unsigned &Imm) { // opcode and that it has a immediate integer right operand. // If so Imm will receive the 32 bit value. static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { - return N->getOpcode() == Opc && isInt32Immediate(N->getOperand(1).Val, Imm); + return N->getOpcode() == Opc + && isInt32Immediate(N->getOperand(1).getNode(), Imm); } +bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) { + if (!Val) + return false; -// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with -// any number of 0s on either side. The 1s are allowed to wrap from LSB to -// MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is -// not, since all 1s are not contiguous. -static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) { if (isShiftedMask_32(Val)) { // look for the first non-zero bit - MB = CountLeadingZeros_32(Val); + MB = countLeadingZeros(Val); // look for the first zero bit after the run of ones - ME = CountLeadingZeros_32((Val - 1) ^ Val); + ME = countLeadingZeros((Val - 1) ^ Val); return true; } else { Val = ~Val; // invert mask if (isShiftedMask_32(Val)) { // effectively look for the first zero bit - ME = CountLeadingZeros_32(Val) - 1; + ME = countLeadingZeros(Val) - 1; // effectively look for the first one bit after the run of zeros - MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1; + MB = countLeadingZeros((Val - 1) ^ Val) + 1; return true; } } @@ -394,10 +353,9 @@ static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) { return false; } -// isRotateAndMask - Returns true if Mask and Shift can be folded into a rotate -// and mask opcode and mask operation. -static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask, - unsigned &SH, unsigned &MB, unsigned &ME) { +bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask, + bool isShiftMask, unsigned &SH, + unsigned &MB, unsigned &ME) { // Don't even go down this path for i64, since different logic will be // necessary for rldicl/rldicr/rldimi. if (N->getValueType(0) != MVT::i32) @@ -407,25 +365,27 @@ static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask, unsigned Indeterminant = ~0; // bit mask marking indeterminant results unsigned Opcode = N->getOpcode(); if (N->getNumOperands() != 2 || - !isInt32Immediate(N->getOperand(1).Val, Shift) || (Shift > 31)) + !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31)) return false; - + if (Opcode == ISD::SHL) { // apply shift left to mask if it comes first - if (IsShiftMask) Mask = Mask << Shift; + if (isShiftMask) Mask = Mask << Shift; // determine which bits are made indeterminant by shift Indeterminant = ~(0xFFFFFFFFu << Shift); - } else if (Opcode == ISD::SRL) { + } else if (Opcode == ISD::SRL) { // apply shift right to mask if it comes first - if (IsShiftMask) Mask = Mask >> Shift; + if (isShiftMask) Mask = Mask >> Shift; // determine which bits are made indeterminant by shift Indeterminant = ~(0xFFFFFFFFu >> Shift); // adjust for the left rotate Shift = 32 - Shift; + } else if (Opcode == ISD::ROTL) { + Indeterminant = 0; } else { return false; } - + // if the mask doesn't intersect any Indeterminant bits if (Mask && !(Mask & Indeterminant)) { SH = Shift & 31; @@ -438,16 +398,17 @@ static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask, /// SelectBitfieldInsert - turn an or of two masked values into /// the rotate left word immediate then mask insert (rlwimi) instruction. SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { - SDOperand Op0 = N->getOperand(0); - SDOperand Op1 = N->getOperand(1); - - uint64_t LKZ, LKO, RKZ, RKO; - TLI.ComputeMaskedBits(Op0, 0xFFFFFFFFULL, LKZ, LKO); - TLI.ComputeMaskedBits(Op1, 0xFFFFFFFFULL, RKZ, RKO); - - unsigned TargetMask = LKZ; - unsigned InsertMask = RKZ; - + SDValue Op0 = N->getOperand(0); + SDValue Op1 = N->getOperand(1); + SDLoc dl(N); + + APInt LKZ, LKO, RKZ, RKO; + CurDAG->ComputeMaskedBits(Op0, LKZ, LKO); + CurDAG->ComputeMaskedBits(Op1, RKZ, RKO); + + unsigned TargetMask = LKZ.getZExtValue(); + unsigned InsertMask = RKZ.getZExtValue(); + if ((TargetMask | InsertMask) == 0xFFFFFFFF) { unsigned Op0Opc = Op0.getOpcode(); unsigned Op1Opc = Op1.getOpcode(); @@ -475,11 +436,10 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { std::swap(TargetMask, InsertMask); } } - + unsigned MB, ME; - if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) { - SDOperand Tmp1, Tmp2, Tmp3; - bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF; + if (isRunOfOnes(InsertMask, MB, ME)) { + SDValue Tmp1, Tmp2; if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && isInt32Immediate(Op1.getOperand(1), Value)) { @@ -490,284 +450,110 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { unsigned SHOpc = Op1.getOperand(0).getOpcode(); if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) { + // Note that Value must be in range here (less than 32) because + // otherwise there would not be any bits set in InsertMask. Op1 = Op1.getOperand(0).getOperand(0); SH = (SHOpc == ISD::SHL) ? Value : 32 - Value; - } else { - Op1 = Op1.getOperand(0); } } - - Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0; - Select(Tmp1, Tmp3); - Select(Tmp2, Op1); + SH &= 31; - return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2, - getI32Imm(SH), getI32Imm(MB), getI32Imm(ME)); + SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB), + getI32Imm(ME) }; + return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops); } } return 0; } -/// SelectAddrImm - Returns true if the address N can be represented by -/// a base register plus a signed 16-bit displacement [r+imm]. -bool PPCDAGToDAGISel::SelectAddrImm(SDOperand N, SDOperand &Disp, - SDOperand &Base) { - // If this can be more profitably realized as r+r, fail. - if (SelectAddrIdx(N, Disp, Base)) - return false; - - if (N.getOpcode() == ISD::ADD) { - short imm = 0; - if (isIntS16Immediate(N.getOperand(1), imm)) { - Disp = getI32Imm((int)imm & 0xFFFF); - if (FrameIndexSDNode *FI = dyn_cast(N.getOperand(0))) { - Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType()); - } else { - Base = N.getOperand(0); - } - return true; // [r+i] - } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { - // Match LOAD (ADD (X, Lo(G))). - assert(!cast(N.getOperand(1).getOperand(1))->getValue() - && "Cannot handle constant offsets yet!"); - Disp = N.getOperand(1).getOperand(0); // The global address. - assert(Disp.getOpcode() == ISD::TargetGlobalAddress || - Disp.getOpcode() == ISD::TargetConstantPool || - Disp.getOpcode() == ISD::TargetJumpTable); - Base = N.getOperand(0); - return true; // [&g+r] - } - } else if (N.getOpcode() == ISD::OR) { - short imm = 0; - if (isIntS16Immediate(N.getOperand(1), imm)) { - // If this is an or of disjoint bitfields, we can codegen this as an add - // (for better address arithmetic) if the LHS and RHS of the OR are - // provably disjoint. - uint64_t LHSKnownZero, LHSKnownOne; - PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U, - LHSKnownZero, LHSKnownOne); - if ((LHSKnownZero|~(unsigned)imm) == ~0U) { - // If all of the bits are known zero on the LHS or RHS, the add won't - // carry. - Base = N.getOperand(0); - Disp = getI32Imm((int)imm & 0xFFFF); - return true; - } - } - } else if (ConstantSDNode *CN = dyn_cast(N)) { - // Loading from a constant address. - - // If this address fits entirely in a 16-bit sext immediate field, codegen - // this as "d, 0" - short Imm; - if (isIntS16Immediate(CN, Imm)) { - Disp = CurDAG->getTargetConstant(Imm, CN->getValueType(0)); - Base = CurDAG->getRegister(PPC::R0, CN->getValueType(0)); - return true; - } - - // FIXME: Handle small sext constant offsets in PPC64 mode also! - if (CN->getValueType(0) == MVT::i32) { - int Addr = (int)CN->getValue(); - - // Otherwise, break this down into an LIS + disp. - Disp = getI32Imm((short)Addr); - Base = CurDAG->getConstant(Addr - (signed short)Addr, MVT::i32); - return true; - } - } - - Disp = getSmallIPtrImm(0); - if (FrameIndexSDNode *FI = dyn_cast(N)) - Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType()); - else - Base = N; - return true; // [r+0] -} - -/// SelectAddrIdx - Given the specified addressed, check to see if it can be -/// represented as an indexed [r+r] operation. Returns false if it can -/// be represented by [r+imm], which are preferred. -bool PPCDAGToDAGISel::SelectAddrIdx(SDOperand N, SDOperand &Base, - SDOperand &Index) { - short imm = 0; - if (N.getOpcode() == ISD::ADD) { - if (isIntS16Immediate(N.getOperand(1), imm)) - return false; // r+i - if (N.getOperand(1).getOpcode() == PPCISD::Lo) - return false; // r+i - - Base = N.getOperand(0); - Index = N.getOperand(1); - return true; - } else if (N.getOpcode() == ISD::OR) { - if (isIntS16Immediate(N.getOperand(1), imm)) - return false; // r+i can fold it if we can. - - // If this is an or of disjoint bitfields, we can codegen this as an add - // (for better address arithmetic) if the LHS and RHS of the OR are provably - // disjoint. - uint64_t LHSKnownZero, LHSKnownOne; - uint64_t RHSKnownZero, RHSKnownOne; - PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U, - LHSKnownZero, LHSKnownOne); - - if (LHSKnownZero) { - PPCLowering.ComputeMaskedBits(N.getOperand(1), ~0U, - RHSKnownZero, RHSKnownOne); - // If all of the bits are known zero on the LHS or RHS, the add won't - // carry. - if ((LHSKnownZero | RHSKnownZero) == ~0U) { - Base = N.getOperand(0); - Index = N.getOperand(1); - return true; - } - } - } - - return false; -} - -/// SelectAddrIdxOnly - Given the specified addressed, force it to be -/// represented as an indexed [r+r] operation. -bool PPCDAGToDAGISel::SelectAddrIdxOnly(SDOperand N, SDOperand &Base, - SDOperand &Index) { - // Check to see if we can easily represent this as an [r+r] address. This - // will fail if it thinks that the address is more profitably represented as - // reg+imm, e.g. where imm = 0. - if (SelectAddrIdx(N, Base, Index)) - return true; - - // If the operand is an addition, always emit this as [r+r], since this is - // better (for code size, and execution, as the memop does the add for free) - // than emitting an explicit add. - if (N.getOpcode() == ISD::ADD) { - Base = N.getOperand(0); - Index = N.getOperand(1); - return true; - } - - // Otherwise, do it the hard way, using R0 as the base register. - Base = CurDAG->getRegister(PPC::R0, N.getValueType()); - Index = N; - return true; -} - -/// SelectAddrImmShift - Returns true if the address N can be represented by -/// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable -/// for use by STD and friends. -bool PPCDAGToDAGISel::SelectAddrImmShift(SDOperand N, SDOperand &Disp, - SDOperand &Base) { - // If this can be more profitably realized as r+r, fail. - if (SelectAddrIdx(N, Disp, Base)) - return false; - - if (N.getOpcode() == ISD::ADD) { - short imm = 0; - if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { - Disp = getI32Imm(((int)imm & 0xFFFF) >> 2); - if (FrameIndexSDNode *FI = dyn_cast(N.getOperand(0))) { - Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType()); - } else { - Base = N.getOperand(0); - } - return true; // [r+i] - } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { - // Match LOAD (ADD (X, Lo(G))). - assert(!cast(N.getOperand(1).getOperand(1))->getValue() - && "Cannot handle constant offsets yet!"); - Disp = N.getOperand(1).getOperand(0); // The global address. - assert(Disp.getOpcode() == ISD::TargetGlobalAddress || - Disp.getOpcode() == ISD::TargetConstantPool || - Disp.getOpcode() == ISD::TargetJumpTable); - Base = N.getOperand(0); - return true; // [&g+r] - } - } else if (N.getOpcode() == ISD::OR) { - short imm = 0; - if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { - // If this is an or of disjoint bitfields, we can codegen this as an add - // (for better address arithmetic) if the LHS and RHS of the OR are - // provably disjoint. - uint64_t LHSKnownZero, LHSKnownOne; - PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U, - LHSKnownZero, LHSKnownOne); - if ((LHSKnownZero|~(unsigned)imm) == ~0U) { - // If all of the bits are known zero on the LHS or RHS, the add won't - // carry. - Base = N.getOperand(0); - Disp = getI32Imm(((int)imm & 0xFFFF) >> 2); - return true; - } - } - } else if (ConstantSDNode *CN = dyn_cast(N)) { - // Loading from a constant address. - - // If this address fits entirely in a 14-bit sext immediate field, codegen - // this as "d, 0" - short Imm; - if (isIntS16Immediate(CN, Imm)) { - Disp = getSmallIPtrImm((unsigned short)Imm >> 2); - Base = CurDAG->getRegister(PPC::R0, CN->getValueType(0)); - return true; - } - - // FIXME: Handle small sext constant offsets in PPC64 mode also! - if (CN->getValueType(0) == MVT::i32) { - int Addr = (int)CN->getValue(); - - // Otherwise, break this down into an LIS + disp. - Disp = getI32Imm((short)Addr >> 2); - Base = CurDAG->getConstant(Addr - (signed short)Addr, MVT::i32); - return true; - } - } - - Disp = getSmallIPtrImm(0); - if (FrameIndexSDNode *FI = dyn_cast(N)) - Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType()); - else - Base = N; - return true; // [r+0] -} - - /// SelectCC - Select a comparison of the specified values with the specified /// condition code, returning the CR# of the expression. -SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS, - ISD::CondCode CC) { +SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, + ISD::CondCode CC, SDLoc dl) { // Always select the LHS. - Select(LHS, LHS); unsigned Opc; - + if (LHS.getValueType() == MVT::i32) { - unsigned Imm, Opc; - if (ISD::isUnsignedIntSetCC(CC)) { - if (isInt32Immediate(RHS, Imm) && isUInt16(Imm)) - return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS, - getI32Imm(Imm & 0xFFFF)), 0); + unsigned Imm; + if (CC == ISD::SETEQ || CC == ISD::SETNE) { + if (isInt32Immediate(RHS, Imm)) { + // SETEQ/SETNE comparison with 16-bit immediate, fold it. + if (isUInt<16>(Imm)) + return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, + getI32Imm(Imm & 0xFFFF)), 0); + // If this is a 16-bit signed immediate, fold it. + if (isInt<16>((int)Imm)) + return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS, + getI32Imm(Imm & 0xFFFF)), 0); + + // For non-equality comparisons, the default code would materialize the + // constant, then compare against it, like this: + // lis r2, 4660 + // ori r2, r2, 22136 + // cmpw cr0, r3, r2 + // Since we are just comparing for equality, we can emit this instead: + // xoris r0,r3,0x1234 + // cmplwi cr0,r0,0x5678 + // beq cr0,L6 + SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS, + getI32Imm(Imm >> 16)), 0); + return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor, + getI32Imm(Imm & 0xFFFF)), 0); + } + Opc = PPC::CMPLW; + } else if (ISD::isUnsignedIntSetCC(CC)) { + if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm)) + return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, + getI32Imm(Imm & 0xFFFF)), 0); Opc = PPC::CMPLW; } else { short SImm; if (isIntS16Immediate(RHS, SImm)) - return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS, - getI32Imm((int)SImm & 0xFFFF)), + return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS, + getI32Imm((int)SImm & 0xFFFF)), 0); Opc = PPC::CMPW; } } else if (LHS.getValueType() == MVT::i64) { uint64_t Imm; - unsigned Opc; - if (ISD::isUnsignedIntSetCC(CC)) { - if (isInt64Immediate(RHS.Val, Imm) && isUInt16(Imm)) - return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS, - getI64Imm(Imm & 0xFFFF)), 0); + if (CC == ISD::SETEQ || CC == ISD::SETNE) { + if (isInt64Immediate(RHS.getNode(), Imm)) { + // SETEQ/SETNE comparison with 16-bit immediate, fold it. + if (isUInt<16>(Imm)) + return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS, + getI32Imm(Imm & 0xFFFF)), 0); + // If this is a 16-bit signed immediate, fold it. + if (isInt<16>(Imm)) + return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS, + getI32Imm(Imm & 0xFFFF)), 0); + + // For non-equality comparisons, the default code would materialize the + // constant, then compare against it, like this: + // lis r2, 4660 + // ori r2, r2, 22136 + // cmpd cr0, r3, r2 + // Since we are just comparing for equality, we can emit this instead: + // xoris r0,r3,0x1234 + // cmpldi cr0,r0,0x5678 + // beq cr0,L6 + if (isUInt<32>(Imm)) { + SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS, + getI64Imm(Imm >> 16)), 0); + return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor, + getI64Imm(Imm & 0xFFFF)), 0); + } + } + Opc = PPC::CMPLD; + } else if (ISD::isUnsignedIntSetCC(CC)) { + if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm)) + return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS, + getI64Imm(Imm & 0xFFFF)), 0); Opc = PPC::CMPLD; } else { short SImm; if (isIntS16Immediate(RHS, SImm)) - return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS, - getI64Imm((int)SImm & 0xFFFF)), + return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS, + getI64Imm(SImm & 0xFFFF)), 0); Opc = PPC::CMPD; } @@ -777,369 +563,645 @@ SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS, assert(LHS.getValueType() == MVT::f64 && "Unknown vt!"); Opc = PPC::FCMPUD; } - Select(RHS, RHS); - return SDOperand(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0); + return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0); } -/// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding -/// to Condition. -static unsigned getBCCForSetCC(ISD::CondCode CC) { +static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { switch (CC) { - default: assert(0 && "Unknown condition!"); abort(); - case ISD::SETOEQ: // FIXME: This is incorrect see PR642. case ISD::SETUEQ: - case ISD::SETEQ: return PPC::BEQ; - case ISD::SETONE: // FIXME: This is incorrect see PR642. + case ISD::SETONE: + case ISD::SETOLE: + case ISD::SETOGE: + llvm_unreachable("Should be lowered by legalize!"); + default: llvm_unreachable("Unknown condition!"); + case ISD::SETOEQ: + case ISD::SETEQ: return PPC::PRED_EQ; case ISD::SETUNE: - case ISD::SETNE: return PPC::BNE; - case ISD::SETOLT: // FIXME: This is incorrect see PR642. - case ISD::SETULT: - case ISD::SETLT: return PPC::BLT; - case ISD::SETOLE: // FIXME: This is incorrect see PR642. + case ISD::SETNE: return PPC::PRED_NE; + case ISD::SETOLT: + case ISD::SETLT: return PPC::PRED_LT; case ISD::SETULE: - case ISD::SETLE: return PPC::BLE; - case ISD::SETOGT: // FIXME: This is incorrect see PR642. - case ISD::SETUGT: - case ISD::SETGT: return PPC::BGT; - case ISD::SETOGE: // FIXME: This is incorrect see PR642. + case ISD::SETLE: return PPC::PRED_LE; + case ISD::SETOGT: + case ISD::SETGT: return PPC::PRED_GT; case ISD::SETUGE: - case ISD::SETGE: return PPC::BGE; - - case ISD::SETO: return PPC::BUN; - case ISD::SETUO: return PPC::BNU; + case ISD::SETGE: return PPC::PRED_GE; + case ISD::SETO: return PPC::PRED_NU; + case ISD::SETUO: return PPC::PRED_UN; + // These two are invalid for floating point. Assume we have int. + case ISD::SETULT: return PPC::PRED_LT; + case ISD::SETUGT: return PPC::PRED_GT; } - return 0; } /// getCRIdxForSetCC - Return the index of the condition register field /// associated with the SetCC condition, and whether or not the field is /// treated as inverted. That is, lt = 0; ge = 0 inverted. -static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) { +static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) { + Invert = false; switch (CC) { - default: assert(0 && "Unknown condition!"); abort(); - case ISD::SETOLT: // FIXME: This is incorrect see PR642. - case ISD::SETULT: - case ISD::SETLT: Inv = false; return 0; - case ISD::SETOGE: // FIXME: This is incorrect see PR642. + default: llvm_unreachable("Unknown condition!"); + case ISD::SETOLT: + case ISD::SETLT: return 0; // Bit #0 = SETOLT + case ISD::SETOGT: + case ISD::SETGT: return 1; // Bit #1 = SETOGT + case ISD::SETOEQ: + case ISD::SETEQ: return 2; // Bit #2 = SETOEQ + case ISD::SETUO: return 3; // Bit #3 = SETUO case ISD::SETUGE: - case ISD::SETGE: Inv = true; return 0; - case ISD::SETOGT: // FIXME: This is incorrect see PR642. - case ISD::SETUGT: - case ISD::SETGT: Inv = false; return 1; - case ISD::SETOLE: // FIXME: This is incorrect see PR642. + case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE case ISD::SETULE: - case ISD::SETLE: Inv = true; return 1; - case ISD::SETOEQ: // FIXME: This is incorrect see PR642. - case ISD::SETUEQ: - case ISD::SETEQ: Inv = false; return 2; - case ISD::SETONE: // FIXME: This is incorrect see PR642. + case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE case ISD::SETUNE: - case ISD::SETNE: Inv = true; return 2; - case ISD::SETO: Inv = true; return 3; - case ISD::SETUO: Inv = false; return 3; + case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE + case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO + case ISD::SETUEQ: + case ISD::SETOGE: + case ISD::SETOLE: + case ISD::SETONE: + llvm_unreachable("Invalid branch code: should be expanded by legalize"); + // These are invalid for floating point. Assume integer. + case ISD::SETULT: return 0; + case ISD::SETUGT: return 1; } - return 0; } -SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) { - SDNode *N = Op.Val; +// getVCmpInst: return the vector compare instruction for the specified +// vector type and condition code. Since this is for altivec specific code, +// only support the altivec types (v16i8, v8i16, v4i32, and v4f32). +static unsigned int getVCmpInst(MVT::SimpleValueType VecVT, ISD::CondCode CC) { + switch (CC) { + case ISD::SETEQ: + case ISD::SETUEQ: + case ISD::SETNE: + case ISD::SETUNE: + if (VecVT == MVT::v16i8) + return PPC::VCMPEQUB; + else if (VecVT == MVT::v8i16) + return PPC::VCMPEQUH; + else if (VecVT == MVT::v4i32) + return PPC::VCMPEQUW; + // v4f32 != v4f32 could be translate to unordered not equal + else if (VecVT == MVT::v4f32) + return PPC::VCMPEQFP; + break; + case ISD::SETLT: + case ISD::SETGT: + case ISD::SETLE: + case ISD::SETGE: + if (VecVT == MVT::v16i8) + return PPC::VCMPGTSB; + else if (VecVT == MVT::v8i16) + return PPC::VCMPGTSH; + else if (VecVT == MVT::v4i32) + return PPC::VCMPGTSW; + else if (VecVT == MVT::v4f32) + return PPC::VCMPGTFP; + break; + case ISD::SETULT: + case ISD::SETUGT: + case ISD::SETUGE: + case ISD::SETULE: + if (VecVT == MVT::v16i8) + return PPC::VCMPGTUB; + else if (VecVT == MVT::v8i16) + return PPC::VCMPGTUH; + else if (VecVT == MVT::v4i32) + return PPC::VCMPGTUW; + break; + case ISD::SETOEQ: + if (VecVT == MVT::v4f32) + return PPC::VCMPEQFP; + break; + case ISD::SETOLT: + case ISD::SETOGT: + case ISD::SETOLE: + if (VecVT == MVT::v4f32) + return PPC::VCMPGTFP; + break; + case ISD::SETOGE: + if (VecVT == MVT::v4f32) + return PPC::VCMPGEFP; + break; + default: + break; + } + llvm_unreachable("Invalid integer vector compare condition"); +} + +// getVCmpEQInst: return the equal compare instruction for the specified vector +// type. Since this is for altivec specific code, only support the altivec +// types (v16i8, v8i16, v4i32, and v4f32). +static unsigned int getVCmpEQInst(MVT::SimpleValueType VecVT) { + switch (VecVT) { + case MVT::v16i8: + return PPC::VCMPEQUB; + case MVT::v8i16: + return PPC::VCMPEQUH; + case MVT::v4i32: + return PPC::VCMPEQUW; + case MVT::v4f32: + return PPC::VCMPEQFP; + default: + llvm_unreachable("Invalid integer vector compare condition"); + } +} + + +SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) { + SDLoc dl(N); unsigned Imm; ISD::CondCode CC = cast(N->getOperand(2))->get(); + EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy(); + bool isPPC64 = (PtrVT == MVT::i64); + if (isInt32Immediate(N->getOperand(1), Imm)) { // We can codegen setcc op, imm very efficiently compared to a brcond. // Check for those cases here. // setcc op, 0 if (Imm == 0) { - SDOperand Op; - Select(Op, N->getOperand(0)); + SDValue Op = N->getOperand(0); switch (CC) { default: break; - case ISD::SETEQ: - Op = SDOperand(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0); - return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27), - getI32Imm(5), getI32Imm(31)); + case ISD::SETEQ: { + Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0); + SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) }; + return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); + } case ISD::SETNE: { - SDOperand AD = - SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, - Op, getI32Imm(~0U)), 0); - return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, + if (isPPC64) break; + SDValue AD = + SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, + Op, getI32Imm(~0U)), 0); + return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1)); } - case ISD::SETLT: - return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1), - getI32Imm(31), getI32Imm(31)); + case ISD::SETLT: { + SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; + return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); + } case ISD::SETGT: { - SDOperand T = - SDOperand(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0); - T = SDOperand(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0); - return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1), - getI32Imm(31), getI32Imm(31)); + SDValue T = + SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0); + T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0); + SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; + return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } } } else if (Imm == ~0U) { // setcc op, -1 - SDOperand Op; - Select(Op, N->getOperand(0)); + SDValue Op = N->getOperand(0); switch (CC) { default: break; case ISD::SETEQ: - Op = SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, - Op, getI32Imm(1)), 0); - return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, - SDOperand(CurDAG->getTargetNode(PPC::LI, MVT::i32, - getI32Imm(0)), 0), - Op.getValue(1)); + if (isPPC64) break; + Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, + Op, getI32Imm(1)), 0); + return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, + SDValue(CurDAG->getMachineNode(PPC::LI, dl, + MVT::i32, + getI32Imm(0)), 0), + Op.getValue(1)); case ISD::SETNE: { - Op = SDOperand(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0); - SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, - Op, getI32Imm(~0U)); - return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0), - Op, SDOperand(AD, 1)); + if (isPPC64) break; + Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0); + SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, + Op, getI32Imm(~0U)); + return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0), + Op, SDValue(AD, 1)); } case ISD::SETLT: { - SDOperand AD = SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op, - getI32Imm(1)), 0); - SDOperand AN = SDOperand(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, - Op), 0); - return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1), - getI32Imm(31), getI32Imm(31)); + SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op, + getI32Imm(1)), 0); + SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD, + Op), 0); + SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; + return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); + } + case ISD::SETGT: { + SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; + Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), + 0); + return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, + getI32Imm(1)); + } } + } + } + + SDValue LHS = N->getOperand(0); + SDValue RHS = N->getOperand(1); + + // Altivec Vector compare instructions do not set any CR register by default and + // vector compare operations return the same type as the operands. + if (LHS.getValueType().isVector()) { + EVT VecVT = LHS.getValueType(); + MVT::SimpleValueType VT = VecVT.getSimpleVT().SimpleTy; + unsigned int VCmpInst = getVCmpInst(VT, CC); + + switch (CC) { + case ISD::SETEQ: + case ISD::SETOEQ: + case ISD::SETUEQ: + return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS); + case ISD::SETNE: + case ISD::SETONE: + case ISD::SETUNE: { + SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0); + return CurDAG->SelectNodeTo(N, PPC::VNOR, VecVT, VCmp, VCmp); + } + case ISD::SETLT: + case ISD::SETOLT: + case ISD::SETULT: + return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, RHS, LHS); case ISD::SETGT: - Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op, - getI32Imm(1), getI32Imm(31), - getI32Imm(31)), 0); - return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1)); + case ISD::SETOGT: + case ISD::SETUGT: + return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS); + case ISD::SETGE: + case ISD::SETOGE: + case ISD::SETUGE: { + // Small optimization: Altivec provides a 'Vector Compare Greater Than + // or Equal To' instruction (vcmpgefp), so in this case there is no + // need for extra logic for the equal compare. + if (VecVT.getSimpleVT().isFloatingPoint()) { + return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS); + } else { + SDValue VCmpGT(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0); + unsigned int VCmpEQInst = getVCmpEQInst(VT); + SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0); + return CurDAG->SelectNodeTo(N, PPC::VOR, VecVT, VCmpGT, VCmpEQ); + } + } + case ISD::SETLE: + case ISD::SETOLE: + case ISD::SETULE: { + SDValue VCmpLE(CurDAG->getMachineNode(VCmpInst, dl, VecVT, RHS, LHS), 0); + unsigned int VCmpEQInst = getVCmpEQInst(VT); + SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0); + return CurDAG->SelectNodeTo(N, PPC::VOR, VecVT, VCmpLE, VCmpEQ); } + default: + llvm_unreachable("Invalid vector compare type: should be expanded by legalize"); } } - + bool Inv; unsigned Idx = getCRIdxForSetCC(CC, Inv); - SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC); - SDOperand IntCR; - + SDValue CCReg = SelectCC(LHS, RHS, CC, dl); + SDValue IntCR; + // Force the ccreg into CR7. - SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32); - - SDOperand InFlag(0, 0); // Null incoming flag value. - CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg, + SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32); + + SDValue InFlag(0, 0); // Null incoming flag value. + CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg, InFlag).getValue(1); - - if (TLI.getTargetMachine().getSubtarget().isGigaProcessor()) - IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, - CCReg), 0); - else - IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0); - - if (!Inv) { - return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR, - getI32Imm((32-(3-Idx)) & 31), - getI32Imm(31), getI32Imm(31)); - } else { - SDOperand Tmp = - SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR, - getI32Imm((32-(3-Idx)) & 31), - getI32Imm(31),getI32Imm(31)), 0); - return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1)); - } + + IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg, + CCReg), 0); + + SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31), + getI32Imm(31), getI32Imm(31) }; + if (!Inv) + return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); + + // Get the specified bit. + SDValue Tmp = + SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0); + return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1)); } // Select - Convert the specified operand from a target-independent to a // target-specific node if it hasn't already been changed. -void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { - SDNode *N = Op.Val; - if (N->getOpcode() >= ISD::BUILTIN_OP_END && - N->getOpcode() < PPCISD::FIRST_NUMBER) { - Result = Op; - return; // Already selected. - } +SDNode *PPCDAGToDAGISel::Select(SDNode *N) { + SDLoc dl(N); + if (N->isMachineOpcode()) + return NULL; // Already selected. - // If this has already been converted, use it. - std::map::iterator CGMI = CodeGenMap.find(Op); - if (CGMI != CodeGenMap.end()) { - Result = CGMI->second; - return; - } - switch (N->getOpcode()) { default: break; + + case ISD::Constant: { + if (N->getValueType(0) == MVT::i64) { + // Get 64 bit value. + int64_t Imm = cast(N)->getZExtValue(); + // Assume no remaining bits. + unsigned Remainder = 0; + // Assume no shift required. + unsigned Shift = 0; + + // If it can't be represented as a 32 bit value. + if (!isInt<32>(Imm)) { + Shift = countTrailingZeros(Imm); + int64_t ImmSh = static_cast(Imm) >> Shift; + + // If the shifted value fits 32 bits. + if (isInt<32>(ImmSh)) { + // Go with the shifted value. + Imm = ImmSh; + } else { + // Still stuck with a 64 bit value. + Remainder = Imm; + Shift = 32; + Imm >>= 32; + } + } + + // Intermediate operand. + SDNode *Result; + + // Handle first 32 bits. + unsigned Lo = Imm & 0xFFFF; + unsigned Hi = (Imm >> 16) & 0xFFFF; + + // Simple value. + if (isInt<16>(Imm)) { + // Just the Lo bits. + Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo)); + } else if (Lo) { + // Handle the Hi bits. + unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8; + Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi)); + // And Lo bits. + Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, + SDValue(Result, 0), getI32Imm(Lo)); + } else { + // Just the Hi bits. + Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi)); + } + + // If no shift, we're done. + if (!Shift) return Result; + + // Shift for next step if the upper 32-bits were not zero. + if (Imm) { + Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, + SDValue(Result, 0), + getI32Imm(Shift), + getI32Imm(63 - Shift)); + } + + // Add in the last bits as required. + if ((Hi = (Remainder >> 16) & 0xFFFF)) { + Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64, + SDValue(Result, 0), getI32Imm(Hi)); + } + if ((Lo = Remainder & 0xFFFF)) { + Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, + SDValue(Result, 0), getI32Imm(Lo)); + } + + return Result; + } + break; + } + case ISD::SETCC: - Result = SelectSETCC(Op); - return; + return SelectSETCC(N); case PPCISD::GlobalBaseReg: - Result = getGlobalBaseReg(); - return; - + return getGlobalBaseReg(); + case ISD::FrameIndex: { int FI = cast(N)->getIndex(); - SDOperand TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType()); - unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8; - if (N->hasOneUse()) { - Result = CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI, - getSmallIPtrImm(0)); - return; - } - Result = CodeGenMap[Op] = - SDOperand(CurDAG->getTargetNode(Opc, Op.getValueType(), TFI, - getSmallIPtrImm(0)), 0); - return; + SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0)); + unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8; + if (N->hasOneUse()) + return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), TFI, + getSmallIPtrImm(0)); + return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI, + getSmallIPtrImm(0)); } - case PPCISD::MFCR: { - SDOperand InFlag; - Select(InFlag, N->getOperand(1)); - // Use MFOCRF if supported. - if (TLI.getTargetMachine().getSubtarget().isGigaProcessor()) - Result = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, - N->getOperand(0), InFlag), 0); - else - Result = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, InFlag), 0); - CodeGenMap[Op] = Result; - return; + case PPCISD::MFOCRF: { + SDValue InFlag = N->getOperand(1); + return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, + N->getOperand(0), InFlag); } - + case ISD::SDIV: { // FIXME: since this depends on the setting of the carry flag from the srawi // we should really be making notes about that for the scheduler. - // FIXME: It sure would be nice if we could cheaply recognize the + // FIXME: It sure would be nice if we could cheaply recognize the // srl/add/sra pattern the dag combiner will generate for this as // sra/addze rather than having to handle sdiv ourselves. oh well. unsigned Imm; if (isInt32Immediate(N->getOperand(1), Imm)) { - SDOperand N0; - Select(N0, N->getOperand(0)); + SDValue N0 = N->getOperand(0); if ((signed)Imm > 0 && isPowerOf2_32(Imm)) { SDNode *Op = - CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag, - N0, getI32Imm(Log2_32(Imm))); - Result = CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, - SDOperand(Op, 0), SDOperand(Op, 1)); + CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue, + N0, getI32Imm(Log2_32(Imm))); + return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, + SDValue(Op, 0), SDValue(Op, 1)); } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) { SDNode *Op = - CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag, - N0, getI32Imm(Log2_32(-Imm))); - SDOperand PT = - SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, - SDOperand(Op, 0), SDOperand(Op, 1)), + CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue, + N0, getI32Imm(Log2_32(-Imm))); + SDValue PT = + SDValue(CurDAG->getMachineNode(PPC::ADDZE, dl, MVT::i32, + SDValue(Op, 0), SDValue(Op, 1)), 0); - Result = CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT); + return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT); } - return; } - + // Other cases are autogenerated. break; } + + case ISD::LOAD: { + // Handle preincrement loads. + LoadSDNode *LD = cast(N); + EVT LoadedVT = LD->getMemoryVT(); + + // Normal loads are handled by code generated from the .td file. + if (LD->getAddressingMode() != ISD::PRE_INC) + break; + + SDValue Offset = LD->getOffset(); + if (Offset.getOpcode() == ISD::TargetConstant || + Offset.getOpcode() == ISD::TargetGlobalAddress) { + + unsigned Opcode; + bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; + if (LD->getValueType(0) != MVT::i64) { + // Handle PPC32 integer and normal FP loads. + assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); + switch (LoadedVT.getSimpleVT().SimpleTy) { + default: llvm_unreachable("Invalid PPC load type!"); + case MVT::f64: Opcode = PPC::LFDU; break; + case MVT::f32: Opcode = PPC::LFSU; break; + case MVT::i32: Opcode = PPC::LWZU; break; + case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break; + case MVT::i1: + case MVT::i8: Opcode = PPC::LBZU; break; + } + } else { + assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!"); + assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); + switch (LoadedVT.getSimpleVT().SimpleTy) { + default: llvm_unreachable("Invalid PPC load type!"); + case MVT::i64: Opcode = PPC::LDU; break; + case MVT::i32: Opcode = PPC::LWZU8; break; + case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; + case MVT::i1: + case MVT::i8: Opcode = PPC::LBZU8; break; + } + } + + SDValue Chain = LD->getChain(); + SDValue Base = LD->getBasePtr(); + SDValue Ops[] = { Offset, Base, Chain }; + return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0), + PPCLowering.getPointerTy(), + MVT::Other, Ops); + } else { + unsigned Opcode; + bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; + if (LD->getValueType(0) != MVT::i64) { + // Handle PPC32 integer and normal FP loads. + assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); + switch (LoadedVT.getSimpleVT().SimpleTy) { + default: llvm_unreachable("Invalid PPC load type!"); + case MVT::f64: Opcode = PPC::LFDUX; break; + case MVT::f32: Opcode = PPC::LFSUX; break; + case MVT::i32: Opcode = PPC::LWZUX; break; + case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break; + case MVT::i1: + case MVT::i8: Opcode = PPC::LBZUX; break; + } + } else { + assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!"); + assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) && + "Invalid sext update load"); + switch (LoadedVT.getSimpleVT().SimpleTy) { + default: llvm_unreachable("Invalid PPC load type!"); + case MVT::i64: Opcode = PPC::LDUX; break; + case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break; + case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break; + case MVT::i1: + case MVT::i8: Opcode = PPC::LBZUX8; break; + } + } + + SDValue Chain = LD->getChain(); + SDValue Base = LD->getBasePtr(); + SDValue Ops[] = { Base, Offset, Chain }; + return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0), + PPCLowering.getPointerTy(), + MVT::Other, Ops); + } + } + case ISD::AND: { - unsigned Imm, Imm2; + unsigned Imm, Imm2, SH, MB, ME; + uint64_t Imm64; + // If this is an and of a value rotated between 0 and 31 bits and then and'd // with a mask, emit rlwinm if (isInt32Immediate(N->getOperand(1), Imm) && - (isShiftedMask_32(Imm) || isShiftedMask_32(~Imm))) { - SDOperand Val; - unsigned SH, MB, ME; - if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) { - Select(Val, N->getOperand(0).getOperand(0)); - } else if (Imm == 0) { - // AND X, 0 -> 0, not "rlwinm 32". - Select(Result, N->getOperand(1)); - return ; - } else { - Select(Val, N->getOperand(0)); - isRunOfOnes(Imm, MB, ME); - SH = 0; - } - Result = CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val, - getI32Imm(SH), getI32Imm(MB), - getI32Imm(ME)); - return; + isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) { + SDValue Val = N->getOperand(0).getOperand(0); + SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; + return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); + } + // If this is just a masked value where the input is not handled above, and + // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm + if (isInt32Immediate(N->getOperand(1), Imm) && + isRunOfOnes(Imm, MB, ME) && + N->getOperand(0).getOpcode() != ISD::ROTL) { + SDValue Val = N->getOperand(0); + SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) }; + return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); + } + // If this is a 64-bit zero-extension mask, emit rldicl. + if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) && + isMask_64(Imm64)) { + SDValue Val = N->getOperand(0); + MB = 64 - CountTrailingOnes_64(Imm64); + SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB) }; + return CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops, 3); + } + // AND X, 0 -> 0, not "rlwinm 32". + if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) { + ReplaceUses(SDValue(N, 0), N->getOperand(1)); + return NULL; } // ISD::OR doesn't get all the bitfield insertion fun. // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert - if (isInt32Immediate(N->getOperand(1), Imm) && + if (isInt32Immediate(N->getOperand(1), Imm) && N->getOperand(0).getOpcode() == ISD::OR && isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) { unsigned MB, ME; Imm = ~(Imm^Imm2); if (isRunOfOnes(Imm, MB, ME)) { - SDOperand Tmp1, Tmp2; - Select(Tmp1, N->getOperand(0).getOperand(0)); - Select(Tmp2, N->getOperand(0).getOperand(1)); - Result = SDOperand(CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, - Tmp1, Tmp2, - getI32Imm(0), getI32Imm(MB), - getI32Imm(ME)), 0); - return; + SDValue Ops[] = { N->getOperand(0).getOperand(0), + N->getOperand(0).getOperand(1), + getI32Imm(0), getI32Imm(MB),getI32Imm(ME) }; + return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops); } } - + // Other cases are autogenerated. break; } case ISD::OR: - if (SDNode *I = SelectBitfieldInsert(N)) { - Result = CodeGenMap[Op] = SDOperand(I, 0); - return; - } - + if (N->getValueType(0) == MVT::i32) + if (SDNode *I = SelectBitfieldInsert(N)) + return I; + // Other cases are autogenerated. break; case ISD::SHL: { unsigned Imm, SH, MB, ME; - if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) && + if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) && isRotateAndMask(N, Imm, true, SH, MB, ME)) { - SDOperand Val; - Select(Val, N->getOperand(0).getOperand(0)); - Result = CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, - Val, getI32Imm(SH), getI32Imm(MB), - getI32Imm(ME)); - return; + SDValue Ops[] = { N->getOperand(0).getOperand(0), + getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; + return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } - + // Other cases are autogenerated. break; } case ISD::SRL: { unsigned Imm, SH, MB, ME; - if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) && - isRotateAndMask(N, Imm, true, SH, MB, ME)) { - SDOperand Val; - Select(Val, N->getOperand(0).getOperand(0)); - Result = CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, - Val, getI32Imm(SH), getI32Imm(MB), - getI32Imm(ME)); - return; + if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) && + isRotateAndMask(N, Imm, true, SH, MB, ME)) { + SDValue Ops[] = { N->getOperand(0).getOperand(0), + getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; + return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } - + // Other cases are autogenerated. break; } case ISD::SELECT_CC: { ISD::CondCode CC = cast(N->getOperand(4))->get(); - + EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy(); + bool isPPC64 = (PtrVT == MVT::i64); + // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc - if (ConstantSDNode *N1C = dyn_cast(N->getOperand(1))) - if (ConstantSDNode *N2C = dyn_cast(N->getOperand(2))) - if (ConstantSDNode *N3C = dyn_cast(N->getOperand(3))) - if (N1C->isNullValue() && N3C->isNullValue() && - N2C->getValue() == 1ULL && CC == ISD::SETNE && - // FIXME: Implement this optzn for PPC64. - N->getValueType(0) == MVT::i32) { - SDOperand LHS; - Select(LHS, N->getOperand(0)); - SDNode *Tmp = - CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, - LHS, getI32Imm(~0U)); - Result = CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, - SDOperand(Tmp, 0), LHS, - SDOperand(Tmp, 1)); - return; - } - - SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC); - unsigned BROpc = getBCCForSetCC(CC); - - bool isFP = MVT::isFloatingPoint(N->getValueType(0)); + if (!isPPC64) + if (ConstantSDNode *N1C = dyn_cast(N->getOperand(1))) + if (ConstantSDNode *N2C = dyn_cast(N->getOperand(2))) + if (ConstantSDNode *N3C = dyn_cast(N->getOperand(3))) + if (N1C->isNullValue() && N3C->isNullValue() && + N2C->getZExtValue() == 1ULL && CC == ISD::SETNE && + // FIXME: Implement this optzn for PPC64. + N->getValueType(0) == MVT::i32) { + SDNode *Tmp = + CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, + N->getOperand(0), getI32Imm(~0U)); + return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, + SDValue(Tmp, 0), N->getOperand(0), + SDValue(Tmp, 1)); + } + + SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl); + unsigned BROpc = getPredicateForSetCC(CC); + unsigned SelectCCOp; if (N->getValueType(0) == MVT::i32) SelectCCOp = PPC::SELECT_CC_I4; @@ -1152,203 +1214,345 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { else SelectCCOp = PPC::SELECT_CC_VRRC; - SDOperand N2, N3; - Select(N2, N->getOperand(2)); - Select(N3, N->getOperand(3)); - Result = CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg, - N2, N3, getI32Imm(BROpc)); - return; + SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3), + getI32Imm(BROpc) }; + return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4); + } + case PPCISD::BDNZ: + case PPCISD::BDZ: { + bool IsPPC64 = PPCSubTarget.isPPC64(); + SDValue Ops[] = { N->getOperand(1), N->getOperand(0) }; + return CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ ? + (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : + (IsPPC64 ? PPC::BDZ8 : PPC::BDZ), + MVT::Other, Ops, 2); + } + case PPCISD::COND_BRANCH: { + // Op #0 is the Chain. + // Op #1 is the PPC::PRED_* number. + // Op #2 is the CR# + // Op #3 is the Dest MBB + // Op #4 is the Flag. + // Prevent PPC::PRED_* from being selected into LI. + SDValue Pred = + getI32Imm(cast(N->getOperand(1))->getZExtValue()); + SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3), + N->getOperand(0), N->getOperand(4) }; + return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5); } case ISD::BR_CC: { - SDOperand Chain; - Select(Chain, N->getOperand(0)); ISD::CondCode CC = cast(N->getOperand(1))->get(); - SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC); - Result = CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, - CondCode, getI32Imm(getBCCForSetCC(CC)), - N->getOperand(4), Chain); - return; + SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); + SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode, + N->getOperand(4), N->getOperand(0) }; + return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4); } case ISD::BRIND: { // FIXME: Should custom lower this. - SDOperand Chain, Target; - Select(Chain, N->getOperand(0)); - Select(Target,N->getOperand(1)); - Chain = SDOperand(CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Target, - Chain), 0); - Result = CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain); - return; + SDValue Chain = N->getOperand(0); + SDValue Target = N->getOperand(1); + unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8; + unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8; + Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target, + Chain), 0); + return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain); } - // FIXME: These are manually selected because tblgen isn't handling varargs - // nodes correctly. - case PPCISD::BCTRL: MySelect_PPCbctrl(Result, Op); return; - case PPCISD::CALL: MySelect_PPCcall(Result, Op); return; - } - - SelectCode(Result, Op); -} + case PPCISD::TOC_ENTRY: { + assert (PPCSubTarget.isPPC64() && "Only supported for 64-bit ABI"); + // For medium and large code model, we generate two instructions as + // described below. Otherwise we allow SelectCodeCommon to handle this, + // selecting one of LDtoc, LDtocJTI, and LDtocCPT. + CodeModel::Model CModel = TM.getCodeModel(); + if (CModel != CodeModel::Medium && CModel != CodeModel::Large) + break; -// FIXME: This is manually selected because tblgen isn't handling varargs nodes -// correctly. -void PPCDAGToDAGISel::MySelect_PPCbctrl(SDOperand &Result, SDOperand N) { - SDOperand Chain(0, 0); - SDOperand InFlag(0, 0); - SDNode *ResNode; - - bool hasFlag = - N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag; - - std::vector Ops; - // Push varargs arguments, including optional flag. - for (unsigned i = 1, e = N.getNumOperands()-hasFlag; i != e; ++i) { - Select(Chain, N.getOperand(i)); - Ops.push_back(Chain); - } + // The first source operand is a TargetGlobalAddress or a + // TargetJumpTable. If it is an externally defined symbol, a symbol + // with common linkage, a function address, or a jump table address, + // or if we are generating code for large code model, we generate: + // LDtocL(, ADDIStocHA(%X2, )) + // Otherwise we generate: + // ADDItocL(ADDIStocHA(%X2, ), ) + SDValue GA = N->getOperand(0); + SDValue TOCbase = N->getOperand(1); + SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64, + TOCbase, GA); - Select(Chain, N.getOperand(0)); - Ops.push_back(Chain); + if (isa(GA) || CModel == CodeModel::Large) + return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA, + SDValue(Tmp, 0)); - if (hasFlag) { - Select(Chain, N.getOperand(N.getNumOperands()-1)); - Ops.push_back(Chain); - } - - ResNode = CurDAG->getTargetNode(PPC::BCTRL, MVT::Other, MVT::Flag, Ops); - Chain = SDOperand(ResNode, 0); - InFlag = SDOperand(ResNode, 1); - SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 0, Chain.Val, - Chain.ResNo); - SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 1, InFlag.Val, - InFlag.ResNo); - Result = SDOperand(ResNode, N.ResNo); - return; -} + if (GlobalAddressSDNode *G = dyn_cast(GA)) { + const GlobalValue *GValue = G->getGlobal(); + const GlobalAlias *GAlias = dyn_cast(GValue); + const GlobalValue *RealGValue = GAlias ? + GAlias->resolveAliasedGlobal(false) : GValue; + const GlobalVariable *GVar = dyn_cast(RealGValue); + assert((GVar || isa(RealGValue)) && + "Unexpected global value subclass!"); -// FIXME: This is manually selected because tblgen isn't handling varargs nodes -// correctly. -void PPCDAGToDAGISel::MySelect_PPCcall(SDOperand &Result, SDOperand N) { - SDOperand Chain(0, 0); - SDOperand InFlag(0, 0); - SDOperand N1(0, 0); - SDOperand Tmp0(0, 0); - SDNode *ResNode; - Chain = N.getOperand(0); - N1 = N.getOperand(1); - - // Pattern: (PPCcall:void (imm:i32):$func) - // Emits: (BLA:void (imm:i32):$func) - // Pattern complexity = 4 cost = 1 - if (N1.getOpcode() == ISD::Constant) { - unsigned Tmp0C = (unsigned)cast(N1)->getValue(); - - std::vector Ops; - Ops.push_back(CurDAG->getTargetConstant(Tmp0C, MVT::i32)); - - bool hasFlag = - N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag; - - // Push varargs arguments, not including optional flag. - for (unsigned i = 2, e = N.getNumOperands()-hasFlag; i != e; ++i) { - Select(Chain, N.getOperand(i)); - Ops.push_back(Chain); - } - Select(Chain, N.getOperand(0)); - Ops.push_back(Chain); - if (hasFlag) { - Select(Chain, N.getOperand(N.getNumOperands()-1)); - Ops.push_back(Chain); + // An external variable is one without an initializer. For these, + // for variables with common linkage, and for Functions, generate + // the LDtocL form. + if (!GVar || !GVar->hasInitializer() || RealGValue->hasCommonLinkage() || + RealGValue->hasAvailableExternallyLinkage()) + return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA, + SDValue(Tmp, 0)); } - ResNode = CurDAG->getTargetNode(PPC::BLA, MVT::Other, MVT::Flag, Ops); - - Chain = SDOperand(ResNode, 0); - InFlag = SDOperand(ResNode, 1); - SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 0, Chain.Val, - Chain.ResNo); - SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 1, InFlag.Val, - InFlag.ResNo); - Result = SDOperand(ResNode, N.ResNo); - return; + + return CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64, + SDValue(Tmp, 0), GA); } - - // Pattern: (PPCcall:void (tglobaladdr:i32):$dst) - // Emits: (BL:void (tglobaladdr:i32):$dst) - // Pattern complexity = 4 cost = 1 - if (N1.getOpcode() == ISD::TargetGlobalAddress) { - std::vector Ops; - Ops.push_back(N1); - - bool hasFlag = - N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag; - - // Push varargs arguments, not including optional flag. - for (unsigned i = 2, e = N.getNumOperands()-hasFlag; i != e; ++i) { - Select(Chain, N.getOperand(i)); - Ops.push_back(Chain); + case PPCISD::VADD_SPLAT: { + // This expands into one of three sequences, depending on whether + // the first operand is odd or even, positive or negative. + assert(isa(N->getOperand(0)) && + isa(N->getOperand(1)) && + "Invalid operand on VADD_SPLAT!"); + + int Elt = N->getConstantOperandVal(0); + int EltSize = N->getConstantOperandVal(1); + unsigned Opc1, Opc2, Opc3; + EVT VT; + + if (EltSize == 1) { + Opc1 = PPC::VSPLTISB; + Opc2 = PPC::VADDUBM; + Opc3 = PPC::VSUBUBM; + VT = MVT::v16i8; + } else if (EltSize == 2) { + Opc1 = PPC::VSPLTISH; + Opc2 = PPC::VADDUHM; + Opc3 = PPC::VSUBUHM; + VT = MVT::v8i16; + } else { + assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!"); + Opc1 = PPC::VSPLTISW; + Opc2 = PPC::VADDUWM; + Opc3 = PPC::VSUBUWM; + VT = MVT::v4i32; } - Select(Chain, N.getOperand(0)); - Ops.push_back(Chain); - if (hasFlag) { - Select(Chain, N.getOperand(N.getNumOperands()-1)); - Ops.push_back(Chain); + + if ((Elt & 1) == 0) { + // Elt is even, in the range [-32,-18] + [16,30]. + // + // Convert: VADD_SPLAT elt, size + // Into: tmp = VSPLTIS[BHW] elt + // VADDU[BHW]M tmp, tmp + // Where: [BHW] = B for size = 1, H for size = 2, W for size = 4 + SDValue EltVal = getI32Imm(Elt >> 1); + SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); + SDValue TmpVal = SDValue(Tmp, 0); + return CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal); + + } else if (Elt > 0) { + // Elt is odd and positive, in the range [17,31]. + // + // Convert: VADD_SPLAT elt, size + // Into: tmp1 = VSPLTIS[BHW] elt-16 + // tmp2 = VSPLTIS[BHW] -16 + // VSUBU[BHW]M tmp1, tmp2 + SDValue EltVal = getI32Imm(Elt - 16); + SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); + EltVal = getI32Imm(-16); + SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); + return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0), + SDValue(Tmp2, 0)); + + } else { + // Elt is odd and negative, in the range [-31,-17]. + // + // Convert: VADD_SPLAT elt, size + // Into: tmp1 = VSPLTIS[BHW] elt+16 + // tmp2 = VSPLTIS[BHW] -16 + // VADDU[BHW]M tmp1, tmp2 + SDValue EltVal = getI32Imm(Elt + 16); + SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); + EltVal = getI32Imm(-16); + SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); + return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0), + SDValue(Tmp2, 0)); } - - ResNode = CurDAG->getTargetNode(PPC::BL, MVT::Other, MVT::Flag, Ops); - - Chain = SDOperand(ResNode, 0); - InFlag = SDOperand(ResNode, 1); - SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 0, Chain.Val, - Chain.ResNo); - SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 1, InFlag.Val, - InFlag.ResNo); - Result = SDOperand(ResNode, N.ResNo); - return; } - - // Pattern: (PPCcall:void (texternalsym:i32):$dst) - // Emits: (BL:void (texternalsym:i32):$dst) - // Pattern complexity = 4 cost = 1 - if (N1.getOpcode() == ISD::TargetExternalSymbol) { - std::vector Ops; - Ops.push_back(N1); - - bool hasFlag = - N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag; - - // Push varargs arguments, not including optional flag. - for (unsigned i = 2, e = N.getNumOperands()-hasFlag; i != e; ++i) { - Select(Chain, N.getOperand(i)); - Ops.push_back(Chain); + } + + return SelectCode(N); +} + +/// PostProcessISelDAG - Perform some late peephole optimizations +/// on the DAG representation. +void PPCDAGToDAGISel::PostprocessISelDAG() { + + // Skip peepholes at -O0. + if (TM.getOptLevel() == CodeGenOpt::None) + return; + + // These optimizations are currently supported only for 64-bit SVR4. + if (PPCSubTarget.isDarwin() || !PPCSubTarget.isPPC64()) + return; + + SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode()); + ++Position; + + while (Position != CurDAG->allnodes_begin()) { + SDNode *N = --Position; + // Skip dead nodes and any non-machine opcodes. + if (N->use_empty() || !N->isMachineOpcode()) + continue; + + unsigned FirstOp; + unsigned StorageOpcode = N->getMachineOpcode(); + + switch (StorageOpcode) { + default: continue; + + case PPC::LBZ: + case PPC::LBZ8: + case PPC::LD: + case PPC::LFD: + case PPC::LFS: + case PPC::LHA: + case PPC::LHA8: + case PPC::LHZ: + case PPC::LHZ8: + case PPC::LWA: + case PPC::LWZ: + case PPC::LWZ8: + FirstOp = 0; + break; + + case PPC::STB: + case PPC::STB8: + case PPC::STD: + case PPC::STFD: + case PPC::STFS: + case PPC::STH: + case PPC::STH8: + case PPC::STW: + case PPC::STW8: + FirstOp = 1; + break; } - Select(Chain, N.getOperand(0)); - Ops.push_back(Chain); - if (hasFlag) { - Select(Chain, N.getOperand(N.getNumOperands()-1)); - Ops.push_back(Chain); + + // If this is a load or store with a zero offset, we may be able to + // fold an add-immediate into the memory operation. + if (!isa(N->getOperand(FirstOp)) || + N->getConstantOperandVal(FirstOp) != 0) + continue; + + SDValue Base = N->getOperand(FirstOp + 1); + if (!Base.isMachineOpcode()) + continue; + + unsigned Flags = 0; + bool ReplaceFlags = true; + + // When the feeding operation is an add-immediate of some sort, + // determine whether we need to add relocation information to the + // target flags on the immediate operand when we fold it into the + // load instruction. + // + // For something like ADDItocL, the relocation information is + // inferred from the opcode; when we process it in the AsmPrinter, + // we add the necessary relocation there. A load, though, can receive + // relocation from various flavors of ADDIxxx, so we need to carry + // the relocation information in the target flags. + switch (Base.getMachineOpcode()) { + default: continue; + + case PPC::ADDI8: + case PPC::ADDI: + // In some cases (such as TLS) the relocation information + // is already in place on the operand, so copying the operand + // is sufficient. + ReplaceFlags = false; + // For these cases, the immediate may not be divisible by 4, in + // which case the fold is illegal for DS-form instructions. (The + // other cases provide aligned addresses and are always safe.) + if ((StorageOpcode == PPC::LWA || + StorageOpcode == PPC::LD || + StorageOpcode == PPC::STD) && + (!isa(Base.getOperand(1)) || + Base.getConstantOperandVal(1) % 4 != 0)) + continue; + break; + case PPC::ADDIdtprelL: + Flags = PPCII::MO_DTPREL_LO; + break; + case PPC::ADDItlsldL: + Flags = PPCII::MO_TLSLD_LO; + break; + case PPC::ADDItocL: + Flags = PPCII::MO_TOC_LO; + break; } - - ResNode = CurDAG->getTargetNode(PPC::BL, MVT::Other, MVT::Flag, Ops); - - Chain = SDOperand(ResNode, 0); - InFlag = SDOperand(ResNode, 1); - SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 0, Chain.Val, - Chain.ResNo); - SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 1, InFlag.Val, - InFlag.ResNo); - Result = SDOperand(ResNode, N.ResNo); - return; + + // We found an opportunity. Reverse the operands from the add + // immediate and substitute them into the load or store. If + // needed, update the target flags for the immediate operand to + // reflect the necessary relocation information. + DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: "); + DEBUG(Base->dump(CurDAG)); + DEBUG(dbgs() << "\nN: "); + DEBUG(N->dump(CurDAG)); + DEBUG(dbgs() << "\n"); + + SDValue ImmOpnd = Base.getOperand(1); + + // If the relocation information isn't already present on the + // immediate operand, add it now. + if (ReplaceFlags) { + if (GlobalAddressSDNode *GA = dyn_cast(ImmOpnd)) { + SDLoc dl(GA); + const GlobalValue *GV = GA->getGlobal(); + // We can't perform this optimization for data whose alignment + // is insufficient for the instruction encoding. + if (GV->getAlignment() < 4 && + (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD || + StorageOpcode == PPC::LWA)) { + DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n"); + continue; + } + ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags); + } else if (ConstantPoolSDNode *CP = + dyn_cast(ImmOpnd)) { + const Constant *C = CP->getConstVal(); + ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64, + CP->getAlignment(), + 0, Flags); + } + } + + if (FirstOp == 1) // Store + (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd, + Base.getOperand(0), N->getOperand(3)); + else // Load + (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0), + N->getOperand(2)); + + // The add-immediate may now be dead, in which case remove it. + if (Base.getNode()->use_empty()) + CurDAG->RemoveDeadNode(Base.getNode()); } - std::cerr << "Cannot yet select: "; - N.Val->dump(CurDAG); - std::cerr << '\n'; - abort(); } -/// createPPCISelDag - This pass converts a legalized DAG into a +/// createPPCISelDag - This pass converts a legalized DAG into a /// PowerPC-specific DAG, ready for instruction scheduling. /// FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) { return new PPCDAGToDAGISel(TM); } +static void initializePassOnce(PassRegistry &Registry) { + const char *Name = "PowerPC DAG->DAG Pattern Instruction Selection"; + PassInfo *PI = new PassInfo(Name, "ppc-codegen", &SelectionDAGISel::ID, 0, + false, false); + Registry.registerPass(*PI, true); +} + +void llvm::initializePPCDAGToDAGISelPass(PassRegistry &Registry) { + CALL_ONCE_INITIALIZATION(initializePassOnce); +} +