X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FPowerPC%2FPPCISelDAGToDAG.cpp;h=a00f686adce1d6ad10661abab7bfdfd5a6b45f70;hb=fef904d0e824a2c587f8c1063b6c4fbf47fec898;hp=35ab9de1134855f98652a1086352f47075c56916;hpb=ea859be53ca13a1547c4675549946b74dc3c6f41;p=oota-llvm.git diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 35ab9de1134..a00f686adce 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by Chris Lattner and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -14,24 +14,22 @@ #define DEBUG_TYPE "ppc-codegen" #include "PPC.h" -#include "PPCPredicates.h" #include "PPCTargetMachine.h" -#include "PPCISelLowering.h" -#include "PPCHazardRecognizers.h" +#include "MCTargetDesc/PPCPredicates.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Constants.h" +#include "llvm/Function.h" #include "llvm/GlobalValue.h" #include "llvm/Intrinsics.h" #include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" -#include "llvm/Support/Compiler.h" -#include -#include +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; namespace { @@ -39,42 +37,44 @@ namespace { /// PPCDAGToDAGISel - PPC specific code to select PPC machine /// instructions for SelectionDAG operations. /// - class VISIBILITY_HIDDEN PPCDAGToDAGISel : public SelectionDAGISel { - PPCTargetMachine &TM; - PPCTargetLowering PPCLowering; + class PPCDAGToDAGISel : public SelectionDAGISel { + const PPCTargetMachine &TM; + const PPCTargetLowering &PPCLowering; + const PPCSubtarget &PPCSubTarget; unsigned GlobalBaseReg; public: - PPCDAGToDAGISel(PPCTargetMachine &tm) - : SelectionDAGISel(PPCLowering), TM(tm), - PPCLowering(*TM.getTargetLowering()) {} - - virtual bool runOnFunction(Function &Fn) { + explicit PPCDAGToDAGISel(PPCTargetMachine &tm) + : SelectionDAGISel(tm), TM(tm), + PPCLowering(*TM.getTargetLowering()), + PPCSubTarget(*TM.getSubtargetImpl()) {} + + virtual bool runOnMachineFunction(MachineFunction &MF) { // Make sure we re-emit a set of the global base reg if necessary GlobalBaseReg = 0; - SelectionDAGISel::runOnFunction(Fn); - - InsertVRSaveCode(Fn); + SelectionDAGISel::runOnMachineFunction(MF); + + InsertVRSaveCode(MF); return true; } - + /// getI32Imm - Return a target constant with the specified value, of type /// i32. - inline SDOperand getI32Imm(unsigned Imm) { + inline SDValue getI32Imm(unsigned Imm) { return CurDAG->getTargetConstant(Imm, MVT::i32); } /// getI64Imm - Return a target constant with the specified value, of type /// i64. - inline SDOperand getI64Imm(uint64_t Imm) { + inline SDValue getI64Imm(uint64_t Imm) { return CurDAG->getTargetConstant(Imm, MVT::i64); } - + /// getSmallIPtrImm - Return a target constant of pointer type. - inline SDOperand getSmallIPtrImm(unsigned Imm) { + inline SDValue getSmallIPtrImm(unsigned Imm) { return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy()); } - - /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s + + /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s /// with any number of 0s on either side. The 1s are allowed to wrap from /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. /// 0x0F0F0000 is not, since all 1s are not contiguous. @@ -83,155 +83,120 @@ namespace { /// isRotateAndMask - Returns true if Mask and Shift can be folded into a /// rotate and mask opcode and mask operation. - static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask, + static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask, unsigned &SH, unsigned &MB, unsigned &ME); - + /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC /// base register. Return the virtual register that holds this value. SDNode *getGlobalBaseReg(); - + // Select - Convert the specified operand from a target-independent to a // target-specific node if it hasn't already been changed. - SDNode *Select(SDOperand Op); - + SDNode *Select(SDNode *N); + SDNode *SelectBitfieldInsert(SDNode *N); /// SelectCC - Select a comparison of the specified values with the /// specified condition code, returning the CR# of the expression. - SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC); + SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl); /// SelectAddrImm - Returns true if the address N can be represented by /// a base register plus a signed 16-bit displacement [r+imm]. - bool SelectAddrImm(SDOperand Op, SDOperand N, SDOperand &Disp, - SDOperand &Base) { + bool SelectAddrImm(SDValue N, SDValue &Disp, + SDValue &Base) { return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG); } - + /// SelectAddrImmOffs - Return true if the operand is valid for a preinc /// immediate field. Because preinc imms have already been validated, just /// accept it. - bool SelectAddrImmOffs(SDOperand Op, SDOperand N, SDOperand &Out) const { + bool SelectAddrImmOffs(SDValue N, SDValue &Out) const { + if (isa(N) || N.getOpcode() == PPCISD::Lo || + N.getOpcode() == ISD::TargetGlobalAddress) { + Out = N; + return true; + } + + return false; + } + + /// SelectAddrIdxOffs - Return true if the operand is valid for a preinc + /// index field. Because preinc imms have already been validated, just + /// accept it. + bool SelectAddrIdxOffs(SDValue N, SDValue &Out) const { + if (isa(N) || N.getOpcode() == PPCISD::Lo || + N.getOpcode() == ISD::TargetGlobalAddress) + return false; + Out = N; return true; } - + /// SelectAddrIdx - Given the specified addressed, check to see if it can be /// represented as an indexed [r+r] operation. Returns false if it can /// be represented by [r+imm], which are preferred. - bool SelectAddrIdx(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &Index) { + bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) { return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG); } - + /// SelectAddrIdxOnly - Given the specified addressed, force it to be /// represented as an indexed [r+r] operation. - bool SelectAddrIdxOnly(SDOperand Op, SDOperand N, SDOperand &Base, - SDOperand &Index) { + bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) { return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG); } /// SelectAddrImmShift - Returns true if the address N can be represented by /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable /// for use by STD and friends. - bool SelectAddrImmShift(SDOperand Op, SDOperand N, SDOperand &Disp, - SDOperand &Base) { + bool SelectAddrImmShift(SDValue N, SDValue &Disp, SDValue &Base) { return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG); } - + /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for - /// inline asm expressions. - virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op, + /// inline asm expressions. It is always correct to compute the value into + /// a register. The case of adding a (possibly relocatable) constant to a + /// register can be improved, but it is wrong to substitute Reg+Reg for + /// Reg in an asm, because the load or store opcode would have to change. + virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, - std::vector &OutOps, - SelectionDAG &DAG) { - SDOperand Op0, Op1; - switch (ConstraintCode) { - default: return true; - case 'm': // memory - if (!SelectAddrIdx(Op, Op, Op0, Op1)) - SelectAddrImm(Op, Op, Op0, Op1); - break; - case 'o': // offsetable - if (!SelectAddrImm(Op, Op, Op0, Op1)) { - Op0 = Op; - AddToISelQueue(Op0); // r+0. - Op1 = getSmallIPtrImm(0); - } - break; - case 'v': // not offsetable - SelectAddrIdxOnly(Op, Op, Op0, Op1); - break; - } - - OutOps.push_back(Op0); - OutOps.push_back(Op1); + std::vector &OutOps) { + OutOps.push_back(Op); return false; } - - SDOperand BuildSDIVSequence(SDNode *N); - SDOperand BuildUDIVSequence(SDNode *N); - - /// InstructionSelectBasicBlock - This callback is invoked by - /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. - virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); - - void InsertVRSaveCode(Function &Fn); + + void InsertVRSaveCode(MachineFunction &MF); virtual const char *getPassName() const { return "PowerPC DAG->DAG Pattern Instruction Selection"; - } - - /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for - /// this target when scheduling the DAG. - virtual HazardRecognizer *CreateTargetHazardRecognizer() { - // Should use subtarget info to pick the right hazard recognizer. For - // now, always return a PPC970 recognizer. - const TargetInstrInfo *II = PPCLowering.getTargetMachine().getInstrInfo(); - assert(II && "No InstrInfo?"); - return new PPCHazardRecognizer970(*II); } // Include the pieces autogenerated from the target description. #include "PPCGenDAGISel.inc" - + private: - SDNode *SelectSETCC(SDOperand Op); + SDNode *SelectSETCC(SDNode *N); }; } -/// InstructionSelectBasicBlock - This callback is invoked by -/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. -void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { - DEBUG(BB->dump()); - - // Select target instructions for the DAG. - DAG.setRoot(SelectRoot(DAG.getRoot())); - DAG.RemoveDeadNodes(); - - // Emit machine code to BB. - ScheduleAndEmitDAG(DAG); -} - /// InsertVRSaveCode - Once the entire function has been instruction selected, /// all virtual registers are created and all machine instructions are built, /// check to see if we need to save/restore VRSAVE. If so, do it. -void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) { +void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) { // Check to see if this function uses vector registers, which means we have to - // save and restore the VRSAVE register and update it with the regs we use. + // save and restore the VRSAVE register and update it with the regs we use. // - // In this case, there will be virtual registers of vector type type created + // In this case, there will be virtual registers of vector type created // by the scheduler. Detect them now. - MachineFunction &Fn = MachineFunction::get(&F); - SSARegMap *RegMap = Fn.getSSARegMap(); bool HasVectorVReg = false; - for (unsigned i = MRegisterInfo::FirstVirtualRegister, - e = RegMap->getLastVirtReg()+1; i != e; ++i) - if (RegMap->getRegClass(i) == &PPC::VRRCRegClass) { + for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) { + unsigned Reg = TargetRegisterInfo::index2VirtReg(i); + if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) { HasVectorVReg = true; break; } + } if (!HasVectorVReg) return; // nothing to do. - + // If we have a vector register, we want to emit code into the entry and exit // blocks to save and restore the VRSAVE register. We do this here (instead // of marking all vector instructions as clobbering VRSAVE) for two reasons: @@ -244,34 +209,36 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) { // Create two vregs - one to hold the VRSAVE register that is live-in to the // function and one for the value after having bits or'd into it. - unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass); - unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass); - + unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); + unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); + const TargetInstrInfo &TII = *TM.getInstrInfo(); MachineBasicBlock &EntryBB = *Fn.begin(); + DebugLoc dl; // Emit the following code into the entry block: // InVRSAVE = MFVRSAVE // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE // MTVRSAVE UpdatedVRSAVE MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point - BuildMI(EntryBB, IP, TII.get(PPC::MFVRSAVE), InVRSAVE); - BuildMI(EntryBB, IP, TII.get(PPC::UPDATE_VRSAVE), UpdatedVRSAVE).addReg(InVRSAVE); - BuildMI(EntryBB, IP, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE); - + BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE); + BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE), + UpdatedVRSAVE).addReg(InVRSAVE); + BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE); + // Find all return blocks, outputting a restore in each epilog. for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { - if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) { + if (!BB->empty() && BB->back().isReturn()) { IP = BB->end(); --IP; - + // Skip over all terminator instructions, which are part of the return // sequence. MachineBasicBlock::iterator I2 = IP; - while (I2 != BB->begin() && TII.isTerminatorInstr((--I2)->getOpcode())) + while (I2 != BB->begin() && (--I2)->isTerminator()) IP = I2; - + // Emit: MTVRSAVE InVRSave - BuildMI(*BB, IP, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE); - } + BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE); + } } } @@ -283,21 +250,22 @@ SDNode *PPCDAGToDAGISel::getGlobalBaseReg() { if (!GlobalBaseReg) { const TargetInstrInfo &TII = *TM.getInstrInfo(); // Insert the set of GlobalBaseReg into the first MBB of the function - MachineBasicBlock &FirstMBB = BB->getParent()->front(); + MachineBasicBlock &FirstMBB = MF->front(); MachineBasicBlock::iterator MBBI = FirstMBB.begin(); - SSARegMap *RegMap = BB->getParent()->getSSARegMap(); + DebugLoc dl; if (PPCLowering.getPointerTy() == MVT::i32) { - GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass); - BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR), PPC::LR); - BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR), GlobalBaseReg); + GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); + BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR)); + BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); } else { - GlobalBaseReg = RegMap->createVirtualRegister(PPC::G8RCRegisterClass); - BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR8), PPC::LR8); - BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg); + GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RCRegClass); + BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8)); + BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg); } } - return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy()).Val; + return CurDAG->getRegister(GlobalBaseReg, + PPCLowering.getPointerTy()).getNode(); } /// isIntS16Immediate - This method tests to see if the node is either a 32-bit @@ -308,15 +276,15 @@ static bool isIntS16Immediate(SDNode *N, short &Imm) { if (N->getOpcode() != ISD::Constant) return false; - Imm = (short)cast(N)->getValue(); + Imm = (short)cast(N)->getZExtValue(); if (N->getValueType(0) == MVT::i32) - return Imm == (int32_t)cast(N)->getValue(); + return Imm == (int32_t)cast(N)->getZExtValue(); else - return Imm == (int64_t)cast(N)->getValue(); + return Imm == (int64_t)cast(N)->getZExtValue(); } -static bool isIntS16Immediate(SDOperand Op, short &Imm) { - return isIntS16Immediate(Op.Val, Imm); +static bool isIntS16Immediate(SDValue Op, short &Imm) { + return isIntS16Immediate(Op.getNode(), Imm); } @@ -324,7 +292,7 @@ static bool isIntS16Immediate(SDOperand Op, short &Imm) { /// operand. If so Imm will receive the 32-bit value. static bool isInt32Immediate(SDNode *N, unsigned &Imm) { if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { - Imm = cast(N)->getValue(); + Imm = cast(N)->getZExtValue(); return true; } return false; @@ -334,7 +302,7 @@ static bool isInt32Immediate(SDNode *N, unsigned &Imm) { /// operand. If so Imm will receive the 64-bit value. static bool isInt64Immediate(SDNode *N, uint64_t &Imm) { if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { - Imm = cast(N)->getValue(); + Imm = cast(N)->getZExtValue(); return true; } return false; @@ -342,8 +310,8 @@ static bool isInt64Immediate(SDNode *N, uint64_t &Imm) { // isInt32Immediate - This method tests to see if a constant operand. // If so Imm will receive the 32 bit value. -static bool isInt32Immediate(SDOperand N, unsigned &Imm) { - return isInt32Immediate(N.Val, Imm); +static bool isInt32Immediate(SDValue N, unsigned &Imm) { + return isInt32Immediate(N.getNode(), Imm); } @@ -351,7 +319,8 @@ static bool isInt32Immediate(SDOperand N, unsigned &Imm) { // opcode and that it has a immediate integer right operand. // If so Imm will receive the 32 bit value. static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { - return N->getOpcode() == Opc && isInt32Immediate(N->getOperand(1).Val, Imm); + return N->getOpcode() == Opc + && isInt32Immediate(N->getOperand(1).getNode(), Imm); } bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) { @@ -375,8 +344,8 @@ bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) { return false; } -bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask, - bool IsShiftMask, unsigned &SH, +bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask, + bool isShiftMask, unsigned &SH, unsigned &MB, unsigned &ME) { // Don't even go down this path for i64, since different logic will be // necessary for rldicl/rldicr/rldimi. @@ -387,17 +356,17 @@ bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask, unsigned Indeterminant = ~0; // bit mask marking indeterminant results unsigned Opcode = N->getOpcode(); if (N->getNumOperands() != 2 || - !isInt32Immediate(N->getOperand(1).Val, Shift) || (Shift > 31)) + !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31)) return false; - + if (Opcode == ISD::SHL) { // apply shift left to mask if it comes first - if (IsShiftMask) Mask = Mask << Shift; + if (isShiftMask) Mask = Mask << Shift; // determine which bits are made indeterminant by shift Indeterminant = ~(0xFFFFFFFFu << Shift); - } else if (Opcode == ISD::SRL) { + } else if (Opcode == ISD::SRL) { // apply shift right to mask if it comes first - if (IsShiftMask) Mask = Mask >> Shift; + if (isShiftMask) Mask = Mask >> Shift; // determine which bits are made indeterminant by shift Indeterminant = ~(0xFFFFFFFFu >> Shift); // adjust for the left rotate @@ -407,7 +376,7 @@ bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask, } else { return false; } - + // if the mask doesn't intersect any Indeterminant bits if (Mask && !(Mask & Indeterminant)) { SH = Shift & 31; @@ -420,16 +389,17 @@ bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask, /// SelectBitfieldInsert - turn an or of two masked values into /// the rotate left word immediate then mask insert (rlwimi) instruction. SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { - SDOperand Op0 = N->getOperand(0); - SDOperand Op1 = N->getOperand(1); - - uint64_t LKZ, LKO, RKZ, RKO; - CurDAG->ComputeMaskedBits(Op0, 0xFFFFFFFFULL, LKZ, LKO); - CurDAG->ComputeMaskedBits(Op1, 0xFFFFFFFFULL, RKZ, RKO); - - unsigned TargetMask = LKZ; - unsigned InsertMask = RKZ; - + SDValue Op0 = N->getOperand(0); + SDValue Op1 = N->getOperand(1); + DebugLoc dl = N->getDebugLoc(); + + APInt LKZ, LKO, RKZ, RKO; + CurDAG->ComputeMaskedBits(Op0, LKZ, LKO); + CurDAG->ComputeMaskedBits(Op1, RKZ, RKO); + + unsigned TargetMask = LKZ.getZExtValue(); + unsigned InsertMask = RKZ.getZExtValue(); + if ((TargetMask | InsertMask) == 0xFFFFFFFF) { unsigned Op0Opc = Op0.getOpcode(); unsigned Op1Opc = Op1.getOpcode(); @@ -457,11 +427,10 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { std::swap(TargetMask, InsertMask); } } - + unsigned MB, ME; if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) { - SDOperand Tmp1, Tmp2, Tmp3; - bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF; + SDValue Tmp1, Tmp2; if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && isInt32Immediate(Op1.getOperand(1), Value)) { @@ -478,14 +447,11 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { Op1 = Op1.getOperand(0); } } - - Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0; - AddToISelQueue(Tmp3); - AddToISelQueue(Op1); + SH &= 31; - SDOperand Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB), + SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; - return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5); + return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5); } } return 0; @@ -493,93 +459,92 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { /// SelectCC - Select a comparison of the specified values with the specified /// condition code, returning the CR# of the expression. -SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS, - ISD::CondCode CC) { +SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, + ISD::CondCode CC, DebugLoc dl) { // Always select the LHS. - AddToISelQueue(LHS); unsigned Opc; - + if (LHS.getValueType() == MVT::i32) { unsigned Imm; if (CC == ISD::SETEQ || CC == ISD::SETNE) { if (isInt32Immediate(RHS, Imm)) { // SETEQ/SETNE comparison with 16-bit immediate, fold it. - if (isUInt16(Imm)) - return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS, - getI32Imm(Imm & 0xFFFF)), 0); + if (isUInt<16>(Imm)) + return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, + getI32Imm(Imm & 0xFFFF)), 0); // If this is a 16-bit signed immediate, fold it. - if (isInt16((int)Imm)) - return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS, - getI32Imm(Imm & 0xFFFF)), 0); - + if (isInt<16>((int)Imm)) + return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS, + getI32Imm(Imm & 0xFFFF)), 0); + // For non-equality comparisons, the default code would materialize the // constant, then compare against it, like this: // lis r2, 4660 - // ori r2, r2, 22136 + // ori r2, r2, 22136 // cmpw cr0, r3, r2 // Since we are just comparing for equality, we can emit this instead: // xoris r0,r3,0x1234 // cmplwi cr0,r0,0x5678 // beq cr0,L6 - SDOperand Xor(CurDAG->getTargetNode(PPC::XORIS, MVT::i32, LHS, - getI32Imm(Imm >> 16)), 0); - return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, Xor, - getI32Imm(Imm & 0xFFFF)), 0); + SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS, + getI32Imm(Imm >> 16)), 0); + return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor, + getI32Imm(Imm & 0xFFFF)), 0); } Opc = PPC::CMPLW; } else if (ISD::isUnsignedIntSetCC(CC)) { - if (isInt32Immediate(RHS, Imm) && isUInt16(Imm)) - return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS, - getI32Imm(Imm & 0xFFFF)), 0); + if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm)) + return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, + getI32Imm(Imm & 0xFFFF)), 0); Opc = PPC::CMPLW; } else { short SImm; if (isIntS16Immediate(RHS, SImm)) - return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS, - getI32Imm((int)SImm & 0xFFFF)), + return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS, + getI32Imm((int)SImm & 0xFFFF)), 0); Opc = PPC::CMPW; } } else if (LHS.getValueType() == MVT::i64) { uint64_t Imm; if (CC == ISD::SETEQ || CC == ISD::SETNE) { - if (isInt64Immediate(RHS.Val, Imm)) { + if (isInt64Immediate(RHS.getNode(), Imm)) { // SETEQ/SETNE comparison with 16-bit immediate, fold it. - if (isUInt16(Imm)) - return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS, - getI32Imm(Imm & 0xFFFF)), 0); + if (isUInt<16>(Imm)) + return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS, + getI32Imm(Imm & 0xFFFF)), 0); // If this is a 16-bit signed immediate, fold it. - if (isInt16(Imm)) - return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS, - getI32Imm(Imm & 0xFFFF)), 0); - + if (isInt<16>(Imm)) + return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS, + getI32Imm(Imm & 0xFFFF)), 0); + // For non-equality comparisons, the default code would materialize the // constant, then compare against it, like this: // lis r2, 4660 - // ori r2, r2, 22136 + // ori r2, r2, 22136 // cmpd cr0, r3, r2 // Since we are just comparing for equality, we can emit this instead: // xoris r0,r3,0x1234 // cmpldi cr0,r0,0x5678 // beq cr0,L6 - if (isUInt32(Imm)) { - SDOperand Xor(CurDAG->getTargetNode(PPC::XORIS8, MVT::i64, LHS, - getI64Imm(Imm >> 16)), 0); - return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, Xor, - getI64Imm(Imm & 0xFFFF)), 0); + if (isUInt<32>(Imm)) { + SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS, + getI64Imm(Imm >> 16)), 0); + return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor, + getI64Imm(Imm & 0xFFFF)), 0); } } Opc = PPC::CMPLD; } else if (ISD::isUnsignedIntSetCC(CC)) { - if (isInt64Immediate(RHS.Val, Imm) && isUInt16(Imm)) - return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS, - getI64Imm(Imm & 0xFFFF)), 0); + if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm)) + return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS, + getI64Imm(Imm & 0xFFFF)), 0); Opc = PPC::CMPLD; } else { short SImm; if (isIntS16Immediate(RHS, SImm)) - return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS, - getI64Imm(SImm & 0xFFFF)), + return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS, + getI64Imm(SImm & 0xFFFF)), 0); Opc = PPC::CMPD; } @@ -589,198 +554,224 @@ SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS, assert(LHS.getValueType() == MVT::f64 && "Unknown vt!"); Opc = PPC::FCMPUD; } - AddToISelQueue(RHS); - return SDOperand(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0); + return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0); } static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { switch (CC) { - default: assert(0 && "Unknown condition!"); abort(); - case ISD::SETOEQ: // FIXME: This is incorrect see PR642. case ISD::SETUEQ: + case ISD::SETONE: + case ISD::SETOLE: + case ISD::SETOGE: + llvm_unreachable("Should be lowered by legalize!"); + default: llvm_unreachable("Unknown condition!"); + case ISD::SETOEQ: case ISD::SETEQ: return PPC::PRED_EQ; - case ISD::SETONE: // FIXME: This is incorrect see PR642. case ISD::SETUNE: case ISD::SETNE: return PPC::PRED_NE; - case ISD::SETOLT: // FIXME: This is incorrect see PR642. - case ISD::SETULT: + case ISD::SETOLT: case ISD::SETLT: return PPC::PRED_LT; - case ISD::SETOLE: // FIXME: This is incorrect see PR642. case ISD::SETULE: case ISD::SETLE: return PPC::PRED_LE; - case ISD::SETOGT: // FIXME: This is incorrect see PR642. - case ISD::SETUGT: + case ISD::SETOGT: case ISD::SETGT: return PPC::PRED_GT; - case ISD::SETOGE: // FIXME: This is incorrect see PR642. case ISD::SETUGE: case ISD::SETGE: return PPC::PRED_GE; - case ISD::SETO: return PPC::PRED_NU; case ISD::SETUO: return PPC::PRED_UN; + // These two are invalid for floating point. Assume we have int. + case ISD::SETULT: return PPC::PRED_LT; + case ISD::SETUGT: return PPC::PRED_GT; } } /// getCRIdxForSetCC - Return the index of the condition register field /// associated with the SetCC condition, and whether or not the field is /// treated as inverted. That is, lt = 0; ge = 0 inverted. -static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) { +/// +/// If this returns with Other != -1, then the returned comparison is an or of +/// two simpler comparisons. In this case, Invert is guaranteed to be false. +static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) { + Invert = false; + Other = -1; switch (CC) { - default: assert(0 && "Unknown condition!"); abort(); - case ISD::SETOLT: // FIXME: This is incorrect see PR642. - case ISD::SETULT: - case ISD::SETLT: Inv = false; return 0; - case ISD::SETOGE: // FIXME: This is incorrect see PR642. + default: llvm_unreachable("Unknown condition!"); + case ISD::SETOLT: + case ISD::SETLT: return 0; // Bit #0 = SETOLT + case ISD::SETOGT: + case ISD::SETGT: return 1; // Bit #1 = SETOGT + case ISD::SETOEQ: + case ISD::SETEQ: return 2; // Bit #2 = SETOEQ + case ISD::SETUO: return 3; // Bit #3 = SETUO case ISD::SETUGE: - case ISD::SETGE: Inv = true; return 0; - case ISD::SETOGT: // FIXME: This is incorrect see PR642. - case ISD::SETUGT: - case ISD::SETGT: Inv = false; return 1; - case ISD::SETOLE: // FIXME: This is incorrect see PR642. + case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE case ISD::SETULE: - case ISD::SETLE: Inv = true; return 1; - case ISD::SETOEQ: // FIXME: This is incorrect see PR642. - case ISD::SETUEQ: - case ISD::SETEQ: Inv = false; return 2; - case ISD::SETONE: // FIXME: This is incorrect see PR642. + case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE case ISD::SETUNE: - case ISD::SETNE: Inv = true; return 2; - case ISD::SETO: Inv = true; return 3; - case ISD::SETUO: Inv = false; return 3; + case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE + case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO + case ISD::SETUEQ: + case ISD::SETOGE: + case ISD::SETOLE: + case ISD::SETONE: + llvm_unreachable("Invalid branch code: should be expanded by legalize"); + // These are invalid for floating point. Assume integer. + case ISD::SETULT: return 0; + case ISD::SETUGT: return 1; } - return 0; } -SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) { - SDNode *N = Op.Val; +SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) { + DebugLoc dl = N->getDebugLoc(); unsigned Imm; ISD::CondCode CC = cast(N->getOperand(2))->get(); + EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy(); + bool isPPC64 = (PtrVT == MVT::i64); + if (isInt32Immediate(N->getOperand(1), Imm)) { // We can codegen setcc op, imm very efficiently compared to a brcond. // Check for those cases here. // setcc op, 0 if (Imm == 0) { - SDOperand Op = N->getOperand(0); - AddToISelQueue(Op); + SDValue Op = N->getOperand(0); switch (CC) { default: break; case ISD::SETEQ: { - Op = SDOperand(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0); - SDOperand Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) }; + Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0); + SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } case ISD::SETNE: { - SDOperand AD = - SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, - Op, getI32Imm(~0U)), 0); - return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, + if (isPPC64) break; + SDValue AD = + SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, + Op, getI32Imm(~0U)), 0); + return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1)); } case ISD::SETLT: { - SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; + SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } case ISD::SETGT: { - SDOperand T = - SDOperand(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0); - T = SDOperand(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0); - SDOperand Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; + SDValue T = + SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0); + T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0); + SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } } } else if (Imm == ~0U) { // setcc op, -1 - SDOperand Op = N->getOperand(0); - AddToISelQueue(Op); + SDValue Op = N->getOperand(0); switch (CC) { default: break; case ISD::SETEQ: - Op = SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, - Op, getI32Imm(1)), 0); - return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, - SDOperand(CurDAG->getTargetNode(PPC::LI, MVT::i32, - getI32Imm(0)), 0), - Op.getValue(1)); + if (isPPC64) break; + Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, + Op, getI32Imm(1)), 0); + return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, + SDValue(CurDAG->getMachineNode(PPC::LI, dl, + MVT::i32, + getI32Imm(0)), 0), + Op.getValue(1)); case ISD::SETNE: { - Op = SDOperand(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0); - SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, - Op, getI32Imm(~0U)); - return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0), - Op, SDOperand(AD, 1)); + if (isPPC64) break; + Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0); + SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, + Op, getI32Imm(~0U)); + return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0), + Op, SDValue(AD, 1)); } case ISD::SETLT: { - SDOperand AD = SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op, - getI32Imm(1)), 0); - SDOperand AN = SDOperand(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, - Op), 0); - SDOperand Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; + SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op, + getI32Imm(1)), 0); + SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD, + Op), 0); + SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } case ISD::SETGT: { - SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; - Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0); - return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, + SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; + Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), + 0); + return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1)); } } } } - + bool Inv; - unsigned Idx = getCRIdxForSetCC(CC, Inv); - SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC); - SDOperand IntCR; - + int OtherCondIdx; + unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx); + SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl); + SDValue IntCR; + // Force the ccreg into CR7. - SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32); - - SDOperand InFlag(0, 0); // Null incoming flag value. - CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg, + SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32); + + SDValue InFlag(0, 0); // Null incoming flag value. + CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg, InFlag).getValue(1); - - if (TLI.getTargetMachine().getSubtarget().isGigaProcessor()) - IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, - CCReg), 0); - else - IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0); - - SDOperand Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31), + + if (PPCSubTarget.hasMFOCRF() && OtherCondIdx == -1) + IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg, + CCReg), 0); + else + IntCR = SDValue(CurDAG->getMachineNode(PPC::MFCRpseud, dl, MVT::i32, + CR7Reg, CCReg), 0); + + SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31), getI32Imm(31), getI32Imm(31) }; - if (!Inv) { + if (OtherCondIdx == -1 && !Inv) return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); - } else { - SDOperand Tmp = - SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0); + + // Get the specified bit. + SDValue Tmp = + SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0); + if (Inv) { + assert(OtherCondIdx == -1 && "Can't have split plus negation"); return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1)); } + + // Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT. + // We already got the bit for the first part of the comparison (e.g. SETULE). + + // Get the other bit of the comparison. + Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31); + SDValue OtherCond = + SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0); + + return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond); } // Select - Convert the specified operand from a target-independent to a // target-specific node if it hasn't already been changed. -SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { - SDNode *N = Op.Val; - if (N->getOpcode() >= ISD::BUILTIN_OP_END && - N->getOpcode() < PPCISD::FIRST_NUMBER) +SDNode *PPCDAGToDAGISel::Select(SDNode *N) { + DebugLoc dl = N->getDebugLoc(); + if (N->isMachineOpcode()) return NULL; // Already selected. switch (N->getOpcode()) { default: break; - + case ISD::Constant: { if (N->getValueType(0) == MVT::i64) { // Get 64 bit value. - int64_t Imm = cast(N)->getValue(); + int64_t Imm = cast(N)->getZExtValue(); // Assume no remaining bits. unsigned Remainder = 0; // Assume no shift required. unsigned Shift = 0; - + // If it can't be represented as a 32 bit value. - if (!isInt32(Imm)) { + if (!isInt<32>(Imm)) { Shift = CountTrailingZeros_64(Imm); int64_t ImmSh = static_cast(Imm) >> Shift; - + // If the shifted value fits 32 bits. - if (isInt32(ImmSh)) { + if (isInt<32>(ImmSh)) { // Go with the shifted value. Imm = ImmSh; } else { @@ -790,134 +781,134 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { Imm >>= 32; } } - + // Intermediate operand. SDNode *Result; // Handle first 32 bits. unsigned Lo = Imm & 0xFFFF; unsigned Hi = (Imm >> 16) & 0xFFFF; - + // Simple value. - if (isInt16(Imm)) { + if (isInt<16>(Imm)) { // Just the Lo bits. - Result = CurDAG->getTargetNode(PPC::LI8, MVT::i64, getI32Imm(Lo)); + Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo)); } else if (Lo) { // Handle the Hi bits. unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8; - Result = CurDAG->getTargetNode(OpC, MVT::i64, getI32Imm(Hi)); + Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi)); // And Lo bits. - Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64, - SDOperand(Result, 0), getI32Imm(Lo)); + Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, + SDValue(Result, 0), getI32Imm(Lo)); } else { // Just the Hi bits. - Result = CurDAG->getTargetNode(PPC::LIS8, MVT::i64, getI32Imm(Hi)); + Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi)); } - + // If no shift, we're done. if (!Shift) return Result; // Shift for next step if the upper 32-bits were not zero. if (Imm) { - Result = CurDAG->getTargetNode(PPC::RLDICR, MVT::i64, - SDOperand(Result, 0), - getI32Imm(Shift), getI32Imm(63 - Shift)); + Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, + SDValue(Result, 0), + getI32Imm(Shift), + getI32Imm(63 - Shift)); } // Add in the last bits as required. if ((Hi = (Remainder >> 16) & 0xFFFF)) { - Result = CurDAG->getTargetNode(PPC::ORIS8, MVT::i64, - SDOperand(Result, 0), getI32Imm(Hi)); - } + Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64, + SDValue(Result, 0), getI32Imm(Hi)); + } if ((Lo = Remainder & 0xFFFF)) { - Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64, - SDOperand(Result, 0), getI32Imm(Lo)); + Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, + SDValue(Result, 0), getI32Imm(Lo)); } - + return Result; } break; } - + case ISD::SETCC: - return SelectSETCC(Op); + return SelectSETCC(N); case PPCISD::GlobalBaseReg: return getGlobalBaseReg(); - + case ISD::FrameIndex: { int FI = cast(N)->getIndex(); - SDOperand TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType()); - unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8; + SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0)); + unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8; if (N->hasOneUse()) - return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI, + return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), TFI, + getSmallIPtrImm(0)); + return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI, getSmallIPtrImm(0)); - return CurDAG->getTargetNode(Opc, Op.getValueType(), TFI, - getSmallIPtrImm(0)); } case PPCISD::MFCR: { - SDOperand InFlag = N->getOperand(1); - AddToISelQueue(InFlag); + SDValue InFlag = N->getOperand(1); // Use MFOCRF if supported. - if (TLI.getTargetMachine().getSubtarget().isGigaProcessor()) - return CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, - N->getOperand(0), InFlag); + if (PPCSubTarget.hasMFOCRF()) + return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, + N->getOperand(0), InFlag); else - return CurDAG->getTargetNode(PPC::MFCR, MVT::i32, InFlag); + return CurDAG->getMachineNode(PPC::MFCRpseud, dl, MVT::i32, + N->getOperand(0), InFlag); } - + case ISD::SDIV: { // FIXME: since this depends on the setting of the carry flag from the srawi // we should really be making notes about that for the scheduler. - // FIXME: It sure would be nice if we could cheaply recognize the + // FIXME: It sure would be nice if we could cheaply recognize the // srl/add/sra pattern the dag combiner will generate for this as // sra/addze rather than having to handle sdiv ourselves. oh well. unsigned Imm; if (isInt32Immediate(N->getOperand(1), Imm)) { - SDOperand N0 = N->getOperand(0); - AddToISelQueue(N0); + SDValue N0 = N->getOperand(0); if ((signed)Imm > 0 && isPowerOf2_32(Imm)) { SDNode *Op = - CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag, - N0, getI32Imm(Log2_32(Imm))); - return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, - SDOperand(Op, 0), SDOperand(Op, 1)); + CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue, + N0, getI32Imm(Log2_32(Imm))); + return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, + SDValue(Op, 0), SDValue(Op, 1)); } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) { SDNode *Op = - CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag, - N0, getI32Imm(Log2_32(-Imm))); - SDOperand PT = - SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, - SDOperand(Op, 0), SDOperand(Op, 1)), + CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue, + N0, getI32Imm(Log2_32(-Imm))); + SDValue PT = + SDValue(CurDAG->getMachineNode(PPC::ADDZE, dl, MVT::i32, + SDValue(Op, 0), SDValue(Op, 1)), 0); return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT); } } - + // Other cases are autogenerated. break; } - + case ISD::LOAD: { // Handle preincrement loads. - LoadSDNode *LD = cast(Op); - MVT::ValueType LoadedVT = LD->getLoadedVT(); - + LoadSDNode *LD = cast(N); + EVT LoadedVT = LD->getMemoryVT(); + // Normal loads are handled by code generated from the .td file. if (LD->getAddressingMode() != ISD::PRE_INC) break; - - SDOperand Offset = LD->getOffset(); + + SDValue Offset = LD->getOffset(); if (isa(Offset) || Offset.getOpcode() == ISD::TargetGlobalAddress) { - + unsigned Opcode; bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; if (LD->getValueType(0) != MVT::i64) { // Handle PPC32 integer and normal FP loads. - assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load"); - switch (LoadedVT) { - default: assert(0 && "Invalid PPC load type!"); + assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); + switch (LoadedVT.getSimpleVT().SimpleTy) { + default: llvm_unreachable("Invalid PPC load type!"); case MVT::f64: Opcode = PPC::LFDU; break; case MVT::f32: Opcode = PPC::LFSU; break; case MVT::i32: Opcode = PPC::LWZU; break; @@ -927,9 +918,9 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { } } else { assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!"); - assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load"); - switch (LoadedVT) { - default: assert(0 && "Invalid PPC load type!"); + assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); + switch (LoadedVT.getSimpleVT().SimpleTy) { + default: llvm_unreachable("Invalid PPC load type!"); case MVT::i64: Opcode = PPC::LDU; break; case MVT::i32: Opcode = PPC::LWZU8; break; case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; @@ -937,66 +928,91 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { case MVT::i8: Opcode = PPC::LBZU8; break; } } - - SDOperand Chain = LD->getChain(); - SDOperand Base = LD->getBasePtr(); - AddToISelQueue(Chain); - AddToISelQueue(Base); - AddToISelQueue(Offset); - SDOperand Ops[] = { Offset, Base, Chain }; - // FIXME: PPC64 - return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32, - MVT::Other, Ops, 3); + + SDValue Chain = LD->getChain(); + SDValue Base = LD->getBasePtr(); + SDValue Ops[] = { Offset, Base, Chain }; + return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0), + PPCLowering.getPointerTy(), + MVT::Other, Ops, 3); } else { - assert(0 && "R+R preindex loads not supported yet!"); + unsigned Opcode; + bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; + if (LD->getValueType(0) != MVT::i64) { + // Handle PPC32 integer and normal FP loads. + assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); + switch (LoadedVT.getSimpleVT().SimpleTy) { + default: llvm_unreachable("Invalid PPC load type!"); + case MVT::f64: Opcode = PPC::LFDUX; break; + case MVT::f32: Opcode = PPC::LFSUX; break; + case MVT::i32: Opcode = PPC::LWZUX; break; + case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break; + case MVT::i1: + case MVT::i8: Opcode = PPC::LBZUX; break; + } + } else { + assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!"); + assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) && + "Invalid sext update load"); + switch (LoadedVT.getSimpleVT().SimpleTy) { + default: llvm_unreachable("Invalid PPC load type!"); + case MVT::i64: Opcode = PPC::LDUX; break; + case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break; + case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break; + case MVT::i1: + case MVT::i8: Opcode = PPC::LBZUX8; break; + } + } + + SDValue Chain = LD->getChain(); + SDValue Base = LD->getBasePtr(); + SDValue Ops[] = { Offset, Base, Chain }; + return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0), + PPCLowering.getPointerTy(), + MVT::Other, Ops, 3); } } - + case ISD::AND: { unsigned Imm, Imm2, SH, MB, ME; // If this is an and of a value rotated between 0 and 31 bits and then and'd // with a mask, emit rlwinm if (isInt32Immediate(N->getOperand(1), Imm) && - isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) { - SDOperand Val = N->getOperand(0).getOperand(0); - AddToISelQueue(Val); - SDOperand Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; + isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) { + SDValue Val = N->getOperand(0).getOperand(0); + SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } // If this is just a masked value where the input is not handled above, and // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm if (isInt32Immediate(N->getOperand(1), Imm) && - isRunOfOnes(Imm, MB, ME) && + isRunOfOnes(Imm, MB, ME) && N->getOperand(0).getOpcode() != ISD::ROTL) { - SDOperand Val = N->getOperand(0); - AddToISelQueue(Val); - SDOperand Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) }; + SDValue Val = N->getOperand(0); + SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } // AND X, 0 -> 0, not "rlwinm 32". if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) { - AddToISelQueue(N->getOperand(1)); - ReplaceUses(SDOperand(N, 0), N->getOperand(1)); + ReplaceUses(SDValue(N, 0), N->getOperand(1)); return NULL; } // ISD::OR doesn't get all the bitfield insertion fun. // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert - if (isInt32Immediate(N->getOperand(1), Imm) && + if (isInt32Immediate(N->getOperand(1), Imm) && N->getOperand(0).getOpcode() == ISD::OR && isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) { unsigned MB, ME; Imm = ~(Imm^Imm2); if (isRunOfOnes(Imm, MB, ME)) { - AddToISelQueue(N->getOperand(0).getOperand(0)); - AddToISelQueue(N->getOperand(0).getOperand(1)); - SDOperand Ops[] = { N->getOperand(0).getOperand(0), + SDValue Ops[] = { N->getOperand(0).getOperand(0), N->getOperand(0).getOperand(1), getI32Imm(0), getI32Imm(MB),getI32Imm(ME) }; - return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5); + return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5); } } - + // Other cases are autogenerated. break; } @@ -1004,56 +1020,56 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { if (N->getValueType(0) == MVT::i32) if (SDNode *I = SelectBitfieldInsert(N)) return I; - + // Other cases are autogenerated. break; case ISD::SHL: { unsigned Imm, SH, MB, ME; - if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) && + if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) && isRotateAndMask(N, Imm, true, SH, MB, ME)) { - AddToISelQueue(N->getOperand(0).getOperand(0)); - SDOperand Ops[] = { N->getOperand(0).getOperand(0), + SDValue Ops[] = { N->getOperand(0).getOperand(0), getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } - + // Other cases are autogenerated. break; } case ISD::SRL: { unsigned Imm, SH, MB, ME; - if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) && - isRotateAndMask(N, Imm, true, SH, MB, ME)) { - AddToISelQueue(N->getOperand(0).getOperand(0)); - SDOperand Ops[] = { N->getOperand(0).getOperand(0), + if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) && + isRotateAndMask(N, Imm, true, SH, MB, ME)) { + SDValue Ops[] = { N->getOperand(0).getOperand(0), getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); } - + // Other cases are autogenerated. break; } case ISD::SELECT_CC: { ISD::CondCode CC = cast(N->getOperand(4))->get(); - + EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy(); + bool isPPC64 = (PtrVT == MVT::i64); + // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc - if (ConstantSDNode *N1C = dyn_cast(N->getOperand(1))) - if (ConstantSDNode *N2C = dyn_cast(N->getOperand(2))) - if (ConstantSDNode *N3C = dyn_cast(N->getOperand(3))) - if (N1C->isNullValue() && N3C->isNullValue() && - N2C->getValue() == 1ULL && CC == ISD::SETNE && - // FIXME: Implement this optzn for PPC64. - N->getValueType(0) == MVT::i32) { - AddToISelQueue(N->getOperand(0)); - SDNode *Tmp = - CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, - N->getOperand(0), getI32Imm(~0U)); - return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, - SDOperand(Tmp, 0), N->getOperand(0), - SDOperand(Tmp, 1)); - } - - SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC); + if (!isPPC64) + if (ConstantSDNode *N1C = dyn_cast(N->getOperand(1))) + if (ConstantSDNode *N2C = dyn_cast(N->getOperand(2))) + if (ConstantSDNode *N3C = dyn_cast(N->getOperand(3))) + if (N1C->isNullValue() && N3C->isNullValue() && + N2C->getZExtValue() == 1ULL && CC == ISD::SETNE && + // FIXME: Implement this optzn for PPC64. + N->getValueType(0) == MVT::i32) { + SDNode *Tmp = + CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue, + N->getOperand(0), getI32Imm(~0U)); + return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, + SDValue(Tmp, 0), N->getOperand(0), + SDValue(Tmp, 1)); + } + + SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl); unsigned BROpc = getPredicateForSetCC(CC); unsigned SelectCCOp; @@ -1068,49 +1084,48 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { else SelectCCOp = PPC::SELECT_CC_VRRC; - AddToISelQueue(N->getOperand(2)); - AddToISelQueue(N->getOperand(3)); - SDOperand Ops[] = { CCReg, N->getOperand(2), N->getOperand(3), + SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3), getI32Imm(BROpc) }; return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4); } case PPCISD::COND_BRANCH: { - AddToISelQueue(N->getOperand(0)); // Op #0 is the Chain. + // Op #0 is the Chain. // Op #1 is the PPC::PRED_* number. // Op #2 is the CR# // Op #3 is the Dest MBB - AddToISelQueue(N->getOperand(4)); // Op #4 is the Flag. - SDOperand Ops[] = { N->getOperand(1), N->getOperand(2), N->getOperand(3), + // Op #4 is the Flag. + // Prevent PPC::PRED_* from being selected into LI. + SDValue Pred = + getI32Imm(cast(N->getOperand(1))->getZExtValue()); + SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3), N->getOperand(0), N->getOperand(4) }; return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5); } case ISD::BR_CC: { - AddToISelQueue(N->getOperand(0)); ISD::CondCode CC = cast(N->getOperand(1))->get(); - SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC); - SDOperand Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode, + SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); + SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode, N->getOperand(4), N->getOperand(0) }; return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4); } case ISD::BRIND: { // FIXME: Should custom lower this. - SDOperand Chain = N->getOperand(0); - SDOperand Target = N->getOperand(1); - AddToISelQueue(Chain); - AddToISelQueue(Target); + SDValue Chain = N->getOperand(0); + SDValue Target = N->getOperand(1); unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8; - Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Target, - Chain), 0); - return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain); + unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8; + Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target, + Chain), 0); + return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain); } } - - return SelectCode(Op); + + return SelectCode(N); } -/// createPPCISelDag - This pass converts a legalized DAG into a +/// createPPCISelDag - This pass converts a legalized DAG into a /// PowerPC-specific DAG, ready for instruction scheduling. /// FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {