X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FPowerPC%2FPPCInstrFormats.td;h=10ac79b1c2e34eb698ccb75cf07a904b40514f2e;hb=d8242b49b24a46f685599834b6ca33dfbeba9382;hp=cba2aabe7801e0e33d4c5f9110c26682bbce8ebc;hpb=01595c52b32b8e40b87dd9d36753f8e972ab6f74;p=oota-llvm.git

diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
index cba2aabe780..10ac79b1c2e 100644
--- a/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/lib/Target/PowerPC/PPCInstrFormats.td
@@ -6,9 +6,6 @@
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
 // 
 //===----------------------------------------------------------------------===//
-//
-//
-//===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 //
@@ -27,12 +24,35 @@ class I<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
   let OperandList = OL;
   let AsmString = asmstr;
   let Itinerary = itin;
+  
+  /// These fields correspond to the fields in PPCInstrInfo.h.  Any changes to
+  /// these must be reflected there!  See comments there for what these are.
+  bits<1> PPC970_First = 0;
+  bits<1> PPC970_Single = 0;
+  bits<1> PPC970_Cracked = 0;
+  bits<3> PPC970_Unit = 0;
 }
 
+class PPC970_DGroup_First   { bits<1> PPC970_First = 1;  }
+class PPC970_DGroup_Single  { bits<1> PPC970_Single = 1; }
+class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
+class PPC970_MicroCode;
+
+class PPC970_Unit_Pseudo   { bits<3> PPC970_Unit = 0;   }
+class PPC970_Unit_FXU      { bits<3> PPC970_Unit = 1;   }
+class PPC970_Unit_LSU      { bits<3> PPC970_Unit = 2;   }
+class PPC970_Unit_FPU      { bits<3> PPC970_Unit = 3;   }
+class PPC970_Unit_CRU      { bits<3> PPC970_Unit = 4;   }
+class PPC970_Unit_VALU     { bits<3> PPC970_Unit = 5;   }
+class PPC970_Unit_VPERM    { bits<3> PPC970_Unit = 6;   }
+class PPC970_Unit_BRU      { bits<3> PPC970_Unit = 7;   }
+
+
 // 1.7.1 I-Form
 class IForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr,
-            InstrItinClass itin>
+            InstrItinClass itin, list<dag> pattern>
          : I<opcode, OL, asmstr, itin> {
+  let Pattern = pattern;
   bits<24> LI;
 
   let Inst{6-29}  = LI;
@@ -57,23 +77,27 @@ class BForm<bits<6> opcode, bit aa, bit lk, bits<5> bo, bits<2> bicode, dag OL,
 
 // 1.7.4 D-Form
 class DForm_base<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
-                 list<dag> pattern>
-   : I<opcode, OL, asmstr, itin> {
-  let Pattern = pattern;
+                 list<dag> pattern> 
+  : I<opcode, OL, asmstr, itin> {
   bits<5>  A;
   bits<5>  B;
   bits<16> C;
+
+  let Pattern = pattern;
   
   let Inst{6-10}  = A;
   let Inst{11-15} = B;
   let Inst{16-31} = C;
 }
 
-class DForm_1<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
-   : I<opcode, OL, asmstr, itin> {
+class DForm_1<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
+              list<dag> pattern>
+  : I<opcode, OL, asmstr, itin> {
   bits<5>  A;
   bits<16> C;
   bits<5>  B;
+
+  let Pattern = pattern;
   
   let Inst{6-10}  = A;
   let Inst{11-15} = B;
@@ -98,12 +122,13 @@ class DForm_2_r0<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
 }
 
 // Currently we make the use/def reg distinction in ISel, not tablegen
-class DForm_3<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
-  : DForm_1<opcode, OL, asmstr, itin>;
+class DForm_3<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
+              list<dag> pattern>
+  : DForm_1<opcode, OL, asmstr, itin, pattern>;
 
 class DForm_4<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
               list<dag> pattern>
- : I<opcode, OL, asmstr, itin> {
+  : I<opcode, OL, asmstr, itin> {
   bits<5>  B;
   bits<5>  A;
   bits<16> C;
@@ -115,8 +140,9 @@ class DForm_4<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
   let Inst{16-31} = C;
 }
               
-class DForm_4_zero<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
-  : DForm_1<opcode, OL, asmstr, itin> {
+class DForm_4_zero<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
+                   list<dag> pattern>
+  : DForm_1<opcode, OL, asmstr, itin, pattern> {
   let A = 0;
   let B = 0;
   let C = 0;
@@ -149,22 +175,26 @@ class DForm_6_ext<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
   let L = PPC64;
 }
 
-class DForm_8<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
-  : DForm_1<opcode, OL, asmstr, itin> {
+class DForm_8<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
+              list<dag> pattern>
+  : DForm_1<opcode, OL, asmstr, itin, pattern> {
 }
 
-class DForm_9<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
-  : DForm_1<opcode, OL, asmstr, itin> {
+class DForm_9<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
+              list<dag> pattern>
+  : DForm_1<opcode, OL, asmstr, itin, pattern> {
 }
 
 // 1.7.5 DS-Form
 class DSForm_1<bits<6> opcode, bits<2> xo, dag OL, string asmstr,
-               InstrItinClass itin>
+               InstrItinClass itin, list<dag> pattern>
          : I<opcode, OL, asmstr, itin> {
   bits<5>  RST;
   bits<14> DS;
   bits<5>  RA;
 
+  let Pattern = pattern;
+  
   let Inst{6-10}  = RST;
   let Inst{11-15} = RA;
   let Inst{16-29} = DS;
@@ -172,17 +202,19 @@ class DSForm_1<bits<6> opcode, bits<2> xo, dag OL, string asmstr,
 }
 
 class DSForm_2<bits<6> opcode, bits<2> xo, dag OL, string asmstr,
-               InstrItinClass itin>
-  : DSForm_1<opcode, xo, OL, asmstr, itin>;
+               InstrItinClass itin, list<dag> pattern>
+  : DSForm_1<opcode, xo, OL, asmstr, itin, pattern>;
 
 // 1.7.6 X-Form
-class XForm_base_r3xo<bits<6> opcode, bits<10> xo, 
-                      dag OL, string asmstr, InstrItinClass itin>
+class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OL, string asmstr, 
+                      InstrItinClass itin, list<dag> pattern>
   : I<opcode, OL, asmstr, itin> {
   bits<5> RST;
   bits<5> A;
   bits<5> B;
 
+  let Pattern = pattern;
+
   bit RC = 0;    // set by isDOT
 
   let Inst{6-10}  = RST;
@@ -213,8 +245,8 @@ class XForm_base_r3xo_swapped
 
 
 class XForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
-              InstrItinClass itin> 
-  : XForm_base_r3xo<opcode, xo, OL, asmstr, itin>;
+              InstrItinClass itin, list<dag> pattern> 
+  : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern>;
 
 class XForm_6<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
               InstrItinClass itin, list<dag> pattern> 
@@ -223,8 +255,8 @@ class XForm_6<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
 }
 
 class XForm_8<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
-              InstrItinClass itin> 
-  : XForm_base_r3xo<opcode, xo, OL, asmstr, itin>;
+              InstrItinClass itin, list<dag> pattern> 
+  : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern>;
 
 class XForm_10<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
                InstrItinClass itin, list<dag> pattern> 
@@ -278,20 +310,39 @@ class XForm_17<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
 }
 
 class XForm_25<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
-               InstrItinClass itin> 
-  : XForm_base_r3xo<opcode, xo, OL, asmstr, itin> {
+               InstrItinClass itin, list<dag> pattern> 
+  : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> {
 }
 
 class XForm_26<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
                InstrItinClass itin, list<dag> pattern>
-  : XForm_base_r3xo<opcode, xo, OL, asmstr, itin> {
+  : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> {
   let A = 0;
-  let Pattern = pattern;
 }
 
 class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
-               InstrItinClass itin> 
-  : XForm_base_r3xo<opcode, xo, OL, asmstr, itin> {
+               InstrItinClass itin, list<dag> pattern> 
+  : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> {
+}
+
+// DSS_Form - Form X instruction, used for altivec dss* instructions.
+class DSS_Form<bits<10> xo, dag OL, string asmstr, 
+                      InstrItinClass itin, list<dag> pattern>
+  : I<31, OL, asmstr, itin> {
+  bits<1> T;
+  bits<2> STRM;
+  bits<5> A;
+  bits<5> B;
+
+  let Pattern = pattern;
+
+  let Inst{6}     = T;
+  let Inst{7-8}   = 0;
+  let Inst{9-10}  = STRM;
+  let Inst{11-15} = A;
+  let Inst{16-20} = B;
+  let Inst{21-30} = xo;
+  let Inst{31}    = 0;
 }
 
 // 1.7.7 XL-Form
@@ -316,12 +367,14 @@ class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
 }
 
 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OL, string asmstr, 
-               InstrItinClass itin>
+               InstrItinClass itin, list<dag> pattern>
     : I<opcode, OL, asmstr, itin> {
   bits<5> BO;
   bits<5> BI;
   bits<2> BH;
   
+  let Pattern = pattern;
+  
   let Inst{6-10}  = BO;
   let Inst{11-15} = BI;
   let Inst{16-18} = 0;
@@ -331,8 +384,8 @@ class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OL, string asmstr,
 }
 
 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo,  bits<5> bi, bit lk,
-                  dag OL, string asmstr, InstrItinClass itin>
-  : XLForm_2<opcode, xo, lk, OL, asmstr, itin> {
+                  dag OL, string asmstr, InstrItinClass itin, list<dag> pattern>
+  : XLForm_2<opcode, xo, lk, OL, asmstr, itin, pattern> {
   let BO = bo;
   let BI = bi;
   let BH = 0;
@@ -361,7 +414,16 @@ class XFXForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
   bits<10> SPR;
 
   let Inst{6-10}  = RT;
-  let Inst{11-20} = SPR;
+  let Inst{11}    = SPR{4};
+  let Inst{12}    = SPR{3};
+  let Inst{13}    = SPR{2};
+  let Inst{14}    = SPR{1};
+  let Inst{15}    = SPR{0};
+  let Inst{16}    = SPR{9};
+  let Inst{17}    = SPR{8};
+  let Inst{18}    = SPR{7};
+  let Inst{19}    = SPR{6};
+  let Inst{20}    = SPR{5};
   let Inst{21-30} = xo;
   let Inst{31}    = 0;
 }
@@ -411,7 +473,6 @@ class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
   let Inst{31}    = 0;
 }
 
-
 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
                 InstrItinClass itin>
   : XFXForm_1<opcode, xo, OL, asmstr, itin>;
@@ -548,12 +609,34 @@ class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr,
   let Inst{31}    = RC;
 }
 
+
+
 // E-1 VA-Form
+
+// VAForm_1 - DACB ordering.
 class VAForm_1<bits<6> xo, dag OL, string asmstr,
                InstrItinClass itin, list<dag> pattern>
     : I<4, OL, asmstr, itin> {
   bits<5> VD;
   bits<5> VA;
+  bits<5> VC;
+  bits<5> VB;
+
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = VD;
+  let Inst{11-15} = VA;
+  let Inst{16-20} = VB;
+  let Inst{21-25} = VC;
+  let Inst{26-31} = xo;
+}
+
+// VAForm_1a - DABC ordering.
+class VAForm_1a<bits<6> xo, dag OL, string asmstr,
+                InstrItinClass itin, list<dag> pattern>
+    : I<4, OL, asmstr, itin> {
+  bits<5> VD;
+  bits<5> VA;
   bits<5> VB;
   bits<5> VC;
 
@@ -566,6 +649,24 @@ class VAForm_1<bits<6> xo, dag OL, string asmstr,
   let Inst{26-31} = xo;
 }
 
+class VAForm_2<bits<6> xo, dag OL, string asmstr,
+               InstrItinClass itin, list<dag> pattern>
+    : I<4, OL, asmstr, itin> {
+  bits<5> VD;
+  bits<5> VA;
+  bits<5> VB;
+  bits<4> SH;
+
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = VD;
+  let Inst{11-15} = VA;
+  let Inst{16-20} = VB;
+  let Inst{21}    = 0;
+  let Inst{22-25} = SH;
+  let Inst{26-31} = xo;
+}
+
 // E-2 VX-Form
 class VXForm_1<bits<11> xo, dag OL, string asmstr,
                InstrItinClass itin, list<dag> pattern>
@@ -582,27 +683,91 @@ class VXForm_1<bits<11> xo, dag OL, string asmstr,
   let Inst{21-31} = xo;
 }
 
+class VXForm_setzero<bits<11> xo, dag OL, string asmstr,
+               InstrItinClass itin, list<dag> pattern>
+    : VXForm_1<xo, OL, asmstr, itin, pattern> {
+  let VA = VD;
+  let VB = VD;
+}
+
+
+class VXForm_2<bits<11> xo, dag OL, string asmstr,
+               InstrItinClass itin, list<dag> pattern>
+    : I<4, OL, asmstr, itin> {
+  bits<5> VD;
+  bits<5> VB;
+  
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = VD;
+  let Inst{11-15} = 0;
+  let Inst{16-20} = VB;
+  let Inst{21-31} = xo;
+}
+
+class VXForm_3<bits<11> xo, dag OL, string asmstr,
+               InstrItinClass itin, list<dag> pattern>
+    : I<4, OL, asmstr, itin> {
+  bits<5> VD;
+  bits<5> IMM;
+  
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = VD;
+  let Inst{11-15} = IMM;
+  let Inst{16-20} = 0;
+  let Inst{21-31} = xo;
+}
+
+/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
+class VXForm_4<bits<11> xo, dag OL, string asmstr,
+               InstrItinClass itin, list<dag> pattern>
+    : I<4, OL, asmstr, itin> {
+  bits<5> VD;
+  
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = VD;
+  let Inst{11-15} = 0;
+  let Inst{16-20} = 0;
+  let Inst{21-31} = xo;
+}
+
+/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
+class VXForm_5<bits<11> xo, dag OL, string asmstr,
+               InstrItinClass itin, list<dag> pattern>
+    : I<4, OL, asmstr, itin> {
+  bits<5> VB;
+  
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = 0;
+  let Inst{11-15} = 0;
+  let Inst{16-20} = VB;
+  let Inst{21-31} = xo;
+}
+
 // E-4 VXR-Form
-class VXRForm_1<bits<10> xo, bit rc, dag OL, string asmstr,
+class VXRForm_1<bits<10> xo, dag OL, string asmstr,
                InstrItinClass itin, list<dag> pattern>
     : I<4, OL, asmstr, itin> {
   bits<5> VD;
   bits<5> VA;
   bits<5> VB;
+  bit RC = 0;
   
   let Pattern = pattern;
   
   let Inst{6-10}  = VD;
   let Inst{11-15} = VA;
   let Inst{16-20} = VB;
-  let Inst{21}    = rc;
+  let Inst{21}    = RC;
   let Inst{22-31} = xo;
 }
 
 //===----------------------------------------------------------------------===//
-def NoItin : InstrItinClass;
 class Pseudo<dag OL, string asmstr, list<dag> pattern>
-    : I<0, OL, asmstr, NoItin> {
+    : I<0, OL, asmstr, NoItinerary> {
   let PPC64 = 0;
   let VMX = 0;
   let Pattern = pattern;