X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FPowerPC%2FPPCRegisterInfo.td;h=b3d145b2cc49083d52f389184f21f975e0556e8b;hb=376a2e104f9ab97dd8f6c4fc52a656ad823d1a88;hp=0b3b4cabde77d456acc52d7e7c7ba838a2ae8f39;hpb=43182ac0d6c2fa99b71cac66fa3da1fa063b2413;p=oota-llvm.git diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index 0b3b4cabde7..b3d145b2cc4 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -1,15 +1,26 @@ -//===- PowerPCRegisterInfo.td - The PowerPC Register File --*- tablegen -*-===// -// +//===-- PPCRegisterInfo.td - The PowerPC Register File -----*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// //===----------------------------------------------------------------------===// // // //===----------------------------------------------------------------------===// +let Namespace = "PPC" in { +def sub_lt : SubRegIndex<1>; +def sub_gt : SubRegIndex<1, 1>; +def sub_eq : SubRegIndex<1, 2>; +def sub_un : SubRegIndex<1, 3>; +def sub_32 : SubRegIndex<32>; +def sub_64 : SubRegIndex<64>; +def sub_128 : SubRegIndex<128>; +} + + class PPCReg : Register { let Namespace = "PPC"; } @@ -18,316 +29,286 @@ class PPCReg : Register { // GPR - One of the 32 32-bit general-purpose registers class GPR num, string n> : PPCReg { - field bits<5> Num = num; + let HWEncoding{4-0} = num; } // GP8 - One of the 32 64-bit general-purpose registers -class GP8 : PPCReg { - field bits<5> Num = SubReg.Num; +class GP8 : PPCReg { + let HWEncoding = SubReg.HWEncoding; let SubRegs = [SubReg]; + let SubRegIndices = [sub_32]; } // SPR - One of the 32-bit special-purpose registers class SPR num, string n> : PPCReg { - field bits<10> Num = num; + let HWEncoding{9-0} = num; } // FPR - One of the 32 64-bit floating-point registers class FPR num, string n> : PPCReg { - field bits<5> Num = num; + let HWEncoding{4-0} = num; +} + +// VF - One of the 32 64-bit floating-point subregisters of the vector +// registers (used by VSX). +class VF num, string n> : PPCReg { + let HWEncoding{4-0} = num; + let HWEncoding{5} = 1; } // VR - One of the 32 128-bit vector registers -class VR num, string n> : PPCReg { - field bits<5> Num = num; +class VR : PPCReg { + let HWEncoding{4-0} = SubReg.HWEncoding{4-0}; + let HWEncoding{5} = 0; + let SubRegs = [SubReg]; + let SubRegIndices = [sub_64]; +} + +// VSRL - One of the 32 128-bit VSX registers that overlap with the scalar +// floating-point registers. +class VSRL : PPCReg { + let HWEncoding = SubReg.HWEncoding; + let SubRegs = [SubReg]; + let SubRegIndices = [sub_64]; +} + +// VSRH - One of the 32 128-bit VSX registers that overlap with the vector +// registers. +class VSRH : PPCReg { + let HWEncoding{4-0} = SubReg.HWEncoding{4-0}; + let HWEncoding{5} = 1; + let SubRegs = [SubReg]; + let SubRegIndices = [sub_128]; } // CR - One of the 8 4-bit condition registers -class CR num, string n> : PPCReg { - field bits<3> Num = num; +class CR num, string n, list subregs> : PPCReg { + let HWEncoding{2-0} = num; + let SubRegs = subregs; } // CRBIT - One of the 32 1-bit condition register fields class CRBIT num, string n> : PPCReg { - field bits<5> Num = num; + let HWEncoding{4-0} = num; } - // General-purpose registers -def R0 : GPR< 0, "r0">, DwarfRegNum<0>; -def R1 : GPR< 1, "r1">, DwarfRegNum<1>; -def R2 : GPR< 2, "r2">, DwarfRegNum<2>; -def R3 : GPR< 3, "r3">, DwarfRegNum<3>; -def R4 : GPR< 4, "r4">, DwarfRegNum<4>; -def R5 : GPR< 5, "r5">, DwarfRegNum<5>; -def R6 : GPR< 6, "r6">, DwarfRegNum<6>; -def R7 : GPR< 7, "r7">, DwarfRegNum<7>; -def R8 : GPR< 8, "r8">, DwarfRegNum<8>; -def R9 : GPR< 9, "r9">, DwarfRegNum<9>; -def R10 : GPR<10, "r10">, DwarfRegNum<10>; -def R11 : GPR<11, "r11">, DwarfRegNum<11>; -def R12 : GPR<12, "r12">, DwarfRegNum<12>; -def R13 : GPR<13, "r13">, DwarfRegNum<13>; -def R14 : GPR<14, "r14">, DwarfRegNum<14>; -def R15 : GPR<15, "r15">, DwarfRegNum<15>; -def R16 : GPR<16, "r16">, DwarfRegNum<16>; -def R17 : GPR<17, "r17">, DwarfRegNum<17>; -def R18 : GPR<18, "r18">, DwarfRegNum<18>; -def R19 : GPR<19, "r19">, DwarfRegNum<19>; -def R20 : GPR<20, "r20">, DwarfRegNum<20>; -def R21 : GPR<21, "r21">, DwarfRegNum<21>; -def R22 : GPR<22, "r22">, DwarfRegNum<22>; -def R23 : GPR<23, "r23">, DwarfRegNum<23>; -def R24 : GPR<24, "r24">, DwarfRegNum<24>; -def R25 : GPR<25, "r25">, DwarfRegNum<25>; -def R26 : GPR<26, "r26">, DwarfRegNum<26>; -def R27 : GPR<27, "r27">, DwarfRegNum<27>; -def R28 : GPR<28, "r28">, DwarfRegNum<28>; -def R29 : GPR<29, "r29">, DwarfRegNum<29>; -def R30 : GPR<30, "r30">, DwarfRegNum<30>; -def R31 : GPR<31, "r31">, DwarfRegNum<31>; +foreach Index = 0-31 in { + def R#Index : GPR, DwarfRegNum<[-2, Index]>; +} // 64-bit General-purpose registers -def X0 : GP8< R0>, DwarfRegNum<0>; -def X1 : GP8< R1>, DwarfRegNum<1>; -def X2 : GP8< R2>, DwarfRegNum<2>; -def X3 : GP8< R3>, DwarfRegNum<3>; -def X4 : GP8< R4>, DwarfRegNum<4>; -def X5 : GP8< R5>, DwarfRegNum<5>; -def X6 : GP8< R6>, DwarfRegNum<6>; -def X7 : GP8< R7>, DwarfRegNum<7>; -def X8 : GP8< R8>, DwarfRegNum<8>; -def X9 : GP8< R9>, DwarfRegNum<9>; -def X10 : GP8, DwarfRegNum<10>; -def X11 : GP8, DwarfRegNum<11>; -def X12 : GP8, DwarfRegNum<12>; -def X13 : GP8, DwarfRegNum<13>; -def X14 : GP8, DwarfRegNum<14>; -def X15 : GP8, DwarfRegNum<15>; -def X16 : GP8, DwarfRegNum<16>; -def X17 : GP8, DwarfRegNum<17>; -def X18 : GP8, DwarfRegNum<18>; -def X19 : GP8, DwarfRegNum<19>; -def X20 : GP8, DwarfRegNum<20>; -def X21 : GP8, DwarfRegNum<21>; -def X22 : GP8, DwarfRegNum<22>; -def X23 : GP8, DwarfRegNum<23>; -def X24 : GP8, DwarfRegNum<24>; -def X25 : GP8, DwarfRegNum<25>; -def X26 : GP8, DwarfRegNum<26>; -def X27 : GP8, DwarfRegNum<27>; -def X28 : GP8, DwarfRegNum<28>; -def X29 : GP8, DwarfRegNum<29>; -def X30 : GP8, DwarfRegNum<30>; -def X31 : GP8, DwarfRegNum<31>; +foreach Index = 0-31 in { + def X#Index : GP8("R"#Index), "r"#Index>, + DwarfRegNum<[Index, -2]>; +} // Floating-point registers -def F0 : FPR< 0, "f0">, DwarfRegNum<32>; -def F1 : FPR< 1, "f1">, DwarfRegNum<33>; -def F2 : FPR< 2, "f2">, DwarfRegNum<34>; -def F3 : FPR< 3, "f3">, DwarfRegNum<35>; -def F4 : FPR< 4, "f4">, DwarfRegNum<36>; -def F5 : FPR< 5, "f5">, DwarfRegNum<37>; -def F6 : FPR< 6, "f6">, DwarfRegNum<38>; -def F7 : FPR< 7, "f7">, DwarfRegNum<39>; -def F8 : FPR< 8, "f8">, DwarfRegNum<40>; -def F9 : FPR< 9, "f9">, DwarfRegNum<41>; -def F10 : FPR<10, "f10">, DwarfRegNum<42>; -def F11 : FPR<11, "f11">, DwarfRegNum<43>; -def F12 : FPR<12, "f12">, DwarfRegNum<44>; -def F13 : FPR<13, "f13">, DwarfRegNum<45>; -def F14 : FPR<14, "f14">, DwarfRegNum<46>; -def F15 : FPR<15, "f15">, DwarfRegNum<47>; -def F16 : FPR<16, "f16">, DwarfRegNum<48>; -def F17 : FPR<17, "f17">, DwarfRegNum<49>; -def F18 : FPR<18, "f18">, DwarfRegNum<50>; -def F19 : FPR<19, "f19">, DwarfRegNum<51>; -def F20 : FPR<20, "f20">, DwarfRegNum<52>; -def F21 : FPR<21, "f21">, DwarfRegNum<53>; -def F22 : FPR<22, "f22">, DwarfRegNum<54>; -def F23 : FPR<23, "f23">, DwarfRegNum<55>; -def F24 : FPR<24, "f24">, DwarfRegNum<56>; -def F25 : FPR<25, "f25">, DwarfRegNum<57>; -def F26 : FPR<26, "f26">, DwarfRegNum<58>; -def F27 : FPR<27, "f27">, DwarfRegNum<59>; -def F28 : FPR<28, "f28">, DwarfRegNum<60>; -def F29 : FPR<29, "f29">, DwarfRegNum<61>; -def F30 : FPR<30, "f30">, DwarfRegNum<62>; -def F31 : FPR<31, "f31">, DwarfRegNum<63>; +foreach Index = 0-31 in { + def F#Index : FPR, + DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>; +} + +// Floating-point vector subregisters (for VSX) +foreach Index = 0-31 in { + def VF#Index : VF; +} // Vector registers -def V0 : VR< 0, "v0">, DwarfRegNum<77>; -def V1 : VR< 1, "v1">, DwarfRegNum<78>; -def V2 : VR< 2, "v2">, DwarfRegNum<79>; -def V3 : VR< 3, "v3">, DwarfRegNum<80>; -def V4 : VR< 4, "v4">, DwarfRegNum<81>; -def V5 : VR< 5, "v5">, DwarfRegNum<82>; -def V6 : VR< 6, "v6">, DwarfRegNum<83>; -def V7 : VR< 7, "v7">, DwarfRegNum<84>; -def V8 : VR< 8, "v8">, DwarfRegNum<85>; -def V9 : VR< 9, "v9">, DwarfRegNum<86>; -def V10 : VR<10, "v10">, DwarfRegNum<87>; -def V11 : VR<11, "v11">, DwarfRegNum<88>; -def V12 : VR<12, "v12">, DwarfRegNum<89>; -def V13 : VR<13, "v13">, DwarfRegNum<90>; -def V14 : VR<14, "v14">, DwarfRegNum<91>; -def V15 : VR<15, "v15">, DwarfRegNum<92>; -def V16 : VR<16, "v16">, DwarfRegNum<93>; -def V17 : VR<17, "v17">, DwarfRegNum<94>; -def V18 : VR<18, "v18">, DwarfRegNum<95>; -def V19 : VR<19, "v19">, DwarfRegNum<96>; -def V20 : VR<20, "v20">, DwarfRegNum<97>; -def V21 : VR<21, "v21">, DwarfRegNum<98>; -def V22 : VR<22, "v22">, DwarfRegNum<99>; -def V23 : VR<23, "v23">, DwarfRegNum<100>; -def V24 : VR<24, "v24">, DwarfRegNum<101>; -def V25 : VR<25, "v25">, DwarfRegNum<102>; -def V26 : VR<26, "v26">, DwarfRegNum<103>; -def V27 : VR<27, "v27">, DwarfRegNum<104>; -def V28 : VR<28, "v28">, DwarfRegNum<105>; -def V29 : VR<29, "v29">, DwarfRegNum<106>; -def V30 : VR<30, "v30">, DwarfRegNum<107>; -def V31 : VR<31, "v31">, DwarfRegNum<108>; +foreach Index = 0-31 in { + def V#Index : VR("VF"#Index), "v"#Index>, + DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>; +} -// Condition registers -def CR0 : CR<0, "cr0">, DwarfRegNum<68>; -def CR1 : CR<1, "cr1">, DwarfRegNum<69>; -def CR2 : CR<2, "cr2">, DwarfRegNum<70>; -def CR3 : CR<3, "cr3">, DwarfRegNum<71>; -def CR4 : CR<4, "cr4">, DwarfRegNum<72>; -def CR5 : CR<5, "cr5">, DwarfRegNum<73>; -def CR6 : CR<6, "cr6">, DwarfRegNum<74>; -def CR7 : CR<7, "cr7">, DwarfRegNum<75>; +// VSX registers +foreach Index = 0-31 in { + def VSL#Index : VSRL("F"#Index), "vs"#Index>, + DwarfRegAlias("F"#Index)>; +} +foreach Index = 0-31 in { + def VSH#Index : VSRH("V"#Index), "vs" # !add(Index, 32)>, + DwarfRegAlias("V"#Index)>; +} + +// The reprsentation of r0 when treated as the constant 0. +def ZERO : GPR<0, "0">; +def ZERO8 : GP8; + +// Representations of the frame pointer used by ISD::FRAMEADDR. +def FP : GPR<0 /* arbitrary */, "**FRAME POINTER**">; +def FP8 : GP8; + +// Representations of the base pointer used by setjmp. +def BP : GPR<0 /* arbitrary */, "**BASE POINTER**">; +def BP8 : GP8; // Condition register bits -def CR0LT : CRBIT< 0, "0">, DwarfRegNum<0>; -def CR0GT : CRBIT< 1, "1">, DwarfRegNum<0>; -def CR0EQ : CRBIT< 2, "2">, DwarfRegNum<0>; -def CR0UN : CRBIT< 3, "3">, DwarfRegNum<0>; -def CR1LT : CRBIT< 4, "4">, DwarfRegNum<0>; -def CR1GT : CRBIT< 5, "5">, DwarfRegNum<0>; -def CR1EQ : CRBIT< 6, "6">, DwarfRegNum<0>; -def CR1UN : CRBIT< 7, "7">, DwarfRegNum<0>; -def CR2LT : CRBIT< 8, "8">, DwarfRegNum<0>; -def CR2GT : CRBIT< 9, "9">, DwarfRegNum<0>; -def CR2EQ : CRBIT<10, "10">, DwarfRegNum<0>; -def CR2UN : CRBIT<11, "11">, DwarfRegNum<0>; -def CR3LT : CRBIT<12, "12">, DwarfRegNum<0>; -def CR3GT : CRBIT<13, "13">, DwarfRegNum<0>; -def CR3EQ : CRBIT<14, "14">, DwarfRegNum<0>; -def CR3UN : CRBIT<15, "15">, DwarfRegNum<0>; -def CR4LT : CRBIT<16, "16">, DwarfRegNum<0>; -def CR4GT : CRBIT<17, "17">, DwarfRegNum<0>; -def CR4EQ : CRBIT<18, "18">, DwarfRegNum<0>; -def CR4UN : CRBIT<19, "19">, DwarfRegNum<0>; -def CR5LT : CRBIT<20, "20">, DwarfRegNum<0>; -def CR5GT : CRBIT<21, "21">, DwarfRegNum<0>; -def CR5EQ : CRBIT<22, "22">, DwarfRegNum<0>; -def CR5UN : CRBIT<23, "23">, DwarfRegNum<0>; -def CR6LT : CRBIT<24, "24">, DwarfRegNum<0>; -def CR6GT : CRBIT<25, "25">, DwarfRegNum<0>; -def CR6EQ : CRBIT<26, "26">, DwarfRegNum<0>; -def CR6UN : CRBIT<27, "27">, DwarfRegNum<0>; -def CR7LT : CRBIT<28, "28">, DwarfRegNum<0>; -def CR7GT : CRBIT<29, "29">, DwarfRegNum<0>; -def CR7EQ : CRBIT<30, "30">, DwarfRegNum<0>; -def CR7UN : CRBIT<31, "31">, DwarfRegNum<0>; - -def : SubRegSet<1, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7], - [CR0LT, CR1LT, CR2LT, CR3LT, CR4LT, CR5LT, CR6LT, CR7LT]>; -def : SubRegSet<2, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7], - [CR0GT, CR1GT, CR2GT, CR3GT, CR4GT, CR5GT, CR6GT, CR7GT]>; -def : SubRegSet<3, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7], - [CR0EQ, CR1EQ, CR2EQ, CR3EQ, CR4EQ, CR5EQ, CR6EQ, CR7EQ]>; -def : SubRegSet<4, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7], - [CR0UN, CR1UN, CR2UN, CR3UN, CR4UN, CR5UN, CR6UN, CR7UN]>; +def CR0LT : CRBIT< 0, "0">; +def CR0GT : CRBIT< 1, "1">; +def CR0EQ : CRBIT< 2, "2">; +def CR0UN : CRBIT< 3, "3">; +def CR1LT : CRBIT< 4, "4">; +def CR1GT : CRBIT< 5, "5">; +def CR1EQ : CRBIT< 6, "6">; +def CR1UN : CRBIT< 7, "7">; +def CR2LT : CRBIT< 8, "8">; +def CR2GT : CRBIT< 9, "9">; +def CR2EQ : CRBIT<10, "10">; +def CR2UN : CRBIT<11, "11">; +def CR3LT : CRBIT<12, "12">; +def CR3GT : CRBIT<13, "13">; +def CR3EQ : CRBIT<14, "14">; +def CR3UN : CRBIT<15, "15">; +def CR4LT : CRBIT<16, "16">; +def CR4GT : CRBIT<17, "17">; +def CR4EQ : CRBIT<18, "18">; +def CR4UN : CRBIT<19, "19">; +def CR5LT : CRBIT<20, "20">; +def CR5GT : CRBIT<21, "21">; +def CR5EQ : CRBIT<22, "22">; +def CR5UN : CRBIT<23, "23">; +def CR6LT : CRBIT<24, "24">; +def CR6GT : CRBIT<25, "25">; +def CR6EQ : CRBIT<26, "26">; +def CR6UN : CRBIT<27, "27">; +def CR7LT : CRBIT<28, "28">; +def CR7GT : CRBIT<29, "29">; +def CR7EQ : CRBIT<30, "30">; +def CR7UN : CRBIT<31, "31">; + +// Condition registers +let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in { +def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>; +def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69, 69]>; +def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70, 70]>; +def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71, 71]>; +def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>; +def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73, 73]>; +def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>; +def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>; +} + +// The full condition-code register. This is not modeled fully, but defined +// here primarily, for compatibility with gcc, to allow the inline asm "cc" +// clobber specification to work. +def CC : PPCReg<"cc">, DwarfRegAlias { + let Aliases = [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]; +} // Link register -def LR : SPR<8, "lr">, DwarfRegNum<65>; +def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; //let Aliases = [LR] in -def LR8 : SPR<8, "lr">, DwarfRegNum<65>; +def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; // Count register -def CTR : SPR<9, "ctr">, DwarfRegNum<66>; -def CTR8 : SPR<9, "ctr">, DwarfRegNum<66>; +def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; +def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; // VRsave register -def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<107>; +def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>; + +// Carry bit. In the architecture this is really bit 0 of the XER register +// (which really is SPR register 1); this is the only bit interesting to a +// compiler. +def CARRY: SPR<1, "ca">; + +// FP rounding mode: bits 30 and 31 of the FP status and control register +// This is not allocated as a normal register; it appears only in +// Uses and Defs. The ABI says it needs to be preserved by a function, +// but this is not achieved by saving and restoring it as with +// most registers, it has to be done in code; to make this work all the +// return and call instructions are described as Uses of RM, so instructions +// that do nothing but change RM will not get deleted. +// Also, in the architecture it is not really a SPR; 512 is arbitrary. +def RM: SPR<512, "**ROUNDING MODE**">; /// Register classes // Allocate volatiles first // then nonvolatiles in reverse order since stmw/lmw save from rN to r31 -def GPRC : RegisterClass<"PPC", [i32], 32, - [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, - R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17, - R16, R15, R14, R13, R31, R0, R1, LR]> -{ - let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - GPRCClass::iterator - GPRCClass::allocation_order_begin(const MachineFunction &MF) const { - // In Linux, r2 is reserved for the OS. - if (!MF.getTarget().getSubtarget().isDarwin()) - return begin()+1; - - return begin(); - } - GPRCClass::iterator - GPRCClass::allocation_order_end(const MachineFunction &MF) const { - // On PPC64, r13 is the thread pointer. Never allocate this register. - // Note that this is overconservative, as it also prevents allocation of - // R31 when the FP is not needed. - if (MF.getTarget().getSubtarget().isPPC64()) - return end()-5; // don't allocate R13, R31, R0, R1, LR - - if (needsFP(MF)) - return end()-4; // don't allocate R31, R0, R1, LR - else - return end()-3; // don't allocate R0, R1, LR - } - }]; -} -def G8RC : RegisterClass<"PPC", [i64], 64, - [X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, - X30, X29, X28, X27, X26, X25, X24, X23, X22, X21, X20, X19, X18, X17, - X16, X15, X14, X31, X13, X0, X1, LR8]> -{ - let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - G8RCClass::iterator - G8RCClass::allocation_order_begin(const MachineFunction &MF) const { - return begin(); - } - G8RCClass::iterator - G8RCClass::allocation_order_end(const MachineFunction &MF) const { - if (needsFP(MF)) - return end()-5; - else - return end()-4; - } - }]; -} +def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12), + (sequence "R%u", 30, 13), + R31, R0, R1, FP, BP)>; +def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12), + (sequence "X%u", 30, 14), + X31, X13, X0, X1, FP8, BP8)>; +// For some instructions r0 is special (representing the value 0 instead of +// the value in the r0 register), and we use these register subclasses to +// prevent r0 from being allocated for use by those instructions. +def GPRC_NOR0 : RegisterClass<"PPC", [i32], 32, (add (sub GPRC, R0), ZERO)>; +def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)>; -def F8RC : RegisterClass<"PPC", [f64], 64, [F0, F1, F2, F3, F4, F5, F6, F7, - F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, - F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>; -def F4RC : RegisterClass<"PPC", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7, - F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, - F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>; +// Allocate volatiles first, then non-volatiles in reverse order. With the SVR4 +// ABI the size of the Floating-point register save area is determined by the +// allocated non-volatile register with the lowest register number, as FP +// register N is spilled to offset 8 * (32 - N) below the back chain word of the +// previous stack frame. By allocating non-volatiles in reverse order we make +// sure that the Floating-point register save area is always as small as +// possible because there aren't any unused spill slots. +def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13), + (sequence "F%u", 31, 14))>; +def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>; def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128, - [V2, V3, V4, V5, V0, V1, - V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21, - V22, V23, V24, V25, V26, V27, V28, V29, V30, V31]>; + (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11, + V12, V13, V14, V15, V16, V17, V18, V19, V31, V30, + V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>; + +// VSX register classes (the allocation order mirrors that of the corresponding +// subregister classes). +def VSLRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128, + (add (sequence "VSL%u", 0, 13), + (sequence "VSL%u", 31, 14))>; +def VSHRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128, + (add VSH2, VSH3, VSH4, VSH5, VSH0, VSH1, VSH6, VSH7, + VSH8, VSH9, VSH10, VSH11, VSH12, VSH13, VSH14, + VSH15, VSH16, VSH17, VSH18, VSH19, VSH31, VSH30, + VSH29, VSH28, VSH27, VSH26, VSH25, VSH24, VSH23, + VSH22, VSH21, VSH20)>; +def VSRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128, + (add VSLRC, VSHRC)>; + +// Register classes for the 64-bit "scalar" VSX subregisters. +def VFRC : RegisterClass<"PPC", [f64], 64, + (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7, + VF8, VF9, VF10, VF11, VF12, VF13, VF14, + VF15, VF16, VF17, VF18, VF19, VF31, VF30, + VF29, VF28, VF27, VF26, VF25, VF24, VF23, + VF22, VF21, VF20)>; +def VSFRC : RegisterClass<"PPC", [f64], 64, (add F8RC, VFRC)>; + +def CRBITRC : RegisterClass<"PPC", [i1], 32, + (add CR2LT, CR2GT, CR2EQ, CR2UN, + CR3LT, CR3GT, CR3EQ, CR3UN, + CR4LT, CR4GT, CR4EQ, CR4UN, + CR5LT, CR5GT, CR5EQ, CR5UN, + CR6LT, CR6GT, CR6EQ, CR6UN, + CR7LT, CR7GT, CR7EQ, CR7UN, + CR1LT, CR1GT, CR1EQ, CR1UN, + CR0LT, CR0GT, CR0EQ, CR0UN)> { + let Size = 32; +} + +def CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6, + CR7, CR2, CR3, CR4)>; + +// The CTR registers are not allocatable because they're used by the +// decrement-and-branch instructions, and thus need to stay live across +// multiple basic blocks. +def CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)> { + let isAllocatable = 0; +} +def CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)> { + let isAllocatable = 0; +} + +def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>; +def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> { + let CopyCost = -1; +} + +def CCRC : RegisterClass<"PPC", [i32], 32, (add CC)> { + let isAllocatable = 0; +} -def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2, - CR3, CR4]>; -