X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FPowerPC%2FPPCTargetMachine.cpp;h=03425c9ca5f8fe9c37bc7b00f4a26af36f76c844;hb=89e8a17b4d1945a6f4ab5de8448767fb483503aa;hp=ed82a63393052354db4bdc7823ea358b985af35c;hpb=ad807370e9e8ed20b9abb9f3f401e83080ad0f38;p=oota-llvm.git diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp index ed82a633930..03425c9ca5f 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -13,13 +13,17 @@ #include "PPCTargetMachine.h" #include "PPC.h" +#include "PPCTargetObjectFile.h" +#include "PPCTargetTransformInfo.h" #include "llvm/CodeGen/Passes.h" +#include "llvm/IR/Function.h" #include "llvm/MC/MCStreamer.h" #include "llvm/PassManager.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Target/TargetOptions.h" +#include "llvm/Transforms/Scalar.h" using namespace llvm; static cl:: @@ -30,6 +34,11 @@ static cl::opt VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early", cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early")); +static cl::opt +EnableGEPOpt("ppc-gep-opt", cl::Hidden, + cl::desc("Enable optimizations on complex GEPs"), + cl::init(true)); + extern "C" void LLVMInitializePowerPCTarget() { // Register the targets RegisterTargetMachine A(ThePPC32Target); @@ -37,16 +46,96 @@ extern "C" void LLVMInitializePowerPCTarget() { RegisterTargetMachine C(ThePPC64LETarget); } +/// Return the datalayout string of a subtarget. +static std::string getDataLayoutString(const Triple &T) { + bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le; + std::string Ret; + + // Most PPC* platforms are big endian, PPC64LE is little endian. + if (T.getArch() == Triple::ppc64le) + Ret = "e"; + else + Ret = "E"; + + Ret += DataLayout::getManglingComponent(T); + + // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit + // pointers. + if (!is64Bit || T.getOS() == Triple::Lv2) + Ret += "-p:32:32"; + + // Note, the alignment values for f64 and i64 on ppc64 in Darwin + // documentation are wrong; these are correct (i.e. "what gcc does"). + if (is64Bit || !T.isOSDarwin()) + Ret += "-i64:64"; + else + Ret += "-f64:32:64"; + + // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones. + if (is64Bit) + Ret += "-n32:64"; + else + Ret += "-n32"; + + return Ret; +} + +static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) { + std::string FullFS = FS; + Triple TargetTriple(TT); + + // Make sure 64-bit features are available when CPUname is generic + if (TargetTriple.getArch() == Triple::ppc64 || + TargetTriple.getArch() == Triple::ppc64le) { + if (!FullFS.empty()) + FullFS = "+64bit," + FullFS; + else + FullFS = "+64bit"; + } + + if (OL >= CodeGenOpt::Default) { + if (!FullFS.empty()) + FullFS = "+crbits," + FullFS; + else + FullFS = "+crbits"; + } + + if (OL != CodeGenOpt::None) { + if (!FullFS.empty()) + FullFS = "+invariant-function-descriptors," + FullFS; + else + FullFS = "+invariant-function-descriptors"; + } + + return FullFS; +} + +static std::unique_ptr createTLOF(const Triple &TT) { + // If it isn't a Mach-O file then it's going to be a linux ELF + // object file. + if (TT.isOSDarwin()) + return make_unique(); + + return make_unique(); +} + +// The FeatureString here is a little subtle. We are modifying the feature string +// with what are (currently) non-function specific overrides as it goes into the +// LLVMTargetMachine constructor and then using the stored value in the +// Subtarget constructor below it. PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, - CodeGenOpt::Level OL, bool is64Bit) - : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), - Subtarget(TT, CPU, FS, is64Bit, OL), JITInfo(Subtarget), - TLInfo(*this), TSInfo(*this) { + CodeGenOpt::Level OL) + : LLVMTargetMachine(T, TT, CPU, computeFSAdditions(FS, OL, TT), Options, RM, + CM, OL), + TLOF(createTLOF(Triple(getTargetTriple()))), + DL(getDataLayoutString(Triple(TT))), Subtarget(TT, CPU, TargetFS, *this) { initAsmInfo(); } +PPCTargetMachine::~PPCTargetMachine() {} + void PPC32TargetMachine::anchor() { } PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, @@ -54,7 +143,7 @@ PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) - : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { + : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) { } void PPC64TargetMachine::anchor() { } @@ -64,9 +153,34 @@ PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) - : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { + : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) { } +const PPCSubtarget * +PPCTargetMachine::getSubtargetImpl(const Function &F) const { + AttributeSet FnAttrs = F.getAttributes(); + Attribute CPUAttr = + FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu"); + Attribute FSAttr = + FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features"); + + std::string CPU = !CPUAttr.hasAttribute(Attribute::None) + ? CPUAttr.getValueAsString().str() + : TargetCPU; + std::string FS = !FSAttr.hasAttribute(Attribute::None) + ? FSAttr.getValueAsString().str() + : TargetFS; + + auto &I = SubtargetMap[CPU + FS]; + if (!I) { + // This needs to be done before we create a new subtarget since any + // creation will depend on the TM and the code generation flags on the + // function that reside in TargetOptions. + resetTargetOptions(F); + I = llvm::make_unique(TargetTriple, CPU, FS, *this); + } + return I.get(); +} //===----------------------------------------------------------------------===// // Pass Pipeline Configuration @@ -83,16 +197,13 @@ public: return getTM(); } - const PPCSubtarget &getPPCSubtarget() const { - return *getPPCTargetMachine().getSubtargetImpl(); - } - + void addIRPasses() override; bool addPreISel() override; bool addILPOpts() override; bool addInstSelector() override; - bool addPreRegAlloc() override; - bool addPreSched2() override; - bool addPreEmitPass() override; + void addPreRegAlloc() override; + void addPreSched2() override; + void addPreEmitPass() override; }; } // namespace @@ -100,6 +211,25 @@ TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) { return new PPCPassConfig(this, PM); } +void PPCPassConfig::addIRPasses() { + addPass(createAtomicExpandPass(&getPPCTargetMachine())); + + if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) { + // Call SeparateConstOffsetFromGEP pass to extract constants within indices + // and lower a GEP with multiple indices to either arithmetic operations or + // multiple GEPs with single index. + addPass(createSeparateConstOffsetFromGEPPass(TM, true)); + // Call EarlyCSE pass to find and remove subexpressions in the lowered + // result. + addPass(createEarlyCSEPass()); + // Do loop invariant code motion in case part of the lowered result is + // invariant. + addPass(createLICMPass()); + } + + TargetPassConfig::addIRPasses(); +} + bool PPCPassConfig::addPreISel() { if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None) addPass(createPPCCTRLoops(getPPCTargetMachine())); @@ -125,47 +255,26 @@ bool PPCPassConfig::addInstSelector() { return false; } -bool PPCPassConfig::addPreRegAlloc() { +void PPCPassConfig::addPreRegAlloc() { initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry()); insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID, &PPCVSXFMAMutateID); - return false; + addPass(createPPCTLSDynamicCallPass()); } -bool PPCPassConfig::addPreSched2() { - addPass(createPPCVSXCopyCleanupPass()); - +void PPCPassConfig::addPreSched2() { if (getOptLevel() != CodeGenOpt::None) addPass(&IfConverterID); - - return true; } -bool PPCPassConfig::addPreEmitPass() { +void PPCPassConfig::addPreEmitPass() { if (getOptLevel() != CodeGenOpt::None) - addPass(createPPCEarlyReturnPass()); + addPass(createPPCEarlyReturnPass(), false); // Must run branch selection immediately preceding the asm printer. - addPass(createPPCBranchSelectionPass()); - return false; -} - -bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, - JITCodeEmitter &JCE) { - // Inform the subtarget that we are in JIT mode. FIXME: does this break macho - // writing? - Subtarget.SetJITMode(); - - // Machine code emitter pass for PowerPC. - PM.add(createPPCJITCodeEmitterPass(*this, JCE)); - - return false; + addPass(createPPCBranchSelectionPass(), false); } -void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) { - // Add first the target-independent BasicTTI pass, then our PPC pass. This - // allows the PPC pass to delegate to the target independent layer when - // appropriate. - PM.add(createBasicTargetTransformInfoPass(this)); - PM.add(createPPCTargetTransformInfoPass(this)); +TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() { + return TargetIRAnalysis( + [this](Function &F) { return TargetTransformInfo(PPCTTIImpl(this, F)); }); } -