X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FR600%2FAMDGPUInstrInfo.h;h=a193a8666ebcd0d16a76bfe2e83ebad01885488a;hb=7f288b455eebcb61c5ecbade9323e4f610068d2a;hp=306f467bc4b2b9d219bbfd9c62f6870028819751;hpb=5e48a0e9ae2365a130dd1ec2e0b4beb337ab79e0;p=oota-llvm.git diff --git a/lib/Target/R600/AMDGPUInstrInfo.h b/lib/Target/R600/AMDGPUInstrInfo.h index 306f467bc4b..a193a8666eb 100644 --- a/lib/Target/R600/AMDGPUInstrInfo.h +++ b/lib/Target/R600/AMDGPUInstrInfo.h @@ -13,10 +13,9 @@ // //===----------------------------------------------------------------------===// -#ifndef AMDGPUINSTRUCTIONINFO_H -#define AMDGPUINSTRUCTIONINFO_H +#ifndef AMDGPUINSTRINFO_H +#define AMDGPUINSTRINFO_H -#include "AMDGPUInstrInfo.h" #include "AMDGPURegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include @@ -33,7 +32,7 @@ namespace llvm { -class AMDGPUTargetMachine; +class AMDGPUSubtarget; class MachineFunction; class MachineInstr; class MachineInstrBuilder; @@ -43,22 +42,24 @@ private: const AMDGPURegisterInfo RI; bool getNextBranchInstr(MachineBasicBlock::iterator &iter, MachineBasicBlock &MBB) const; + virtual void anchor(); protected: - TargetMachine &TM; + const AMDGPUSubtarget &ST; public: - explicit AMDGPUInstrInfo(TargetMachine &tm); + explicit AMDGPUInstrInfo(const AMDGPUSubtarget &st); virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0; bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, - unsigned &DstReg, unsigned &SubIdx) const; + unsigned &DstReg, unsigned &SubIdx) const override; - unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; + unsigned isLoadFromStackSlot(const MachineInstr *MI, + int &FrameIndex) const override; unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, - int &FrameIndex) const; + int &FrameIndex) const override; bool hasLoadFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, - int &FrameIndex) const; + int &FrameIndex) const override; unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const; @@ -69,7 +70,7 @@ public: MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, - LiveVariables *LV) const; + LiveVariables *LV) const override; virtual void copyPhysReg(MachineBasicBlock &MBB, @@ -77,61 +78,67 @@ public: unsigned DestReg, unsigned SrcReg, bool KillSrc) const = 0; + bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override; + void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const; + const TargetRegisterInfo *TRI) const override; void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const; + const TargetRegisterInfo *TRI) const override; protected: MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl &Ops, - int FrameIndex) const; + int FrameIndex) const override; MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl &Ops, - MachineInstr *LoadMI) const; + MachineInstr *LoadMI) const override; + /// \returns the smallest register index that will be accessed by an indirect + /// read or write or -1 if indirect addressing is not used by this program. + int getIndirectIndexBegin(const MachineFunction &MF) const; + + /// \returns the largest register index that will be accessed by an indirect + /// read or write or -1 if indirect addressing is not used by this program. + int getIndirectIndexEnd(const MachineFunction &MF) const; + public: bool canFoldMemoryOperand(const MachineInstr *MI, - const SmallVectorImpl &Ops) const; + const SmallVectorImpl &Ops) const override; bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, - unsigned Reg, bool UnfoldLoad, bool UnfoldStore, - SmallVectorImpl &NewMIs) const; + unsigned Reg, bool UnfoldLoad, bool UnfoldStore, + SmallVectorImpl &NewMIs) const override; bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, - SmallVectorImpl &NewNodes) const; + SmallVectorImpl &NewNodes) const override; unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, - bool UnfoldLoad, bool UnfoldStore, - unsigned *LoadRegIndex = 0) const; + bool UnfoldLoad, bool UnfoldStore, + unsigned *LoadRegIndex = nullptr) const override; + + bool enableClusterLoads() const override; + bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, - unsigned NumLoads) const; + unsigned NumLoads) const override; - bool ReverseBranchCondition(SmallVectorImpl &Cond) const; + bool + ReverseBranchCondition(SmallVectorImpl &Cond) const override; void insertNoop(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI) const; - bool isPredicated(const MachineInstr *MI) const; + MachineBasicBlock::iterator MI) const override; + bool isPredicated(const MachineInstr *MI) const override; bool SubsumesPredicate(const SmallVectorImpl &Pred1, - const SmallVectorImpl &Pred2) const; + const SmallVectorImpl &Pred2) const override; bool DefinesPredicate(MachineInstr *MI, - std::vector &Pred) const; - bool isPredicable(MachineInstr *MI) const; - bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; + std::vector &Pred) const override; + bool isPredicable(MachineInstr *MI) const override; + bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override; // Helper functions that check the opcode for status information - bool isLoadInst(llvm::MachineInstr *MI) const; - bool isExtLoadInst(llvm::MachineInstr *MI) const; - bool isSWSExtLoadInst(llvm::MachineInstr *MI) const; - bool isSExtLoadInst(llvm::MachineInstr *MI) const; - bool isZExtLoadInst(llvm::MachineInstr *MI) const; - bool isAExtLoadInst(llvm::MachineInstr *MI) const; - bool isStoreInst(llvm::MachineInstr *MI) const; - bool isTruncStoreInst(llvm::MachineInstr *MI) const; bool isRegisterStore(const MachineInstr &MI) const; bool isRegisterLoad(const MachineInstr &MI) const; @@ -139,19 +146,8 @@ public: // Pure virtual funtions to be implemented by sub-classes. //===---------------------------------------------------------------------===// - virtual MachineInstr* getMovImmInstr(MachineFunction *MF, unsigned DstReg, - int64_t Imm) const = 0; - virtual unsigned getIEQOpcode() const = 0; virtual bool isMov(unsigned opcode) const = 0; - /// \returns the smallest register index that will be accessed by an indirect - /// read or write or -1 if indirect addressing is not used by this program. - virtual int getIndirectIndexBegin(const MachineFunction &MF) const = 0; - - /// \returns the largest register index that will be accessed by an indirect - /// read or write or -1 if indirect addressing is not used by this program. - virtual int getIndirectIndexEnd(const MachineFunction &MF) const = 0; - /// \brief Calculate the "Indirect Address" for the given \p RegIndex and /// \p Channel /// @@ -162,14 +158,9 @@ public: virtual unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const = 0; - /// \returns The register class to be used for storing values to an - /// "Indirect Address" . - virtual const TargetRegisterClass *getIndirectAddrStoreRegClass( - unsigned SourceReg) const = 0; - - /// \returns The register class to be used for loading values from - /// an "Indirect Address" . - virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const = 0; + /// \returns The register class to be used for loading and storing values + /// from an "Indirect Address" . + virtual const TargetRegisterClass *getIndirectAddrRegClass() const = 0; /// \brief Build instruction(s) for an indirect register write. /// @@ -187,15 +178,14 @@ public: unsigned ValueReg, unsigned Address, unsigned OffsetReg) const = 0; - /// \returns the register class whose sub registers are the set of all - /// possible registers that can be used for indirect addressing. - virtual const TargetRegisterClass *getSuperIndirectRegClass() const = 0; - + /// \brief Build a MOV instruction. + virtual MachineInstr *buildMovInstr(MachineBasicBlock *MBB, + MachineBasicBlock::iterator I, + unsigned DstReg, unsigned SrcReg) const = 0; - /// \brief Convert the AMDIL MachineInstr to a supported ISA - /// MachineInstr - virtual void convertToISA(MachineInstr & MI, MachineFunction &MF, - DebugLoc DL) const; + /// \brief Given a MIMG \p Opcode that writes all 4 channels, return the + /// equivalent opcode that writes \p Channels Channels. + int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const; };