X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FREADME.txt;h=9c27f27696613fbe69574f384a9752467d6d68eb;hb=bfcb4aa10b5948539f6ee59eecfe88faa9fc4e94;hp=99e1252dc8aed1584e585bbaccff02842ffa1253;hpb=ed0318eab83cac5250353d8b70bca684ce247d70;p=oota-llvm.git diff --git a/lib/Target/README.txt b/lib/Target/README.txt index 99e1252dc8a..9c27f276966 100644 --- a/lib/Target/README.txt +++ b/lib/Target/README.txt @@ -2,22 +2,6 @@ Target Independent Opportunities: //===---------------------------------------------------------------------===// -With the recent changes to make the implicit def/use set explicit in -machineinstrs, we should change the target descriptions for 'call' instructions -so that the .td files don't list all the call-clobbered registers as implicit -defs. Instead, these should be added by the code generator (e.g. on the dag). - -This has a number of uses: - -1. PPC32/64 and X86 32/64 can avoid having multiple copies of call instructions - for their different impdef sets. -2. Targets with multiple calling convs (e.g. x86) which have different clobber - sets don't need copies of call instructions. -3. 'Interprocedural register allocation' can be done to reduce the clobber sets - of calls. - -//===---------------------------------------------------------------------===// - We should recognized various "overflow detection" idioms and translate them into llvm.uadd.with.overflow and similar intrinsics. Here is a multiply idiom: @@ -870,11 +854,6 @@ rshift_gt (unsigned int a) bar (); } -void neg_eq_cst(unsigned int a) { -if (-a == 123) -bar(); -} - All should simplify to a single comparison. All of these are currently not optimized with "clang -emit-llvm-bc | opt -std-compile-opts". @@ -966,6 +945,31 @@ optimized with "clang -emit-llvm-bc | opt -std-compile-opts". //===---------------------------------------------------------------------===// +int g(int x) { return (x - 10) < 0; } +Should combine to "x <= 9" (the sub has nsw). Currently not +optimized with "clang -emit-llvm-bc | opt -std-compile-opts". + +//===---------------------------------------------------------------------===// + +int g(int x) { return (x + 10) < 0; } +Should combine to "x < -10" (the add has nsw). Currently not +optimized with "clang -emit-llvm-bc | opt -std-compile-opts". + +//===---------------------------------------------------------------------===// + +int f(int i, int j) { return i < j + 1; } +int g(int i, int j) { return j > i - 1; } +Should combine to "i <= j" (the add/sub has nsw). Currently not +optimized with "clang -emit-llvm-bc | opt -std-compile-opts". + +//===---------------------------------------------------------------------===// + +unsigned f(unsigned x) { return ((x & 7) + 1) & 15; } +The & 15 part should be optimized away, it doesn't change the result. Currently +not optimized with "clang -emit-llvm-bc | opt -std-compile-opts". + +//===---------------------------------------------------------------------===// + This was noticed in the entryblock for grokdeclarator in 403.gcc: %tmp = icmp eq i32 %decl_context, 4 @@ -1767,7 +1771,6 @@ case it choses instead to keep the max operation obvious. //===---------------------------------------------------------------------===// -Switch lowering generates less than ideal code for the following switch: define void @a(i32 %x) nounwind { entry: switch i32 %x, label %if.end [ @@ -1788,19 +1791,15 @@ declare void @foo() Generated code on x86-64 (other platforms give similar results): a: cmpl $5, %edi - ja .LBB0_2 - movl %edi, %eax - movl $47, %ecx - btq %rax, %rcx - jb .LBB0_3 + ja LBB2_2 + cmpl $4, %edi + jne LBB2_3 .LBB0_2: ret .LBB0_3: jmp foo # TAILCALL -The movl+movl+btq+jb could be simplified to a cmpl+jne. - -Or, if we wanted to be really clever, we could simplify the whole thing to +If we wanted to be really clever, we could simplify the whole thing to something like the following, which eliminates a branch: xorl $1, %edi cmpl $4, %edi @@ -2259,52 +2258,6 @@ icmp transform. //===---------------------------------------------------------------------===// -We should optimize this: - - %tmp = load i16* %arrayidx, align 4, !tbaa !0 - %A = trunc i16 %tmp to i8 - %cmp = icmp eq i8 %A, 127 - %B.mask = and i16 %tmp, -256 - %cmp7 = icmp eq i16 %B.mask, 17664 - %or.cond = and i1 %cmp, %cmp7 - br i1 %or.cond, label %land.lhs.true9, label %if.end - -into: - - %tmp = load i16* %arrayidx, align 4, !tbaa !0 - %0 = icmp eq i16 %tmp, 17791 - br i1 %0, label %land.lhs.true9, label %if.end - -with this patch: -Index: InstCombine/InstCombineCompares.cpp -=================================================================== ---- InstCombine/InstCombineCompares.cpp (revision 129500) -+++ InstCombine/InstCombineCompares.cpp (working copy) -@@ -2506,6 +2506,18 @@ - return &I; - } - } -+ -+ // Transform "icmp eq (trunc X), cst" to "icmp (and X, mask), cst" -+ if (Op0->hasOneUse() && match(Op0, m_Trunc(m_Value(A))) && -+ isa(Op1)) { -+ APInt MaskV = APInt::getLowBitsSet(A->getType()->getPrimitiveSizeInBits(), -+ Op0->getType()->getPrimitiveSizeInBits()); -+ Value *Mask = -+ Builder->CreateAnd(A, ConstantInt::get(A->getContext(), MaskV)); -+ return new ICmpInst(I.getPredicate(), Mask, -+ ConstantExpr::getZExt(cast(Op1), -+ Mask->getType())); -+ } - } - - { - - -Not having this is blocking resolving PR6627. - -//===---------------------------------------------------------------------===// - This code: typedef struct { @@ -2351,4 +2304,66 @@ The two or/and's should be merged into one each. //===---------------------------------------------------------------------===// +Machine level code hoisting can be useful in some cases. For example, PR9408 +is about: + +typedef union { + void (*f1)(int); + void (*f2)(long); +} funcs; + +void foo(funcs f, int which) { + int a = 5; + if (which) { + f.f1(a); + } else { + f.f2(a); + } +} + +which we compile to: + +foo: # @foo +# BB#0: # %entry + pushq %rbp + movq %rsp, %rbp + testl %esi, %esi + movq %rdi, %rax + je .LBB0_2 +# BB#1: # %if.then + movl $5, %edi + callq *%rax + popq %rbp + ret +.LBB0_2: # %if.else + movl $5, %edi + callq *%rax + popq %rbp + ret +Note that bb1 and bb2 are the same. This doesn't happen at the IR level +because one call is passing an i32 and the other is passing an i64. + +//===---------------------------------------------------------------------===// + +I see this sort of pattern in 176.gcc in a few places (e.g. the start of +store_bit_field). The rem should be replaced with a multiply and subtract: + + %3 = sdiv i32 %A, %B + %4 = srem i32 %A, %B + +Similarly for udiv/urem. Note that this shouldn't be done on X86 or ARM, +which can do this in a single operation (instruction or libcall). It is +probably best to do this in the code generator. + +//===---------------------------------------------------------------------===// + +unsigned foo(unsigned x, unsigned y) { return (x & y) == 0 || x == 0; } +should fold to (x & y) == 0. + +//===---------------------------------------------------------------------===// + +unsigned foo(unsigned x, unsigned y) { return x > y && x != 0; } +should fold to x > y. + +//===---------------------------------------------------------------------===//