X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FSparc%2FFPMover.cpp;h=9a729bd8704458ddeee395a1170ec3a1d4f49be5;hb=fef904d0e824a2c587f8c1063b6c4fbf47fec898;hp=feeadc52a799f33520cd695150aa65074dee9e91;hpb=da5a7fd8d4bcf61e92e30ab2907ba01d30c0755a;p=oota-llvm.git diff --git a/lib/Target/Sparc/FPMover.cpp b/lib/Target/Sparc/FPMover.cpp index feeadc52a79..9a729bd8704 100644 --- a/lib/Target/Sparc/FPMover.cpp +++ b/lib/Target/Sparc/FPMover.cpp @@ -1,9 +1,9 @@ -//===-- FPMover.cpp - SparcV8 double-precision floating point move fixer --===// +//===-- FPMover.cpp - Sparc double-precision floating point move fixer ----===// // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -11,45 +11,47 @@ // //===----------------------------------------------------------------------===// -#include "SparcV8.h" +#define DEBUG_TYPE "fpmover" +#include "Sparc.h" +#include "SparcSubtarget.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetInstrInfo.h" #include "llvm/ADT/Statistic.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; -namespace { - Statistic<> NumFpDs("fpmover", "Number of instructions translated"); - Statistic<> NoopFpDs("fpmover", "Number of noop instructions removed"); +STATISTIC(NumFpDs , "Number of instructions translated"); +STATISTIC(NoopFpDs, "Number of noop instructions removed"); +namespace { struct FPMover : public MachineFunctionPass { /// Target machine description which we query for reg. names, data /// layout, etc. /// TargetMachine &TM; - - FPMover(TargetMachine &tm) : TM(tm) { } + + static char ID; + explicit FPMover(TargetMachine &tm) + : MachineFunctionPass(ID), TM(tm) { } virtual const char *getPassName() const { - return "SparcV8 Double-FP Move Fixer"; + return "Sparc Double-FP Move Fixer"; } bool runOnMachineBasicBlock(MachineBasicBlock &MBB); - bool runOnMachineFunction(MachineFunction &F) { - bool Changed = false; - for (MachineFunction::iterator FI = F.begin(), FE = F.end(); - FI != FE; ++FI) - Changed |= runOnMachineBasicBlock(*FI); - return Changed; - } - + bool runOnMachineFunction(MachineFunction &F); }; + char FPMover::ID = 0; } // end of anonymous namespace -/// createSparcV8FPMoverPass - Returns a pass that turns FpMOVD +/// createSparcFPMoverPass - Returns a pass that turns FpMOVD /// instructions into FMOVS instructions /// -FunctionPass *llvm::createSparcV8FPMoverPass(TargetMachine &tm) { +FunctionPass *llvm::createSparcFPMoverPass(TargetMachine &tm) { return new FPMover(tm); } @@ -57,25 +59,25 @@ FunctionPass *llvm::createSparcV8FPMoverPass(TargetMachine &tm) { /// registers that correspond to it. static void getDoubleRegPair(unsigned DoubleReg, unsigned &EvenReg, unsigned &OddReg) { - static const unsigned EvenHalvesOfPairs[] = { - V8::F0, V8::F2, V8::F4, V8::F6, V8::F8, V8::F10, V8::F12, V8::F14, - V8::F16, V8::F18, V8::F20, V8::F22, V8::F24, V8::F26, V8::F28, V8::F30 + static const uint16_t EvenHalvesOfPairs[] = { + SP::F0, SP::F2, SP::F4, SP::F6, SP::F8, SP::F10, SP::F12, SP::F14, + SP::F16, SP::F18, SP::F20, SP::F22, SP::F24, SP::F26, SP::F28, SP::F30 }; - static const unsigned OddHalvesOfPairs[] = { - V8::F1, V8::F3, V8::F5, V8::F7, V8::F9, V8::F11, V8::F13, V8::F15, - V8::F17, V8::F19, V8::F21, V8::F23, V8::F25, V8::F27, V8::F29, V8::F31 + static const uint16_t OddHalvesOfPairs[] = { + SP::F1, SP::F3, SP::F5, SP::F7, SP::F9, SP::F11, SP::F13, SP::F15, + SP::F17, SP::F19, SP::F21, SP::F23, SP::F25, SP::F27, SP::F29, SP::F31 }; - static const unsigned DoubleRegsInOrder[] = { - V8::D0, V8::D1, V8::D2, V8::D3, V8::D4, V8::D5, V8::D6, V8::D7, V8::D8, - V8::D9, V8::D10, V8::D11, V8::D12, V8::D13, V8::D14, V8::D15 + static const uint16_t DoubleRegsInOrder[] = { + SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, + SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15 }; - for (unsigned i = 0; i < sizeof(DoubleRegsInOrder)/sizeof(unsigned); ++i) + for (unsigned i = 0; i < array_lengthof(DoubleRegsInOrder); ++i) if (DoubleRegsInOrder[i] == DoubleReg) { EvenReg = EvenHalvesOfPairs[i]; OddReg = OddHalvesOfPairs[i]; return; } - assert(0 && "Can't find reg"); + llvm_unreachable("Can't find reg"); } /// runOnMachineBasicBlock - Fixup FpMOVD instructions in this MBB. @@ -84,28 +86,56 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) { bool Changed = false; for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) { MachineInstr *MI = I++; - if (MI->getOpcode() == V8::FpMOVD) { + DebugLoc dl = MI->getDebugLoc(); + if (MI->getOpcode() == SP::FpMOVD || MI->getOpcode() == SP::FpABSD || + MI->getOpcode() == SP::FpNEGD) { + Changed = true; unsigned DestDReg = MI->getOperand(0).getReg(); unsigned SrcDReg = MI->getOperand(1).getReg(); - if (DestDReg != SrcDReg || MI->getOpcode() != V8::FpMOVD) { - unsigned EvenSrcReg = 0, OddSrcReg = 0, EvenDestReg = 0, OddDestReg = 0; - getDoubleRegPair(DestDReg, EvenDestReg, OddDestReg); - getDoubleRegPair(SrcDReg, EvenSrcReg, OddSrcReg); - - I->setOpcode(V8::FMOVS); - I->SetMachineOperandReg(0, EvenDestReg); - I->SetMachineOperandReg(1, EvenSrcReg); - DEBUG(std::cerr << "FPMover: the modified instr is: " << *I); - // Insert copy for the other half of the double: - MI = BuildMI(MBB, I, V8::FMOVS, 1, OddDestReg).addReg(OddSrcReg); - DEBUG(std::cerr << "FPMover: the inserted instr is: " << *MI); - ++NumFpDs; - } else { - MBB.erase(MI); + if (DestDReg == SrcDReg && MI->getOpcode() == SP::FpMOVD) { + MBB.erase(MI); // Eliminate the noop copy. ++NoopFpDs; + continue; } - Changed = true; + + unsigned EvenSrcReg = 0, OddSrcReg = 0, EvenDestReg = 0, OddDestReg = 0; + getDoubleRegPair(DestDReg, EvenDestReg, OddDestReg); + getDoubleRegPair(SrcDReg, EvenSrcReg, OddSrcReg); + + const TargetInstrInfo *TII = TM.getInstrInfo(); + if (MI->getOpcode() == SP::FpMOVD) + MI->setDesc(TII->get(SP::FMOVS)); + else if (MI->getOpcode() == SP::FpNEGD) + MI->setDesc(TII->get(SP::FNEGS)); + else if (MI->getOpcode() == SP::FpABSD) + MI->setDesc(TII->get(SP::FABSS)); + else + llvm_unreachable("Unknown opcode!"); + + MI->getOperand(0).setReg(EvenDestReg); + MI->getOperand(1).setReg(EvenSrcReg); + DEBUG(errs() << "FPMover: the modified instr is: " << *MI); + // Insert copy for the other half of the double. + if (DestDReg != SrcDReg) { + MI = BuildMI(MBB, I, dl, TM.getInstrInfo()->get(SP::FMOVS), OddDestReg) + .addReg(OddSrcReg); + DEBUG(errs() << "FPMover: the inserted instr is: " << *MI); + } + ++NumFpDs; } } return Changed; } + +bool FPMover::runOnMachineFunction(MachineFunction &F) { + // If the target has V9 instructions, the fp-mover pseudos will never be + // emitted. Avoid a scan of the instructions to improve compile time. + if (TM.getSubtarget().isV9()) + return false; + + bool Changed = false; + for (MachineFunction::iterator FI = F.begin(), FE = F.end(); + FI != FE; ++FI) + Changed |= runOnMachineBasicBlock(*FI); + return Changed; +}