X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FSparc%2FMakefile;h=4b81ada956f2ece540d7c344e03640909d529081;hb=6a2e7ac0b6647a409394e58b385e579ea62b5cba;hp=e2a09cfa735852dc423905d8458c37d66146fcbe;hpb=e785e531f4495068ee46cabd926939eec15a565a;p=oota-llvm.git

diff --git a/lib/Target/Sparc/Makefile b/lib/Target/Sparc/Makefile
index e2a09cfa735..4b81ada956f 100644
--- a/lib/Target/Sparc/Makefile
+++ b/lib/Target/Sparc/Makefile
@@ -1,55 +1,22 @@
-##===- lib/Target/SparcV8/Makefile -------------------------*- Makefile -*-===##
-# 
+##===- lib/Target/Sparc/Makefile ---------------------------*- Makefile -*-===##
+#
 #                     The LLVM Compiler Infrastructure
 #
-# This file was developed by the LLVM research group and is distributed under
-# the University of Illinois Open Source License. See LICENSE.TXT for details.
-# 
+# This file is distributed under the University of Illinois Open Source
+# License. See LICENSE.TXT for details.
+#
 ##===----------------------------------------------------------------------===##
+
 LEVEL = ../../..
-LIBRARYNAME = sparcv8
-include $(LEVEL)/Makefile.common
+LIBRARYNAME = LLVMSparcCodeGen
+TARGET = Sparc
 
 # Make sure that tblgen is run, first thing.
-$(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
-                 SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
-                 SparcV8GenInstrInfo.inc SparcV8GenInstrSelector.inc
-
-SparcV8GenRegisterNames.inc:: $(SourceDir)/SparcV8.td \
-                           $(SourceDir)/SparcV8Reg.td \
-                           $(SourceDir)/../Target.td $(TBLGEN)
-	@echo "Building SparcV8.td register names with tblgen"
-	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
+BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrInfo.inc \
+		SparcGenAsmWriter.inc SparcGenDAGISel.inc \
+		SparcGenSubtargetInfo.inc SparcGenCallingConv.inc
 
-SparcV8GenRegisterInfo.h.inc:: $(SourceDir)/SparcV8.td \
-                           $(SourceDir)/SparcV8Reg.td \
-                           $(SourceDir)/../Target.td $(TBLGEN)
-	@echo "Building SparcV8.td register information header with tblgen"
-	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
+DIRS = TargetInfo MCTargetDesc
 
-SparcV8GenRegisterInfo.inc:: $(SourceDir)/SparcV8.td \
-                         $(SourceDir)/SparcV8Reg.td \
-                         $(SourceDir)/../Target.td $(TBLGEN)
-	@echo "Building SparcV8.td register information implementation with tblgen"
-	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
-
-SparcV8GenInstrNames.inc:: $(SourceDir)/SparcV8.td \
-                       $(SourceDir)/SparcV8Instrs.td \
-                       $(SourceDir)/../Target.td $(TBLGEN)
-	@echo "Building SparcV8.td instruction names with tblgen"
-	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
-
-SparcV8GenInstrInfo.inc:: $(SourceDir)/SparcV8.td \
-                      $(SourceDir)/SparcV8Instrs.td \
-                      $(SourceDir)/../Target.td $(TBLGEN)
-	@echo "Building SparcV8.td instruction information with tblgen"
-	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
-
-SparcV8GenInstrSelector.inc:: $(SourceDir)/SparcV8.td \
-                          $(SourceDir)/SparcV8Instrs.td \
-                          $(SourceDir)/../Target.td $(TBLGEN)
-	@echo "Building SparcV8.td instruction selector with tblgen"
-	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
+include $(LEVEL)/Makefile.common
 
-clean::
-	$(VERB) rm -f *.inc