X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FSparc%2FSparc.td;h=3159a4651ac9061c43a98ff9f2db7cd8a22d3b38;hb=4638c993331b04c73453927cb0b9909fa0dbd282;hp=53ea8f4a35f0fd295ea62855363b820174d5bbfd;hpb=027fdbe3ba6762b9867c6f891d64f76b7d6a4557;p=oota-llvm.git diff --git a/lib/Target/Sparc/Sparc.td b/lib/Target/Sparc/Sparc.td index 53ea8f4a35f..3159a4651ac 100644 --- a/lib/Target/Sparc/Sparc.td +++ b/lib/Target/Sparc/Sparc.td @@ -1,10 +1,10 @@ -//===- Sparc.td - Describe the Sparc Target Machine -------------*- C++ -*-===// -// +//===-- Sparc.td - Describe the Sparc Target Machine -------*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // @@ -19,7 +19,7 @@ include "llvm/Target/Target.td" //===----------------------------------------------------------------------===// // SPARC Subtarget features. // - + def FeatureV9 : SubtargetFeature<"v9", "IsV9", "true", "Enable SPARC-V9 instructions">; @@ -29,6 +29,19 @@ def FeatureV8Deprecated def FeatureVIS : SubtargetFeature<"vis", "IsVIS", "true", "Enable UltraSPARC Visual Instruction Set extensions">; +def FeatureVIS2 + : SubtargetFeature<"vis2", "IsVIS2", "true", + "Enable Visual Instruction Set extensions II">; +def FeatureVIS3 + : SubtargetFeature<"vis3", "IsVIS3", "true", + "Enable Visual Instruction Set extensions III">; + +def FeatureHardQuad + : SubtargetFeature<"hard-quad-float", "HasHardQuad", "true", + "Enable quad-word floating point instructions">; + +def UsePopc : SubtargetFeature<"popc", "UsePopc", "true", + "Use the popc (population count) instruction">; //===----------------------------------------------------------------------===// // Register File, Calling Conv, Instruction Descriptions @@ -38,10 +51,10 @@ include "SparcRegisterInfo.td" include "SparcCallingConv.td" include "SparcInstrInfo.td" -def SparcInstrInfo : InstrInfo { - // Define how we want to layout our target-specific information field. - let TSFlagsFields = []; - let TSFlagsShifts = []; +def SparcInstrInfo : InstrInfo; + +def SparcAsmParser : AsmParser { + bit ShouldEmitMatchRegisterName = 0; } //===----------------------------------------------------------------------===// @@ -52,6 +65,7 @@ class Proc Features> : Processor; def : Proc<"generic", []>; +def : Proc<"v7", []>; def : Proc<"v8", []>; def : Proc<"supersparc", []>; def : Proc<"sparclite", []>; @@ -61,9 +75,17 @@ def : Proc<"sparclite86x", []>; def : Proc<"sparclet", []>; def : Proc<"tsc701", []>; def : Proc<"v9", [FeatureV9]>; -def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated]>; -def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated]>; -def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>; +def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>; +def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS, + FeatureVIS2]>; +def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS, + FeatureVIS2]>; +def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc, + FeatureVIS, FeatureVIS2]>; +def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc, + FeatureVIS, FeatureVIS2]>; +def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc, + FeatureVIS, FeatureVIS2, FeatureVIS3]>; //===----------------------------------------------------------------------===// @@ -73,4 +95,5 @@ def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>; def Sparc : Target { // Pull in Instruction Info: let InstructionSet = SparcInstrInfo; + let AssemblyParsers = [SparcAsmParser]; }