X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FSparc%2FSparc.td;h=d42c40faa15ae1bc18c22a0918a8035e60b9b28f;hb=e67a4afb5da59c02338622eea68e096ba143113f;hp=928689ca8b80705edaa1f9785a66b9ae6af8aa5b;hpb=e785e531f4495068ee46cabd926939eec15a565a;p=oota-llvm.git diff --git a/lib/Target/Sparc/Sparc.td b/lib/Target/Sparc/Sparc.td index 928689ca8b8..d42c40faa15 100644 --- a/lib/Target/Sparc/Sparc.td +++ b/lib/Target/Sparc/Sparc.td @@ -1,41 +1,72 @@ -//===- SparcV8.td - Describe the SparcV8 Target Machine ---------*- C++ -*-===// -// +//===-- Sparc.td - Describe the Sparc Target Machine -------*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// //===----------------------------------------------------------------------===// // // //===----------------------------------------------------------------------===// -// Get the target-independent interfaces which we are implementing... +//===----------------------------------------------------------------------===// +// Target-independent interfaces which we are implementing +//===----------------------------------------------------------------------===// + +include "llvm/Target/Target.td" + +//===----------------------------------------------------------------------===// +// SPARC Subtarget features. // -include "../Target.td" + +def FeatureV9 + : SubtargetFeature<"v9", "IsV9", "true", + "Enable SPARC-V9 instructions">; +def FeatureV8Deprecated + : SubtargetFeature<"deprecated-v8", "V8DeprecatedInsts", "true", + "Enable deprecated V8 instructions in V9 mode">; +def FeatureVIS + : SubtargetFeature<"vis", "IsVIS", "true", + "Enable UltraSPARC Visual Instruction Set extensions">; //===----------------------------------------------------------------------===// -// Register File Description +// Register File, Calling Conv, Instruction Descriptions //===----------------------------------------------------------------------===// -include "SparcV8Reg.td" -include "SparcV8Instrs.td" +include "SparcRegisterInfo.td" +include "SparcCallingConv.td" +include "SparcInstrInfo.td" -def SparcV8InstrInfo : InstrInfo { - let PHIInst = PHI; -} +def SparcInstrInfo : InstrInfo; + +//===----------------------------------------------------------------------===// +// SPARC processors supported. +//===----------------------------------------------------------------------===// -def SparcV8 : Target { - // Pointers are 32-bits in size. - let PointerType = i32; +class Proc Features> + : Processor; - // According to the Mach-O Runtime ABI, these regs are nonvolatile across - // calls: - let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19, - R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15, - F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, - F30, F31, CR2, CR3, CR4]; +def : Proc<"generic", []>; +def : Proc<"v8", []>; +def : Proc<"supersparc", []>; +def : Proc<"sparclite", []>; +def : Proc<"f934", []>; +def : Proc<"hypersparc", []>; +def : Proc<"sparclite86x", []>; +def : Proc<"sparclet", []>; +def : Proc<"tsc701", []>; +def : Proc<"v9", [FeatureV9]>; +def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated]>; +def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated]>; +def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>; + + +//===----------------------------------------------------------------------===// +// Declare the target which we are implementing +//===----------------------------------------------------------------------===// +def Sparc : Target { // Pull in Instruction Info: - let InstructionSet = SparcV8InstrInfo; + let InstructionSet = SparcInstrInfo; }