X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FSparc%2FSparcInstrFormats.td;h=6535259e16ffec9157df578719842900f718ba56;hb=5ed5506f18fcc0a277c863f7a21b39f58e892ca5;hp=9b15aeed50cb7357ef2aeaaa3760fb0dc9d83872;hpb=eee99bd459ab17a498d076f27de313398b9d3d4d;p=oota-llvm.git

diff --git a/lib/Target/Sparc/SparcInstrFormats.td b/lib/Target/Sparc/SparcInstrFormats.td
index 9b15aeed50c..6535259e16f 100644
--- a/lib/Target/Sparc/SparcInstrFormats.td
+++ b/lib/Target/Sparc/SparcInstrFormats.td
@@ -1,32 +1,33 @@
-//===- SparcV8InstrFormats.td - SparcV8 Instr Formats ------*- tablegen -*-===//
+//===- SparcInstrFormats.td - Sparc Instruction Formats ----*- tablegen -*-===//
 // 
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 // 
 //===----------------------------------------------------------------------===//
 
-class InstV8<dag ops, string asmstr, list<dag> pattern> : Instruction {
+class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
   field bits<32> Inst;
 
-  let Namespace = "V8";
+  let Namespace = "SP";
 
   bits<2> op;
   let Inst{31-30} = op;               // Top two bits are the 'op' field
   
-  dag OperandList = ops;
+  dag OutOperandList = outs;
+  dag InOperandList = ins;
   let AsmString   = asmstr;
   let Pattern = pattern;
 }
 
 //===----------------------------------------------------------------------===//
-// Format #2 instruction classes in the SparcV8
+// Format #2 instruction classes in the Sparc
 //===----------------------------------------------------------------------===//
 
 // Format 2 instructions
-class F2<dag ops, string asmstr, list<dag> pattern>
-   : InstV8<ops, asmstr, pattern> {
+class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
+   : InstSP<outs, ins, asmstr, pattern> {
   bits<3>  op2;
   bits<22> imm22;
   let op          = 0;    // op = 0
@@ -36,8 +37,8 @@ class F2<dag ops, string asmstr, list<dag> pattern>
 
 // Specific F2 classes: SparcV8 manual, page 44
 //
-class F2_1<bits<3> op2Val, dag ops, string asmstr, list<dag> pattern>
-   : F2<ops, asmstr, pattern> {
+class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
+   : F2<outs, ins, asmstr, pattern> {
   bits<5>  rd;
 
   let op2         = op2Val;
@@ -45,8 +46,8 @@ class F2_1<bits<3> op2Val, dag ops, string asmstr, list<dag> pattern>
   let Inst{29-25} = rd;
 }
 
-class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr, 
-           list<dag> pattern> : F2<ops, asmstr, pattern> {
+class F2_2<bits<4> condVal, bits<3> op2Val, dag outs, dag ins, string asmstr, 
+           list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
   bits<4>   cond;
   bit       annul = 0;     // currently unused
 
@@ -58,11 +59,11 @@ class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr,
 }
 
 //===----------------------------------------------------------------------===//
-// Format #3 instruction classes in the SparcV8
+// Format #3 instruction classes in the Sparc
 //===----------------------------------------------------------------------===//
 
-class F3<dag ops, string asmstr, list<dag> pattern>
-    : InstV8<ops, asmstr, pattern> {
+class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
+    : InstSP<outs, ins, asmstr, pattern> {
   bits<5> rd;
   bits<6> op3;
   bits<5> rs1;
@@ -74,9 +75,9 @@ class F3<dag ops, string asmstr, list<dag> pattern>
 
 // Specific F3 classes: SparcV8 manual, page 44
 //
-class F3_1<bits<2> opVal, bits<6> op3val, dag ops,
-           string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
-  bits<8> asi = 0; // asi not currently used in SparcV8
+class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
+           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
+  bits<8> asi = 0; // asi not currently used
   bits<5> rs2;
 
   let op         = opVal;
@@ -87,8 +88,8 @@ class F3_1<bits<2> opVal, bits<6> op3val, dag ops,
   let Inst{4-0}  = rs2;
 }
 
-class F3_2<bits<2> opVal, bits<6> op3val, dag ops, 
-           string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
+class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 
+           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
   bits<13> simm13;
 
   let op         = opVal;
@@ -99,8 +100,8 @@ class F3_2<bits<2> opVal, bits<6> op3val, dag ops,
 }
 
 // floating-point
-class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag ops,
-           string asmstr, list<dag> pattern> : F3<ops, asmstr, pattern> {
+class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
+           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
   bits<5> rs2;
 
   let op         = opVal;
@@ -109,3 +110,5 @@ class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag ops,
   let Inst{13-5} = opfval;   // fp opcode
   let Inst{4-0}  = rs2;
 }
+
+