X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FSparc%2FSparcRegisterInfo.cpp;h=b010d04a27d132338db9e71d1f1f42ef60122c24;hb=4abce0c90b0c7c7c859951069baf0c0a70e085a9;hp=7b258567304afe95c3e29a3ddf3baff5244f13f4;hpb=43875e63f323ee01a08e0f2709213f2f84ff66c7;p=oota-llvm.git diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index 7b258567304..b010d04a27d 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -1,163 +1,134 @@ -//===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===// +//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===// // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // -// This file contains the SparcV8 implementation of the MRegisterInfo class. +// This file contains the SPARC implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// -#include "SparcV8.h" -#include "SparcV8RegisterInfo.h" +#include "Sparc.h" +#include "SparcRegisterInfo.h" +#include "SparcSubtarget.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineLocation.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Type.h" +#include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" -#include using namespace llvm; -SparcV8RegisterInfo::SparcV8RegisterInfo() - : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN, - V8::ADJCALLSTACKUP) {} - -void SparcV8RegisterInfo:: -storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned SrcReg, int FrameIdx, - const TargetRegisterClass *RC) const { - // On the order of operands here: think "[FrameIdx + 0] = SrcReg". - if (RC == V8::IntRegsRegisterClass) - BuildMI (MBB, I, V8::STri, 3).addFrameIndex (FrameIdx).addSImm (0) - .addReg (SrcReg); - else if (RC == V8::FPRegsRegisterClass) - BuildMI (MBB, I, V8::STFri, 3).addFrameIndex (FrameIdx).addSImm (0) - .addReg (SrcReg); - else if (RC == V8::DFPRegsRegisterClass) - BuildMI (MBB, I, V8::STDFri, 3).addFrameIndex (FrameIdx).addSImm (0) - .addReg (SrcReg); - else - assert (0 && "Can't store this register to stack slot"); +SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st, + const TargetInstrInfo &tii) + : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), + Subtarget(st), TII(tii) { } -void SparcV8RegisterInfo:: -loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned DestReg, int FrameIdx, - const TargetRegisterClass *RC) const { - if (RC == V8::IntRegsRegisterClass) - BuildMI (MBB, I, V8::LDri, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0); - else if (RC == V8::FPRegsRegisterClass) - BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx) - .addSImm (0); - else if (RC == V8::DFPRegsRegisterClass) - BuildMI (MBB, I, V8::LDDFri, 2, DestReg).addFrameIndex (FrameIdx) - .addSImm (0); - else - assert(0 && "Can't load this register from stack slot"); +const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) + const { + static const unsigned CalleeSavedRegs[] = { 0 }; + return CalleeSavedRegs; } -void SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const { - if (RC == V8::IntRegsRegisterClass) - BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg); - else if (RC == V8::FPRegsRegisterClass) - BuildMI (MBB, I, V8::FMOVS, 1, DestReg).addReg (SrcReg); - else if (RC == V8::DFPRegsRegisterClass) - BuildMI (MBB, I, V8::FpMOVD, 1, DestReg).addReg (SrcReg); - else - assert (0 && "Can't copy this register"); +BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const { + BitVector Reserved(getNumRegs()); + Reserved.set(SP::G2); + Reserved.set(SP::G3); + Reserved.set(SP::G4); + Reserved.set(SP::O6); + Reserved.set(SP::I6); + Reserved.set(SP::I7); + Reserved.set(SP::G0); + Reserved.set(SP::G5); + Reserved.set(SP::G6); + Reserved.set(SP::G7); + return Reserved; } -void SparcV8RegisterInfo:: +void SparcRegisterInfo:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { MachineInstr &MI = *I; - int Size = MI.getOperand(0).getImmedValue(); - if (MI.getOpcode() == V8::ADJCALLSTACKDOWN) + DebugLoc dl = MI.getDebugLoc(); + int Size = MI.getOperand(0).getImm(); + if (MI.getOpcode() == SP::ADJCALLSTACKDOWN) Size = -Size; if (Size) - BuildMI(MBB, I, V8::ADDri, 2, V8::O6).addReg(V8::O6).addSImm(Size); + BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size); MBB.erase(I); } void -SparcV8RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { +SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, + int SPAdj, RegScavenger *RS) const { + assert(SPAdj == 0 && "Unexpected"); + unsigned i = 0; MachineInstr &MI = *II; - while (!MI.getOperand(i).isFrameIndex()) { + DebugLoc dl = MI.getDebugLoc(); + while (!MI.getOperand(i).isFI()) { ++i; assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); } - int FrameIndex = MI.getOperand(i).getFrameIndex(); - - // Replace frame index with a frame pointer reference - MI.SetMachineOperandReg (i, V8::I6); + int FrameIndex = MI.getOperand(i).getIndex(); // Addressable stack objects are accessed using neg. offsets from %fp MachineFunction &MF = *MI.getParent()->getParent(); int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + - MI.getOperand(i+1).getImmedValue(); - // note: Offset < 0 - MI.SetMachineOperandConst (i+1, MachineOperand::MO_SignExtendedImmed, Offset); + MI.getOperand(i+1).getImm(); + + // Replace frame index with a frame pointer reference. + if (Offset >= -4096 && Offset <= 4095) { + // If the offset is small enough to fit in the immediate field, directly + // encode it. + MI.getOperand(i).ChangeToRegister(SP::I6, false); + MI.getOperand(i+1).ChangeToImmediate(Offset); + } else { + // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to + // scavenge a register here instead of reserving G1 all of the time. + unsigned OffHi = (unsigned)Offset >> 10U; + BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); + // Emit G1 = G1 + I6 + BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) + .addReg(SP::I6); + // Insert: G1+%lo(offset) into the user. + MI.getOperand(i).ChangeToRegister(SP::G1, false); + MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1)); + } } -void SparcV8RegisterInfo:: +void SparcRegisterInfo:: processFunctionBeforeFrameFinalized(MachineFunction &MF) const {} -void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const { - MachineBasicBlock &MBB = MF.front(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - - // Get the number of bytes to allocate from the FrameInfo - int NumBytes = (int) MFI->getStackSize(); - - // Emit the correct save instruction based on the number of bytes in - // the frame. Minimum stack frame size according to V8 ABI is: - // 16 words for register window spill - // 1 word for address of returned aggregate-value - // + 6 words for passing parameters on the stack - // ---------- - // 23 words * 4 bytes per word = 92 bytes - NumBytes += 92; - // Round up to next doubleword boundary -- a double-word boundary - // is required by the ABI. - NumBytes = (NumBytes + 7) & ~7; - BuildMI(MBB, MBB.begin(), V8::SAVEri, 2, - V8::O6).addImm(-NumBytes).addReg(V8::O6); +unsigned SparcRegisterInfo::getRARegister() const { + return SP::I7; } -void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { - MachineBasicBlock::iterator MBBI = prior(MBB.end()); - assert(MBBI->getOpcode() == V8::RETL && - "Can only put epilog before 'retl' instruction!"); - BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0); +unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const { + return SP::I6; } -#include "SparcV8GenRegisterInfo.inc" - -const TargetRegisterClass* -SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const { - switch (Ty->getTypeID()) { - case Type::FloatTyID: return V8::FPRegsRegisterClass; - case Type::DoubleTyID: return V8::DFPRegsRegisterClass; - case Type::LongTyID: - case Type::ULongTyID: assert(0 && "Long values do not fit in registers!"); - default: assert(0 && "Invalid type to getClass!"); - case Type::BoolTyID: - case Type::SByteTyID: - case Type::UByteTyID: - case Type::ShortTyID: - case Type::UShortTyID: - case Type::IntTyID: - case Type::UIntTyID: - case Type::PointerTyID: return V8::IntRegsRegisterClass; - } +unsigned SparcRegisterInfo::getEHExceptionRegister() const { + llvm_unreachable("What is the exception register"); + return 0; } +unsigned SparcRegisterInfo::getEHHandlerRegister() const { + llvm_unreachable("What is the exception handler register"); + return 0; +} + +int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { + return SparcGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); +} + +#include "SparcGenRegisterInfo.inc" +