X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FSparc%2FSparcTargetMachine.cpp;h=b84eab568d2909b9d8206b5078a65ea4b4d0ace1;hb=a5e62019d771fd0b01311cc0136e64b66b299eb1;hp=ed133489bed1004d302114b9e74dd421b791cd59;hpb=a9a582fbb6f0c9e24bebda73f0a13e560f2d3c5e;p=oota-llvm.git diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp index ed133489bed..b84eab568d2 100644 --- a/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/lib/Target/Sparc/SparcTargetMachine.cpp @@ -1,135 +1,67 @@ -//===-- SparcV8TargetMachine.cpp - Define TargetMachine for SparcV8 -------===// -// +//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===// +// // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// //===----------------------------------------------------------------------===// -// +// // //===----------------------------------------------------------------------===// -#include "SparcV8TargetMachine.h" -#include "SparcV8.h" -#include "llvm/Module.h" +#include "Sparc.h" +#include "SparcMCAsmInfo.h" +#include "SparcTargetMachine.h" #include "llvm/PassManager.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/Passes.h" -#include "llvm/Target/TargetMachineImpls.h" -#include "llvm/Transforms/Scalar.h" +#include "llvm/Target/TargetRegistry.h" using namespace llvm; -// allocateSparcV8TargetMachine - Allocate and return a subclass of -// TargetMachine that implements the SparcV8 backend. -// -TargetMachine *llvm::allocateSparcV8TargetMachine(const Module &M, - IntrinsicLowering *IL) { - return new SparcV8TargetMachine(M, IL); -} +extern "C" void LLVMInitializeSparcTarget() { + // Register the target. + RegisterTargetMachine X(TheSparcTarget); + RegisterTargetMachine Y(TheSparcV9Target); + + RegisterAsmInfo A(TheSparcTarget); + RegisterAsmInfo B(TheSparcV9Target); -/// SparcV8TargetMachine ctor - Create an ILP32 architecture model -/// -SparcV8TargetMachine::SparcV8TargetMachine(const Module &M, - IntrinsicLowering *IL) - : TargetMachine("SparcV8", IL, true, 4, 4, 4, 4, 4), - FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0), JITInfo(*this) { } -/// addPassesToEmitAssembly - Add passes to the specified pass manager -/// to implement a static compiler for this target. +/// SparcTargetMachine ctor - Create an ILP32 architecture model /// -bool SparcV8TargetMachine::addPassesToEmitAssembly(PassManager &PM, - std::ostream &Out) { - // FIXME: Implement efficient support for garbage collection intrinsics. - PM.add(createLowerGCPass()); - - // Replace malloc and free instructions with library calls. - PM.add(createLowerAllocationsPass()); - - // FIXME: implement the select instruction in the instruction selector. - PM.add(createLowerSelectPass()); - - // FIXME: implement the switch instruction in the instruction selector. - PM.add(createLowerSwitchPass()); - - // FIXME: implement the invoke/unwind instructions! - PM.add(createLowerInvokePass()); - - PM.add(createLowerConstantExpressionsPass()); - - // Make sure that no unreachable blocks are instruction selected. - PM.add(createUnreachableBlockEliminationPass()); - - PM.add(createSparcV8SimpleInstructionSelector(*this)); - - // Print machine instructions as they were initially generated. - if (PrintMachineCode) - PM.add(createMachineFunctionPrinterPass(&std::cerr)); - - PM.add(createRegisterAllocator()); - PM.add(createPrologEpilogCodeInserter()); - - // Print machine instructions after register allocation and prolog/epilog - // insertion. - if (PrintMachineCode) - PM.add(createMachineFunctionPrinterPass(&std::cerr)); - - PM.add(createSparcV8DelaySlotFillerPass(*this)); - - // Print machine instructions after filling delay slots. - if (PrintMachineCode) - PM.add(createMachineFunctionPrinterPass(&std::cerr)); - - // Output assembly language. - PM.add(createSparcV8CodePrinterPass(Out, *this)); +SparcTargetMachine::SparcTargetMachine(const Target &T, const std::string &TT, + const std::string &FS, bool is64bit) + : LLVMTargetMachine(T, TT), + Subtarget(TT, FS, is64bit), + DataLayout(Subtarget.getDataLayout()), + TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget), + FrameLowering(Subtarget) { +} - // Delete the MachineInstrs we generated, since they're no longer needed. - PM.add(createMachineCodeDeleter()); +bool SparcTargetMachine::addInstSelector(PassManagerBase &PM, + CodeGenOpt::Level OptLevel) { + PM.add(createSparcISelDag(*this)); return false; } -/// addPassesToJITCompile - Add passes to the specified pass manager to -/// implement a fast dynamic compiler for this target. -/// -void SparcV8JITInfo::addPassesToJITCompile(FunctionPassManager &PM) { - // FIXME: Implement efficient support for garbage collection intrinsics. - PM.add(createLowerGCPass()); - - // Replace malloc and free instructions with library calls. - PM.add(createLowerAllocationsPass()); - - // FIXME: implement the select instruction in the instruction selector. - PM.add(createLowerSelectPass()); - - // FIXME: implement the switch instruction in the instruction selector. - PM.add(createLowerSwitchPass()); - - // FIXME: implement the invoke/unwind instructions! - PM.add(createLowerInvokePass()); - - PM.add(createLowerConstantExpressionsPass()); - - // Make sure that no unreachable blocks are instruction selected. - PM.add(createUnreachableBlockEliminationPass()); - - PM.add(createSparcV8SimpleInstructionSelector(TM)); - - // Print machine instructions as they were initially generated. - if (PrintMachineCode) - PM.add(createMachineFunctionPrinterPass(&std::cerr)); - - PM.add(createRegisterAllocator()); - PM.add(createPrologEpilogCodeInserter()); - - // Print machine instructions after register allocation and prolog/epilog - // insertion. - if (PrintMachineCode) - PM.add(createMachineFunctionPrinterPass(&std::cerr)); +/// addPreEmitPass - This pass may be implemented by targets that want to run +/// passes immediately before machine code is emitted. This should return +/// true if -print-machineinstrs should print out the code after the passes. +bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, + CodeGenOpt::Level OptLevel){ + PM.add(createSparcFPMoverPass(*this)); + PM.add(createSparcDelaySlotFillerPass(*this)); + return true; +} - PM.add(createSparcV8DelaySlotFillerPass(TM)); +SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, + const std::string &TT, + const std::string &FS) + : SparcTargetMachine(T, TT, FS, false) { +} - // Print machine instructions after filling delay slots. - if (PrintMachineCode) - PM.add(createMachineFunctionPrinterPass(&std::cerr)); +SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, + const std::string &TT, + const std::string &FS) + : SparcTargetMachine(T, TT, FS, true) { }