X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FSparcV9%2FSparcV9InstrSelection.cpp;h=5195f4ac29faef839c3603f35fff817e89f62238;hb=edf3a727b7106cfa9f10aadd5e6f603bcc0b879f;hp=9c556faed95924bc0d44e20e7841764eab068b21;hpb=243dd45820022c0f3829673715d07a775c65c04b;p=oota-llvm.git diff --git a/lib/Target/SparcV9/SparcV9InstrSelection.cpp b/lib/Target/SparcV9/SparcV9InstrSelection.cpp index 9c556faed95..5195f4ac29f 100644 --- a/lib/Target/SparcV9/SparcV9InstrSelection.cpp +++ b/lib/Target/SparcV9/SparcV9InstrSelection.cpp @@ -1,186 +1,32 @@ -// $Id$ -//*************************************************************************** -// File: -// SparcInstrSelection.cpp -// -// Purpose: -// -// History: -// 7/02/01 - Vikram Adve - Created -//**************************************************************************/ +//===-- SparcInstrSelection.cpp -------------------------------------------===// +// +// BURS instruction selection for SPARC V9 architecture. +// +//===----------------------------------------------------------------------===// #include "SparcInternals.h" +#include "SparcInstrSelectionSupport.h" +#include "SparcRegClassInfo.h" +#include "llvm/CodeGen/InstrSelectionSupport.h" #include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineInstrAnnot.h" #include "llvm/CodeGen/InstrForest.h" #include "llvm/CodeGen/InstrSelection.h" -#include "llvm/Support/MathExtras.h" +#include "llvm/CodeGen/MachineCodeForMethod.h" +#include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/DerivedTypes.h" #include "llvm/iTerminators.h" #include "llvm/iMemory.h" #include "llvm/iOther.h" -#include "llvm/BasicBlock.h" -#include "llvm/Method.h" -#include "llvm/ConstPoolVals.h" - - -//******************** Internal Data Declarations ************************/ - -// to be used later -struct BranchPattern { - bool flipCondition; // should the sense of the test be reversed - BasicBlock* targetBB; // which basic block to branch to - MachineInstr* extraBranch; // if neither branch is fall-through, then this - // BA must be inserted after the cond'l one -}; - -//************************* Forward Declarations ***************************/ - - -static MachineOpCode ChooseBprInstruction (const InstructionNode* instrNode); - -static MachineOpCode ChooseBccInstruction (const InstructionNode* instrNode, - bool& isFPBranch); - -static MachineOpCode ChooseBpccInstruction (const InstructionNode* instrNode, - const BinaryOperator* setCCInst); - -static MachineOpCode ChooseBFpccInstruction (const InstructionNode* instrNode, - const BinaryOperator* setCCInst); - -static MachineOpCode ChooseMovFpccInstruction(const InstructionNode*); - -static MachineOpCode ChooseMovpccAfterSub (const InstructionNode* instrNode, - bool& mustClearReg, - int& valueToMove); - -static MachineOpCode ChooseConvertToFloatInstr(const InstructionNode*, - const Type* opType); - -static MachineOpCode ChooseConvertToIntInstr(const InstructionNode* instrNode, - const Type* opType); - -static MachineOpCode ChooseAddInstruction (const InstructionNode* instrNode); - -static MachineOpCode ChooseSubInstruction (const InstructionNode* instrNode); - -static MachineOpCode ChooseFcmpInstruction (const InstructionNode* instrNode); - -static MachineOpCode ChooseMulInstruction (const InstructionNode* instrNode, - bool checkCasts); - -static MachineOpCode ChooseDivInstruction (const InstructionNode* instrNode); - -static MachineOpCode ChooseLoadInstruction (const Type* resultType); - -static MachineOpCode ChooseStoreInstruction (const Type* valueType); - -static void SetOperandsForMemInstr(MachineInstr* minstr, - const InstructionNode* vmInstrNode, - const TargetMachine& target); - -static void SetMemOperands_Internal (MachineInstr* minstr, - const InstructionNode* vmInstrNode, - Value* ptrVal, - Value* arrayOffsetVal, - const vector& idxVec, - const TargetMachine& target); - -static unsigned FixConstantOperands(const InstructionNode* vmInstrNode, - MachineInstr** mvec, - unsigned numInstr, - TargetMachine& target); - -static MachineInstr* MakeLoadConstInstr(Instruction* vmInstr, - Value* val, - TmpInstruction*& tmpReg, - MachineInstr*& getMinstr2); - -static void ForwardOperand (InstructionNode* treeNode, - InstrTreeNode* parent, - int operandNum); - +#include "llvm/Function.h" +#include "llvm/Constants.h" +#include "llvm/ConstantHandling.h" +#include "Support/MathExtras.h" +#include +using std::vector; //************************ Internal Functions ******************************/ -// Convenience function to get the value of an integer constant, for an -// appropriate integer or non-integer type that can be held in an integer. -// The type of the argument must be the following: -// Signed or unsigned integer -// Boolean -// Pointer -// -// isValidConstant is set to true if a valid constant was found. -// -static int64_t -GetConstantValueAsSignedInt(const Value *V, - bool &isValidConstant) -{ - if (!V->isConstant()) { isValidConstant = false; return 0; } - isValidConstant = true; - - if (V->getType() == Type::BoolTy) - return ((ConstPoolBool*)V)->getValue(); - if (V->getType()->isIntegral()) { - if (V->getType()->isSigned()) - return ((ConstPoolSInt*)V)->getValue(); - - assert(V->getType()->isUnsigned()); - uint64_t Val = ((ConstPoolUInt*)V)->getValue(); - - if (Val < INT64_MAX) // then safe to cast to signed - return (int64_t)Val; - } - - isValidConstant = false; - return 0; -} - - - -//------------------------------------------------------------------------ -// External Function: ThisIsAChainRule -// -// Purpose: -// Check if a given BURG rule is a chain rule. -//------------------------------------------------------------------------ - -extern bool -ThisIsAChainRule(int eruleno) -{ - switch(eruleno) - { - case 111: // stmt: reg - case 112: // stmt: boolconst - case 113: // stmt: bool - case 121: - case 122: - case 123: - case 124: - case 125: - case 126: - case 127: - case 128: - case 129: - case 130: - case 131: - case 132: - case 133: - case 153: - case 155: - case 221: - case 222: - case 232: - case 241: - case 242: - case 243: - case 244: - return true; break; - - default: - return false; break; - } -} - static inline MachineOpCode ChooseBprInstruction(const InstructionNode* instrNode) @@ -208,26 +54,9 @@ ChooseBprInstruction(const InstructionNode* instrNode) } -static inline MachineOpCode -ChooseBccInstruction(const InstructionNode* instrNode, - bool& isFPBranch) -{ - InstructionNode* setCCNode = (InstructionNode*) instrNode->leftChild(); - BinaryOperator* setCCInstr = (BinaryOperator*) setCCNode->getInstruction(); - const Type* setCCType = setCCInstr->getOperand(0)->getType(); - - isFPBranch = (setCCType == Type::FloatTy || setCCType == Type::DoubleTy); - - if (isFPBranch) - return ChooseBFpccInstruction(instrNode, setCCInstr); - else - return ChooseBpccInstruction(instrNode, setCCInstr); -} - - static inline MachineOpCode ChooseBpccInstruction(const InstructionNode* instrNode, - const BinaryOperator* setCCInstr) + const BinaryOperator* setCCInstr) { MachineOpCode opCode = INVALID_OPCODE; @@ -236,32 +65,32 @@ ChooseBpccInstruction(const InstructionNode* instrNode, if (isSigned) { switch(setCCInstr->getOpcode()) - { - case Instruction::SetEQ: opCode = BE; break; - case Instruction::SetNE: opCode = BNE; break; - case Instruction::SetLE: opCode = BLE; break; - case Instruction::SetGE: opCode = BGE; break; - case Instruction::SetLT: opCode = BL; break; - case Instruction::SetGT: opCode = BG; break; - default: - assert(0 && "Unrecognized VM instruction!"); - break; - } + { + case Instruction::SetEQ: opCode = BE; break; + case Instruction::SetNE: opCode = BNE; break; + case Instruction::SetLE: opCode = BLE; break; + case Instruction::SetGE: opCode = BGE; break; + case Instruction::SetLT: opCode = BL; break; + case Instruction::SetGT: opCode = BG; break; + default: + assert(0 && "Unrecognized VM instruction!"); + break; + } } else { switch(setCCInstr->getOpcode()) - { - case Instruction::SetEQ: opCode = BE; break; - case Instruction::SetNE: opCode = BNE; break; - case Instruction::SetLE: opCode = BLEU; break; - case Instruction::SetGE: opCode = BCC; break; - case Instruction::SetLT: opCode = BCS; break; - case Instruction::SetGT: opCode = BGU; break; - default: - assert(0 && "Unrecognized VM instruction!"); - break; - } + { + case Instruction::SetEQ: opCode = BE; break; + case Instruction::SetNE: opCode = BNE; break; + case Instruction::SetLE: opCode = BLEU; break; + case Instruction::SetGE: opCode = BCC; break; + case Instruction::SetLT: opCode = BCS; break; + case Instruction::SetGT: opCode = BGU; break; + default: + assert(0 && "Unrecognized VM instruction!"); + break; + } } return opCode; @@ -269,7 +98,7 @@ ChooseBpccInstruction(const InstructionNode* instrNode, static inline MachineOpCode ChooseBFpccInstruction(const InstructionNode* instrNode, - const BinaryOperator* setCCInstr) + const BinaryOperator* setCCInstr) { MachineOpCode opCode = INVALID_OPCODE; @@ -290,6 +119,57 @@ ChooseBFpccInstruction(const InstructionNode* instrNode, } +// Create a unique TmpInstruction for a boolean value, +// representing the CC register used by a branch on that value. +// For now, hack this using a little static cache of TmpInstructions. +// Eventually the entire BURG instruction selection should be put +// into a separate class that can hold such information. +// The static cache is not too bad because the memory for these +// TmpInstructions will be freed along with the rest of the Function anyway. +// +static TmpInstruction* +GetTmpForCC(Value* boolVal, const Function *F, const Type* ccType) +{ + typedef hash_map BoolTmpCache; + static BoolTmpCache boolToTmpCache; // Map boolVal -> TmpInstruction* + static const Function *lastFunction = 0;// Use to flush cache between funcs + + assert(boolVal->getType() == Type::BoolTy && "Weird but ok! Delete assert"); + + if (lastFunction != F) + { + lastFunction = F; + boolToTmpCache.clear(); + } + + // Look for tmpI and create a new one otherwise. The new value is + // directly written to map using the ref returned by operator[]. + TmpInstruction*& tmpI = boolToTmpCache[boolVal]; + if (tmpI == NULL) + tmpI = new TmpInstruction(ccType, boolVal); + + return tmpI; +} + + +static inline MachineOpCode +ChooseBccInstruction(const InstructionNode* instrNode, + bool& isFPBranch) +{ + InstructionNode* setCCNode = (InstructionNode*) instrNode->leftChild(); + assert(setCCNode->getOpLabel() == SetCCOp); + BinaryOperator* setCCInstr =cast(setCCNode->getInstruction()); + const Type* setCCType = setCCInstr->getOperand(0)->getType(); + + isFPBranch = setCCType->isFloatingPoint(); // Return value: don't delete! + + if (isFPBranch) + return ChooseBFpccInstruction(instrNode, setCCInstr); + else + return ChooseBpccInstruction(instrNode, setCCInstr); +} + + static inline MachineOpCode ChooseMovFpccInstruction(const InstructionNode* instrNode) { @@ -322,8 +202,8 @@ ChooseMovFpccInstruction(const InstructionNode* instrNode) // static MachineOpCode ChooseMovpccAfterSub(const InstructionNode* instrNode, - bool& mustClearReg, - int& valueToMove) + bool& mustClearReg, + int& valueToMove) { MachineOpCode opCode = INVALID_OPCODE; mustClearReg = true; @@ -343,39 +223,42 @@ ChooseMovpccAfterSub(const InstructionNode* instrNode, return opCode; } - static inline MachineOpCode -ChooseConvertToFloatInstr(const InstructionNode* instrNode, - const Type* opType) +ChooseConvertToFloatInstr(OpLabel vopCode, const Type* opType) { MachineOpCode opCode = INVALID_OPCODE; - switch(instrNode->getOpLabel()) + switch(vopCode) { case ToFloatTy: if (opType == Type::SByteTy || opType == Type::ShortTy || opType == Type::IntTy) - opCode = FITOS; + opCode = FITOS; else if (opType == Type::LongTy) - opCode = FXTOS; + opCode = FXTOS; else if (opType == Type::DoubleTy) - opCode = FDTOS; + opCode = FDTOS; else if (opType == Type::FloatTy) - ; + ; else - assert(0 && "Cannot convert this type to FLOAT on SPARC"); + assert(0 && "Cannot convert this type to FLOAT on SPARC"); break; case ToDoubleTy: - if (opType == Type::SByteTy || opType == Type::ShortTy || opType == Type::IntTy) - opCode = FITOD; - else if (opType == Type::LongTy) - opCode = FXTOD; + // This is usually used in conjunction with CreateCodeToCopyIntToFloat(). + // Both functions should treat the integer as a 32-bit value for types + // of 4 bytes or less, and as a 64-bit value otherwise. + if (opType == Type::SByteTy || opType == Type::UByteTy || + opType == Type::ShortTy || opType == Type::UShortTy || + opType == Type::IntTy || opType == Type::UIntTy) + opCode = FITOD; + else if (opType == Type::LongTy || opType == Type::ULongTy) + opCode = FXTOD; else if (opType == Type::FloatTy) - opCode = FSTOD; + opCode = FSTOD; else if (opType == Type::DoubleTy) - ; + ; else - assert(0 && "Cannot convert this type to DOUBLE on SPARC"); + assert(0 && "Cannot convert this type to DOUBLE on SPARC"); break; default: @@ -386,81 +269,109 @@ ChooseConvertToFloatInstr(const InstructionNode* instrNode, } static inline MachineOpCode -ChooseConvertToIntInstr(const InstructionNode* instrNode, - const Type* opType) +ChooseConvertFPToIntInstr(Type::PrimitiveID tid, const Type* opType) { MachineOpCode opCode = INVALID_OPCODE;; - - int instrType = (int) instrNode->getOpLabel(); - - if (instrType == ToSByteTy || instrType == ToShortTy || instrType == ToIntTy) + + assert((opType == Type::FloatTy || opType == Type::DoubleTy) + && "This function should only be called for FLOAT or DOUBLE"); + + if (tid==Type::UIntTyID) { - switch (opType->getPrimitiveID()) - { - case Type::FloatTyID: opCode = FSTOI; break; - case Type::DoubleTyID: opCode = FDTOI; break; - default: - assert(0 && "Non-numeric non-bool type cannot be converted to Int"); - break; - } + assert(tid != Type::UIntTyID && "FP-to-uint conversions must be expanded" + " into FP->long->uint for SPARC v9: SO RUN PRESELECTION PASS!"); } - else if (instrType == ToLongTy) + else if (tid==Type::SByteTyID || tid==Type::ShortTyID || tid==Type::IntTyID || + tid==Type::UByteTyID || tid==Type::UShortTyID) { - switch (opType->getPrimitiveID()) - { - case Type::FloatTyID: opCode = FSTOX; break; - case Type::DoubleTyID: opCode = FDTOX; break; - default: - assert(0 && "Non-numeric non-bool type cannot be converted to Long"); - break; - } + opCode = (opType == Type::FloatTy)? FSTOI : FDTOI; + } + else if (tid==Type::LongTyID || tid==Type::ULongTyID) + { + opCode = (opType == Type::FloatTy)? FSTOX : FDTOX; } else assert(0 && "Should not get here, Mo!"); - + return opCode; } +MachineInstr* +CreateConvertFPToIntInstr(Type::PrimitiveID destTID, + Value* srcVal, Value* destVal) +{ + MachineOpCode opCode = ChooseConvertFPToIntInstr(destTID, srcVal->getType()); + assert(opCode != INVALID_OPCODE && "Expected to need conversion!"); + + MachineInstr* M = new MachineInstr(opCode); + M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, srcVal); + M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, destVal); + return M; +} + +// CreateCodeToConvertFloatToInt: Convert FP value to signed or unsigned integer +// The FP value must be converted to the dest type in an FP register, +// and the result is then copied from FP to int register via memory. +// +// Since fdtoi converts to signed integers, any FP value V between MAXINT+1 +// and MAXUNSIGNED (i.e., 2^31 <= V <= 2^32-1) would be converted incorrectly +// *only* when converting to an unsigned int. (Unsigned byte, short or long +// don't have this problem.) +// For unsigned int, we therefore have to generate the code sequence: +// +// if (V > (float) MAXINT) { +// unsigned result = (unsigned) (V - (float) MAXINT); +// result = result + (unsigned) MAXINT; +// } +// else +// result = (unsigned int) V; +// +static void +CreateCodeToConvertFloatToInt(const TargetMachine& target, + Value* opVal, + Instruction* destI, + std::vector& mvec, + MachineCodeForInstruction& mcfi) +{ + // Create a temporary to represent the FP register into which the + // int value will placed after conversion. The type of this temporary + // depends on the type of FP register to use: single-prec for a 32-bit + // int or smaller; double-prec for a 64-bit int. + // + size_t destSize = target.DataLayout.getTypeSize(destI->getType()); + const Type* destTypeToUse = (destSize > 4)? Type::DoubleTy : Type::FloatTy; + TmpInstruction* destForCast = new TmpInstruction(destTypeToUse, opVal); + mcfi.addTemp(destForCast); + + // Create the fp-to-int conversion code + MachineInstr* M =CreateConvertFPToIntInstr(destI->getType()->getPrimitiveID(), + opVal, destForCast); + mvec.push_back(M); + + // Create the fpreg-to-intreg copy code + target.getInstrInfo(). + CreateCodeToCopyFloatToInt(target, destI->getParent()->getParent(), + destForCast, destI, mvec, mcfi); +} + static inline MachineOpCode ChooseAddInstruction(const InstructionNode* instrNode) { - MachineOpCode opCode = INVALID_OPCODE; - - const Type* resultType = instrNode->getInstruction()->getType(); - - if (resultType->isIntegral() || - resultType->isPointerType() || - resultType->isMethodType() || - resultType->isLabelType()) - { - opCode = ADD; - } - else - { - Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue(); - switch(operand->getType()->getPrimitiveID()) - { - case Type::FloatTyID: opCode = FADDS; break; - case Type::DoubleTyID: opCode = FADDD; break; - default: assert(0 && "Invalid type for ADD instruction"); break; - } - } - - return opCode; + return ChooseAddInstructionByType(instrNode->getInstruction()->getType()); } static inline MachineInstr* CreateMovFloatInstruction(const InstructionNode* instrNode, - const Type* resultType) + const Type* resultType) { MachineInstr* minstr = new MachineInstr((resultType == Type::FloatTy) - ? FMOVS : FMOVD); - minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, - instrNode->leftChild()->getValue()); - minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, - instrNode->getValue()); + ? FMOVS : FMOVD); + minstr->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, + instrNode->leftChild()->getValue()); + minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, + instrNode->getValue()); return minstr; } @@ -470,46 +381,39 @@ CreateAddConstInstruction(const InstructionNode* instrNode) MachineInstr* minstr = NULL; Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue(); - assert(constOp->isConstant()); + assert(isa(constOp)); // Cases worth optimizing are: // (1) Add with 0 for float or double: use an FMOV of appropriate type, // instead of an FADD (1 vs 3 cycles). There is no integer MOV. // - const Type* resultType = instrNode->getInstruction()->getType(); - - if (resultType == Type::FloatTy || resultType == Type::DoubleTy) { - double dval = ((ConstPoolFP*) constOp)->getValue(); - if (dval == 0.0) - minstr = CreateMovFloatInstruction(instrNode, resultType); - } + if (ConstantFP *FPC = dyn_cast(constOp)) { + double dval = FPC->getValue(); + if (dval == 0.0) + minstr = CreateMovFloatInstruction(instrNode, + instrNode->getInstruction()->getType()); + } return minstr; } static inline MachineOpCode -ChooseSubInstruction(const InstructionNode* instrNode) +ChooseSubInstructionByType(const Type* resultType) { MachineOpCode opCode = INVALID_OPCODE; - const Type* resultType = instrNode->getInstruction()->getType(); - - if (resultType->isIntegral() || - resultType->isPointerType()) + if (resultType->isInteger() || isa(resultType)) { opCode = SUB; } else - { - Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue(); - switch(operand->getType()->getPrimitiveID()) - { - case Type::FloatTyID: opCode = FSUBS; break; - case Type::DoubleTyID: opCode = FSUBD; break; - default: assert(0 && "Invalid type for SUB instruction"); break; - } - } + switch(resultType->getPrimitiveID()) + { + case Type::FloatTyID: opCode = FSUBS; break; + case Type::DoubleTyID: opCode = FSUBD; break; + default: assert(0 && "Invalid type for SUB instruction"); break; + } return opCode; } @@ -521,21 +425,18 @@ CreateSubConstInstruction(const InstructionNode* instrNode) MachineInstr* minstr = NULL; Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue(); - assert(constOp->isConstant()); + assert(isa(constOp)); // Cases worth optimizing are: // (1) Sub with 0 for float or double: use an FMOV of appropriate type, // instead of an FSUB (1 vs 3 cycles). There is no integer MOV. // - const Type* resultType = instrNode->getInstruction()->getType(); - - if (resultType == Type::FloatTy || - resultType == Type::DoubleTy) - { - double dval = ((ConstPoolFP*) constOp)->getValue(); - if (dval == 0.0) - minstr = CreateMovFloatInstruction(instrNode, resultType); - } + if (ConstantFP *FPC = dyn_cast(constOp)) { + double dval = FPC->getValue(); + if (dval == 0.0) + minstr = CreateMovFloatInstruction(instrNode, + instrNode->getInstruction()->getType()); + } return minstr; } @@ -570,188 +471,278 @@ BothFloatToDouble(const InstructionNode* instrNode) // Check if both arguments are floats cast to double return (leftArg->getValue()->getType() == Type::DoubleTy && - leftArgArg->getValue()->getType() == Type::FloatTy && - rightArgArg->getValue()->getType() == Type::FloatTy); + leftArgArg->getValue()->getType() == Type::FloatTy && + rightArgArg->getValue()->getType() == Type::FloatTy); } static inline MachineOpCode -ChooseMulInstruction(const InstructionNode* instrNode, - bool checkCasts) +ChooseMulInstructionByType(const Type* resultType) { MachineOpCode opCode = INVALID_OPCODE; - if (checkCasts && BothFloatToDouble(instrNode)) - { - return opCode = FSMULD; - } - // else fall through and use the regular multiply instructions - - const Type* resultType = instrNode->getInstruction()->getType(); - - if (resultType->isIntegral()) - { - opCode = MULX; - } + if (resultType->isInteger()) + opCode = MULX; else - { - switch(instrNode->leftChild()->getValue()->getType()->getPrimitiveID()) - { - case Type::FloatTyID: opCode = FMULS; break; - case Type::DoubleTyID: opCode = FMULD; break; - default: assert(0 && "Invalid type for MUL instruction"); break; - } - } + switch(resultType->getPrimitiveID()) + { + case Type::FloatTyID: opCode = FMULS; break; + case Type::DoubleTyID: opCode = FMULD; break; + default: assert(0 && "Invalid type for MUL instruction"); break; + } return opCode; } + static inline MachineInstr* -CreateIntNegInstruction(Value* vreg) +CreateIntNegInstruction(const TargetMachine& target, + Value* vreg) { MachineInstr* minstr = new MachineInstr(SUB); - minstr->SetMachineOperand(0, /*regNum %g0*/(unsigned int) 0); - minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, vreg); - minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, vreg); + minstr->SetMachineOperandReg(0, target.getRegInfo().getZeroRegNum()); + minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, vreg); + minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, vreg); return minstr; } -static inline MachineInstr* -CreateMulConstInstruction(const InstructionNode* instrNode, - MachineInstr*& getMinstr2) +// Create instruction sequence for any shift operation. +// SLL or SLLX on an operand smaller than the integer reg. size (64bits) +// requires a second instruction for explicit sign-extension. +// Note that we only have to worry about a sign-bit appearing in the +// most significant bit of the operand after shifting (e.g., bit 32 of +// Int or bit 16 of Short), so we do not have to worry about results +// that are as large as a normal integer register. +// +static inline void +CreateShiftInstructions(const TargetMachine& target, + Function* F, + MachineOpCode shiftOpCode, + Value* argVal1, + Value* optArgVal2, /* Use optArgVal2 if not NULL */ + unsigned int optShiftNum, /* else use optShiftNum */ + Instruction* destVal, + vector& mvec, + MachineCodeForInstruction& mcfi) { - MachineInstr* minstr = NULL; - getMinstr2 = NULL; - bool needNeg = false; + assert((optArgVal2 != NULL || optShiftNum <= 64) && + "Large shift sizes unexpected, but can be handled below: " + "You need to check whether or not it fits in immed field below"); + + // If this is a logical left shift of a type smaller than the standard + // integer reg. size, we have to extend the sign-bit into upper bits + // of dest, so we need to put the result of the SLL into a temporary. + // + Value* shiftDest = destVal; + unsigned opSize = target.DataLayout.getTypeSize(argVal1->getType()); + if ((shiftOpCode == SLL || shiftOpCode == SLLX) + && opSize < target.DataLayout.getIntegerRegize()) + { // put SLL result into a temporary + shiftDest = new TmpInstruction(argVal1, optArgVal2, "sllTmp"); + mcfi.addTemp(shiftDest); + } + + MachineInstr* M = (optArgVal2 != NULL) + ? Create3OperandInstr(shiftOpCode, argVal1, optArgVal2, shiftDest) + : Create3OperandInstr_UImmed(shiftOpCode, argVal1, optShiftNum, shiftDest); + mvec.push_back(M); + + if (shiftDest != destVal) + { // extend the sign-bit of the result into all upper bits of dest + assert(8*opSize <= 32 && "Unexpected type size > 4 and < IntRegSize?"); + target.getInstrInfo(). + CreateSignExtensionInstructions(target, F, shiftDest, destVal, + 8*opSize, mvec, mcfi); + } +} - Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue(); - assert(constOp->isConstant()); + +// Does not create any instructions if we cannot exploit constant to +// create a cheaper instruction. +// This returns the approximate cost of the instructions generated, +// which is used to pick the cheapest when both operands are constant. +static inline unsigned int +CreateMulConstInstruction(const TargetMachine &target, Function* F, + Value* lval, Value* rval, Instruction* destVal, + vector& mvec, + MachineCodeForInstruction& mcfi) +{ + /* Use max. multiply cost, viz., cost of MULX */ + unsigned int cost = target.getInstrInfo().minLatency(MULX); + unsigned int firstNewInstr = mvec.size(); + + Value* constOp = rval; + if (! isa(constOp)) + return cost; // Cases worth optimizing are: // (1) Multiply by 0 or 1 for any type: replace with copy (ADD or FMOV) // (2) Multiply by 2^x for integer types: replace with Shift // - const Type* resultType = instrNode->getInstruction()->getType(); + const Type* resultType = destVal->getType(); - if (resultType->isIntegral() || resultType->isPointerType()) + if (resultType->isInteger() || isa(resultType)) { - unsigned pow; bool isValidConst; int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst); if (isValidConst) - { - bool needNeg = false; - if (C < 0) - { - needNeg = true; - C = -C; - } - - if (C == 0 || C == 1) - { - minstr = new MachineInstr(ADD); - - if (C == 0) - minstr->SetMachineOperand(0, /*regNum %g0*/ (unsigned int) 0); - else - minstr->SetMachineOperand(0,MachineOperand::MO_VirtualRegister, - instrNode->leftChild()->getValue()); - minstr->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0); - } - else if (IsPowerOf2(C, pow)) - { - minstr = new MachineInstr((resultType == Type::LongTy) - ? SLLX : SLL); - minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, - instrNode->leftChild()->getValue()); - minstr->SetMachineOperand(1, MachineOperand::MO_UnextendedImmed, - pow); - } - - if (minstr && needNeg) - { // insert after the instr to flip the sign - getMinstr2 = CreateIntNegInstruction(instrNode->getValue()); - } - } + { + unsigned pow; + bool needNeg = false; + if (C < 0) + { + needNeg = true; + C = -C; + } + + if (C == 0 || C == 1) + { + cost = target.getInstrInfo().minLatency(ADD); + MachineInstr* M = (C == 0) + ? Create3OperandInstr_Reg(ADD, + target.getRegInfo().getZeroRegNum(), + target.getRegInfo().getZeroRegNum(), + destVal) + : Create3OperandInstr_Reg(ADD, lval, + target.getRegInfo().getZeroRegNum(), + destVal); + mvec.push_back(M); + } + else if (isPowerOf2(C, pow)) + { + unsigned int opSize = target.DataLayout.getTypeSize(resultType); + MachineOpCode opCode = (opSize <= 32)? SLL : SLLX; + CreateShiftInstructions(target, F, opCode, lval, NULL, pow, + destVal, mvec, mcfi); + } + + if (mvec.size() > 0 && needNeg) + { // insert after the instr to flip the sign + MachineInstr* M = CreateIntNegInstruction(target, destVal); + mvec.push_back(M); + } + } } else { - if (resultType == Type::FloatTy || - resultType == Type::DoubleTy) - { - bool isValidConst; - double dval = ((ConstPoolFP*) constOp)->getValue(); - - if (isValidConst) - { - if (dval == 0) - { - minstr = new MachineInstr((resultType == Type::FloatTy) - ? FITOS : FITOD); - minstr->SetMachineOperand(0, /*regNum %g0*/(unsigned int) 0); - } - else if (fabs(dval) == 1) - { - bool needNeg = (dval < 0); - - MachineOpCode opCode = needNeg - ? (resultType == Type::FloatTy? FNEGS : FNEGD) - : (resultType == Type::FloatTy? FMOVS : FMOVD); - - minstr = new MachineInstr(opCode); - minstr->SetMachineOperand(0, - MachineOperand::MO_VirtualRegister, - instrNode->leftChild()->getValue()); - } - } - } + if (ConstantFP *FPC = dyn_cast(constOp)) + { + double dval = FPC->getValue(); + if (fabs(dval) == 1) + { + MachineOpCode opCode = (dval < 0) + ? (resultType == Type::FloatTy? FNEGS : FNEGD) + : (resultType == Type::FloatTy? FMOVS : FMOVD); + MachineInstr* M = Create2OperandInstr(opCode, lval, destVal); + mvec.push_back(M); + } + } } - if (minstr != NULL) - minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, - instrNode->getValue()); + if (firstNewInstr < mvec.size()) + { + cost = 0; + for (unsigned int i=firstNewInstr; i < mvec.size(); ++i) + cost += target.getInstrInfo().minLatency(mvec[i]->getOpCode()); + } - return minstr; + return cost; +} + + +// Does not create any instructions if we cannot exploit constant to +// create a cheaper instruction. +// +static inline void +CreateCheapestMulConstInstruction(const TargetMachine &target, + Function* F, + Value* lval, Value* rval, + Instruction* destVal, + vector& mvec, + MachineCodeForInstruction& mcfi) +{ + Value* constOp; + if (isa(lval) && isa(rval)) + { // both operands are constant: evaluate and "set" in dest + Constant* P = ConstantFoldBinaryInstruction(Instruction::Mul, + cast(lval), cast(rval)); + target.getInstrInfo().CreateCodeToLoadConst(target,F,P,destVal,mvec,mcfi); + } + else if (isa(rval)) // rval is constant, but not lval + CreateMulConstInstruction(target, F, lval, rval, destVal, mvec, mcfi); + else if (isa(lval)) // lval is constant, but not rval + CreateMulConstInstruction(target, F, lval, rval, destVal, mvec, mcfi); + + // else neither is constant + return; +} + +// Return NULL if we cannot exploit constant to create a cheaper instruction +static inline void +CreateMulInstruction(const TargetMachine &target, Function* F, + Value* lval, Value* rval, Instruction* destVal, + vector& mvec, + MachineCodeForInstruction& mcfi, + MachineOpCode forceMulOp = INVALID_MACHINE_OPCODE) +{ + unsigned int L = mvec.size(); + CreateCheapestMulConstInstruction(target,F, lval, rval, destVal, mvec, mcfi); + if (mvec.size() == L) + { // no instructions were added so create MUL reg, reg, reg. + // Use FSMULD if both operands are actually floats cast to doubles. + // Otherwise, use the default opcode for the appropriate type. + MachineOpCode mulOp = ((forceMulOp != INVALID_MACHINE_OPCODE) + ? forceMulOp + : ChooseMulInstructionByType(destVal->getType())); + MachineInstr* M = new MachineInstr(mulOp); + M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, lval); + M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, rval); + M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, destVal); + mvec.push_back(M); + } } +// Generate a divide instruction for Div or Rem. +// For Rem, this assumes that the operand type will be signed if the result +// type is signed. This is correct because they must have the same sign. +// static inline MachineOpCode -ChooseDivInstruction(const InstructionNode* instrNode) +ChooseDivInstruction(TargetMachine &target, + const InstructionNode* instrNode) { MachineOpCode opCode = INVALID_OPCODE; const Type* resultType = instrNode->getInstruction()->getType(); - if (resultType->isIntegral()) - { - opCode = resultType->isSigned()? SDIVX : UDIVX; - } + if (resultType->isInteger()) + opCode = resultType->isSigned()? SDIVX : UDIVX; else - { - Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue(); - switch(operand->getType()->getPrimitiveID()) - { - case Type::FloatTyID: opCode = FDIVS; break; - case Type::DoubleTyID: opCode = FDIVD; break; - default: assert(0 && "Invalid type for DIV instruction"); break; - } - } + switch(resultType->getPrimitiveID()) + { + case Type::FloatTyID: opCode = FDIVS; break; + case Type::DoubleTyID: opCode = FDIVD; break; + default: assert(0 && "Invalid type for DIV instruction"); break; + } return opCode; } -static inline MachineInstr* -CreateDivConstInstruction(const InstructionNode* instrNode, - MachineInstr*& getMinstr2) +// Return NULL if we cannot exploit constant to create a cheaper instruction +static inline void +CreateDivConstInstruction(TargetMachine &target, + const InstructionNode* instrNode, + vector& mvec) { - MachineInstr* minstr = NULL; - getMinstr2 = NULL; + MachineInstr* minstr1 = NULL; + MachineInstr* minstr2 = NULL; Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue(); - assert(constOp->isConstant()); + if (! isa(constOp)) + return; // Cases worth optimizing are: // (1) Divide by 1 for any type: replace with copy (ADD or FMOV) @@ -759,115 +750,173 @@ CreateDivConstInstruction(const InstructionNode* instrNode, // const Type* resultType = instrNode->getInstruction()->getType(); - if (resultType->isIntegral()) + if (resultType->isInteger()) { unsigned pow; bool isValidConst; int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst); if (isValidConst) - { - bool needNeg = false; - if (C < 0) - { - needNeg = true; - C = -C; - } - - if (C == 1) - { - minstr = new MachineInstr(ADD); - minstr->SetMachineOperand(0,MachineOperand::MO_VirtualRegister, - instrNode->leftChild()->getValue()); - minstr->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0); - } - else if (IsPowerOf2(C, pow)) - { - MachineOpCode opCode= ((resultType->isSigned()) - ? (resultType==Type::LongTy)? SRAX : SRA - : (resultType==Type::LongTy)? SRLX : SRL); - minstr = new MachineInstr(opCode); - minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, - instrNode->leftChild()->getValue()); - minstr->SetMachineOperand(1, MachineOperand::MO_UnextendedImmed, - pow); - } - - if (minstr && needNeg) - { // insert after the instr to flip the sign - getMinstr2 = CreateIntNegInstruction(instrNode->getValue()); - } - } + { + bool needNeg = false; + if (C < 0) + { + needNeg = true; + C = -C; + } + + if (C == 1) + { + minstr1 = new MachineInstr(ADD); + minstr1->SetMachineOperandVal(0, + MachineOperand::MO_VirtualRegister, + instrNode->leftChild()->getValue()); + minstr1->SetMachineOperandReg(1, + target.getRegInfo().getZeroRegNum()); + } + else if (isPowerOf2(C, pow)) + { + MachineOpCode opCode= ((resultType->isSigned()) + ? (resultType==Type::LongTy)? SRAX : SRA + : (resultType==Type::LongTy)? SRLX : SRL); + minstr1 = new MachineInstr(opCode); + minstr1->SetMachineOperandVal(0, + MachineOperand::MO_VirtualRegister, + instrNode->leftChild()->getValue()); + minstr1->SetMachineOperandConst(1, + MachineOperand::MO_UnextendedImmed, + pow); + } + + if (minstr1 && needNeg) + { // insert after the instr to flip the sign + minstr2 = CreateIntNegInstruction(target, + instrNode->getValue()); + } + } } else { - if (resultType == Type::FloatTy || - resultType == Type::DoubleTy) - { - bool isValidConst; - double dval = ((ConstPoolFP*) constOp)->getValue(); - - if (isValidConst && fabs(dval) == 1) - { - bool needNeg = (dval < 0); - - MachineOpCode opCode = needNeg - ? (resultType == Type::FloatTy? FNEGS : FNEGD) - : (resultType == Type::FloatTy? FMOVS : FMOVD); - - minstr = new MachineInstr(opCode); - minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, - instrNode->leftChild()->getValue()); - } - } + if (ConstantFP *FPC = dyn_cast(constOp)) + { + double dval = FPC->getValue(); + if (fabs(dval) == 1) + { + bool needNeg = (dval < 0); + + MachineOpCode opCode = needNeg + ? (resultType == Type::FloatTy? FNEGS : FNEGD) + : (resultType == Type::FloatTy? FMOVS : FMOVD); + + minstr1 = new MachineInstr(opCode); + minstr1->SetMachineOperandVal(0, + MachineOperand::MO_VirtualRegister, + instrNode->leftChild()->getValue()); + } + } } - if (minstr != NULL) - minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, - instrNode->getValue()); + if (minstr1 != NULL) + minstr1->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, + instrNode->getValue()); - return minstr; + if (minstr1) + mvec.push_back(minstr1); + if (minstr2) + mvec.push_back(minstr2); } -static inline MachineOpCode ChooseLoadInstruction(const Type *DestTy) { - switch (DestTy->getPrimitiveID()) { - case Type::BoolTyID: - case Type::UByteTyID: return LDUB; - case Type::SByteTyID: return LDSB; - case Type::UShortTyID: return LDUH; - case Type::ShortTyID: return LDSH; - case Type::UIntTyID: return LDUW; - case Type::IntTyID: return LDSW; - case Type::PointerTyID: - case Type::ULongTyID: - case Type::LongTyID: return LDX; - case Type::FloatTyID: return LD; - case Type::DoubleTyID: return LDD; - default: assert(0 && "Invalid type for Load instruction"); - } - - return 0; -} +static void +CreateCodeForVariableSizeAlloca(const TargetMachine& target, + Instruction* result, + unsigned int tsize, + Value* numElementsVal, + vector& getMvec) +{ + MachineInstr* M; + MachineCodeForInstruction& mcfi = MachineCodeForInstruction::get(result); + + // Create a Value to hold the (constant) element size + Value* tsizeVal = ConstantSInt::get(Type::IntTy, tsize); + + // Get the constant offset from SP for dynamically allocated storage + // and create a temporary Value to hold it. + assert(result && result->getParent() && "Result value is not part of a fn?"); + Function *F = result->getParent()->getParent(); + MachineCodeForMethod& mcInfo = MachineCodeForMethod::get(F); + bool growUp; + ConstantSInt* dynamicAreaOffset = + ConstantSInt::get(Type::IntTy, + target.getFrameInfo().getDynamicAreaOffset(mcInfo,growUp)); + assert(! growUp && "Has SPARC v9 stack frame convention changed?"); + + // Create a temporary value to hold the result of MUL + TmpInstruction* tmpProd = new TmpInstruction(numElementsVal, tsizeVal); + mcfi.addTemp(tmpProd); + + // Instruction 1: mul numElements, typeSize -> tmpProd + CreateMulInstruction(target, F, numElementsVal, tsizeVal, tmpProd, getMvec, + mcfi, INVALID_MACHINE_OPCODE); + + // Instruction 2: sub %sp, tmpProd -> %sp + M = new MachineInstr(SUB); + M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer()); + M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, tmpProd); + M->SetMachineOperandReg(2, target.getRegInfo().getStackPointer()); + getMvec.push_back(M); + + // Instruction 3: add %sp, frameSizeBelowDynamicArea -> result + M = new MachineInstr(ADD); + M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer()); + M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, dynamicAreaOffset); + M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, result); + getMvec.push_back(M); +} -static inline MachineOpCode ChooseStoreInstruction(const Type *DestTy) { - switch (DestTy->getPrimitiveID()) { - case Type::BoolTyID: - case Type::UByteTyID: - case Type::SByteTyID: return STB; - case Type::UShortTyID: - case Type::ShortTyID: return STH; - case Type::UIntTyID: - case Type::IntTyID: return STW; - case Type::PointerTyID: - case Type::ULongTyID: - case Type::LongTyID: return STX; - case Type::FloatTyID: return ST; - case Type::DoubleTyID: return STD; - default: assert(0 && "Invalid type for Store instruction"); - } +static void +CreateCodeForFixedSizeAlloca(const TargetMachine& target, + Instruction* result, + unsigned int tsize, + unsigned int numElements, + vector& getMvec) +{ + assert(tsize > 0 && "Illegal (zero) type size for alloca"); + assert(result && result->getParent() && + "Result value is not part of a function?"); + Function *F = result->getParent()->getParent(); + MachineCodeForMethod &mcInfo = MachineCodeForMethod::get(F); + + // Check if the offset would small enough to use as an immediate in + // load/stores (check LDX because all load/stores have the same-size immediate + // field). If not, put the variable in the dynamically sized area of the + // frame. + unsigned int paddedSizeIgnored; + int offsetFromFP = mcInfo.computeOffsetforLocalVar(target, result, + paddedSizeIgnored, + tsize * numElements); + if (! target.getInstrInfo().constantFitsInImmedField(LDX, offsetFromFP)) + { + CreateCodeForVariableSizeAlloca(target, result, tsize, + ConstantSInt::get(Type::IntTy,numElements), + getMvec); + return; + } + + // else offset fits in immediate field so go ahead and allocate it. + offsetFromFP = mcInfo.allocateLocalVar(target, result, tsize * numElements); + + // Create a temporary Value to hold the constant offset. + // This is needed because it may not fit in the immediate field. + ConstantSInt* offsetVal = ConstantSInt::get(Type::IntTy, offsetFromFP); - return 0; + // Instruction 1: add %fp, offsetFromFP -> result + MachineInstr* M = new MachineInstr(ADD); + M->SetMachineOperandReg(0, target.getRegInfo().getFramePointer()); + M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, offsetVal); + M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, result); + + getMvec.push_back(M); } @@ -888,375 +937,141 @@ static inline MachineOpCode ChooseStoreInstruction(const Type *DestTy) { //------------------------------------------------------------------------ static void -SetOperandsForMemInstr(MachineInstr* minstr, - const InstructionNode* vmInstrNode, - const TargetMachine& target) +SetOperandsForMemInstr(vector& mvec, + InstructionNode* vmInstrNode, + const TargetMachine& target) { - MemAccessInst* memInst = (MemAccessInst*) vmInstrNode->getInstruction(); - - // Variables to hold the index vector, ptr value, and offset value. - // The major work here is to extract these for all 3 instruction types - // and then call the common function SetMemOperands_Internal(). - // - const vector* idxVec = & memInst->getIndexVec(); - vector* newIdxVec = NULL; - Value* ptrVal; - Value* arrayOffsetVal = NULL; - - // Test if a GetElemPtr instruction is being folded into this mem instrn. - // If so, it will be in the left child for Load and GetElemPtr, - // and in the right child for Store instructions. - // - InstrTreeNode* ptrChild = (vmInstrNode->getOpLabel() == Instruction::Store - ? vmInstrNode->rightChild() - : vmInstrNode->leftChild()); - - if (ptrChild->getOpLabel() == Instruction::GetElementPtr || - ptrChild->getOpLabel() == GetElemPtrIdx) - { - // There is a GetElemPtr instruction and there may be a chain of - // more than one. Use the pointer value of the last one in the chain. - // Fold the index vectors from the entire chain and from the mem - // instruction into one single index vector. - // Finally, we never fold for an array instruction so make that NULL. - - newIdxVec = new vector; - ptrVal = FoldGetElemChain((InstructionNode*) ptrChild, *newIdxVec); - - newIdxVec->insert(newIdxVec->end(), idxVec->begin(), idxVec->end()); - idxVec = newIdxVec; - - assert(! ((PointerType*)ptrVal->getType())->getValueType()->isArrayType() - && "GetElemPtr cannot be folded into array refs in selection"); - } - else - { - // There is no GetElemPtr instruction. - // Use the pointer value and the index vector from the Mem instruction. - // If it is an array reference, get the array offset value. - // - ptrVal = memInst->getPtrOperand(); - - const Type* opType = - ((const PointerType*) ptrVal->getType())->getValueType(); - if (opType->isArrayType()) - { - assert((memInst->getNumOperands() - == (unsigned) 1 + memInst->getFirstOffsetIdx()) - && "Array refs must be lowered before Instruction Selection"); - - arrayOffsetVal = memInst->getOperand(memInst->getFirstOffsetIdx()); - } - } - - SetMemOperands_Internal(minstr, vmInstrNode, ptrVal, arrayOffsetVal, - *idxVec, target); - - if (newIdxVec != NULL) - delete newIdxVec; -} + Instruction* memInst = vmInstrNode->getInstruction(); + vector::iterator mvecI = mvec.end() - 1; + // Index vector, ptr value, and flag if all indices are const. + vector idxVec; + bool allConstantIndices; + Value* ptrVal = GetMemInstArgs(vmInstrNode, idxVec, allConstantIndices); -static void -SetMemOperands_Internal(MachineInstr* minstr, - const InstructionNode* vmInstrNode, - Value* ptrVal, - Value* arrayOffsetVal, - const vector& idxVec, - const TargetMachine& target) -{ - MemAccessInst* memInst = (MemAccessInst*) vmInstrNode->getInstruction(); - - // Initialize so we default to storing the offset in a register. - int64_t smallConstOffset; + // Now create the appropriate operands for the machine instruction. + // First, initialize so we default to storing the offset in a register. + int64_t smallConstOffset = 0; Value* valueForRegOffset = NULL; - MachineOperand::MachineOperandType offsetOpType =MachineOperand::MO_VirtualRegister; + MachineOperand::MachineOperandType offsetOpType = + MachineOperand::MO_VirtualRegister; - // Check if there is an index vector and if so, if it translates to - // a small enough constant to fit in the immediate-offset field. + // Check if there is an index vector and if so, compute the + // right offset for structures and for arrays // - if (idxVec.size() > 0) + if (!idxVec.empty()) { - bool isConstantOffset = false; - unsigned offset; - - const PointerType* ptrType = (PointerType*) ptrVal->getType(); + const PointerType* ptrType = cast(ptrVal->getType()); - if (ptrType->getValueType()->isStructType()) - { - // the offset is always constant for structs - isConstantOffset = true; - - // Compute the offset value using the index vector - offset = target.DataLayout.getIndexedOffset(ptrType, idxVec); - } + // If all indices are constant, compute the combined offset directly. + if (allConstantIndices) + { + // Compute the offset value using the index vector. Create a + // virtual reg. for it since it may not fit in the immed field. + uint64_t offset = target.DataLayout.getIndexedOffset(ptrType,idxVec); + valueForRegOffset = ConstantSInt::get(Type::LongTy, offset); + } else - { - // It must be an array ref. Check if the offset is a constant, - // and that the indexing has been lowered to a single offset. - // - assert(ptrType->getValueType()->isArrayType()); - assert(arrayOffsetVal != NULL - && "Expect to be given Value* for array offsets"); - - if (ConstPoolVal *CPV = arrayOffsetVal->castConstant()) - { - isConstantOffset = true; // always constant for structs - assert(arrayOffsetVal->getType()->isIntegral()); - offset = (CPV->getType()->isSigned() - ? ((ConstPoolSInt*)CPV)->getValue() - : (int64_t) ((ConstPoolUInt*)CPV)->getValue()); - } - else - { - valueForRegOffset = arrayOffsetVal; - } - } - - if (isConstantOffset) - { - // create a virtual register for the constant - valueForRegOffset = ConstPoolSInt::get(Type::IntTy, offset); - } + { + // There is at least one non-constant offset. Therefore, this must + // be an array ref, and must have been lowered to a single non-zero + // offset. (An extra leading zero offset, if any, can be ignored.) + // Generate code sequence to compute address from index. + // + bool firstIdxIsZero = + (idxVec[0] == Constant::getNullValue(idxVec[0]->getType())); + assert(idxVec.size() == 1U + firstIdxIsZero + && "Array refs must be lowered before Instruction Selection"); + + Value* idxVal = idxVec[firstIdxIsZero]; + + vector mulVec; + Instruction* addr = new TmpInstruction(Type::ULongTy, memInst); + MachineCodeForInstruction::get(memInst).addTemp(addr); + + // Get the array type indexed by idxVal, and compute its element size. + // The call to getTypeSize() will fail if size is not constant. + const Type* vecType = (firstIdxIsZero + ? GetElementPtrInst::getIndexedType(ptrType, + std::vector(1U, idxVec[0]), + /*AllowCompositeLeaf*/ true) + : ptrType); + const Type* eltType = cast(vecType)->getElementType(); + ConstantUInt* eltSizeVal = ConstantUInt::get(Type::ULongTy, + target.DataLayout.getTypeSize(eltType)); + + // CreateMulInstruction() folds constants intelligently enough. + CreateMulInstruction(target, memInst->getParent()->getParent(), + idxVal, /* lval, not likely to be const*/ + eltSizeVal, /* rval, likely to be constant */ + addr, /* result */ + mulVec, MachineCodeForInstruction::get(memInst), + INVALID_MACHINE_OPCODE); + + // Insert mulVec[] before *mvecI in mvec[] and update mvecI + // to point to the same instruction it pointed to before. + assert(mulVec.size() > 0 && "No multiply code created?"); + vector::iterator oldMvecI = mvecI; + for (unsigned i=0, N=mulVec.size(); i < N; ++i) + mvecI = mvec.insert(mvecI, mulVec[i]) + 1; // pts to mem instr + + valueForRegOffset = addr; + } } else { offsetOpType = MachineOperand::MO_SignExtendedImmed; smallConstOffset = 0; } - - // Operand 0 is value for STORE, ptr for LOAD or GET_ELEMENT_PTR - // It is the left child in the instruction tree in all cases. - Value* leftVal = vmInstrNode->leftChild()->getValue(); - minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, leftVal); - - // Operand 1 is ptr for STORE, offset for LOAD or GET_ELEMENT_PTR - // Operand 3 is offset for STORE, result reg for LOAD or GET_ELEMENT_PTR - // - unsigned offsetOpNum = (memInst->getOpcode() == Instruction::Store)? 2 : 1; - if (offsetOpType == MachineOperand::MO_VirtualRegister) - { - assert(valueForRegOffset != NULL); - minstr->SetMachineOperand(offsetOpNum, offsetOpType, valueForRegOffset); - } - else - minstr->SetMachineOperand(offsetOpNum, offsetOpType, smallConstOffset); - - if (memInst->getOpcode() == Instruction::Store) - minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, ptrVal); - else - minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, - vmInstrNode->getValue()); -} - - -// Special handling for constant operands: -// -- if the constant is 0, use the hardwired 0 register, if any; -// -- if the constant is of float or double type but has an integer value, -// use int-to-float conversion instruction instead of generating a load; -// -- if the constant fits in the IMMEDIATE field, use that field; -// -- else insert instructions to put the constant into a register, either -// directly or by loading explicitly from the constant pool. -// -static unsigned -FixConstantOperands(const InstructionNode* vmInstrNode, - MachineInstr** mvec, - unsigned numInstr, - TargetMachine& target) -{ - static MachineInstr* loadConstVec[MAX_INSTR_PER_VMINSTR]; - unsigned numNew = 0; - Instruction* vmInstr = vmInstrNode->getInstruction(); - - for (unsigned i=0; i < numInstr; i++) - { - MachineInstr* minstr = mvec[i]; - const MachineInstrDescriptor& instrDesc = - target.getInstrInfo().getDescriptor(minstr->getOpCode()); - - for (unsigned op=0; op < minstr->getNumOperands(); op++) - { - const MachineOperand& mop = minstr->getOperand(op); - - // skip the result position (for efficiency below) and any other - // positions already marked as not a virtual register - if (instrDesc.resultPos == (int) op || - mop.getOperandType() != MachineOperand::MO_VirtualRegister || - mop.getVRegValue() == NULL) - { - break; - } - - Value* opValue = mop.getVRegValue(); - - if (opValue->isConstant()) - { - unsigned int machineRegNum; - int64_t immedValue; - MachineOperand::MachineOperandType opType = - ChooseRegOrImmed(opValue, minstr->getOpCode(), target, - /*canUseImmed*/ (op == 1), - machineRegNum, immedValue); - - if (opType == MachineOperand::MO_MachineRegister) - minstr->SetMachineOperand(op, machineRegNum); - else if (opType == MachineOperand::MO_VirtualRegister) - { - // value is constant and must be loaded into a register - TmpInstruction* tmpReg; - MachineInstr* minstr2; - loadConstVec[numNew++] = MakeLoadConstInstr(vmInstr, opValue, - tmpReg, minstr2); - minstr->SetMachineOperand(op, opType, tmpReg); - if (minstr2 != NULL) - loadConstVec[numNew++] = minstr2; - } - else - minstr->SetMachineOperand(op, opType, immedValue); - } - } - } - - if (numNew > 0) - { - // Insert the new instructions *before* the old ones by moving - // the old ones over `numNew' positions (last-to-first, of course!). - // We do check *after* returning that we did not exceed the vector mvec. - for (int i=numInstr-1; i >= 0; i--) - mvec[i+numNew] = mvec[i]; - - for (unsigned i=0; i < numNew; i++) - mvec[i] = loadConstVec[i]; - } - - return (numInstr + numNew); -} - - -static inline MachineInstr* -MakeIntSetInstruction(int64_t C, bool isSigned, Value* dest) -{ - MachineInstr* minstr; - if (isSigned) + // For STORE: + // Operand 0 is value, operand 1 is ptr, operand 2 is offset + // For LOAD or GET_ELEMENT_PTR, + // Operand 0 is ptr, operand 1 is offset, operand 2 is result. + // + unsigned offsetOpNum, ptrOpNum; + if (memInst->getOpcode() == Instruction::Store) { - minstr = new MachineInstr(SETSW); - minstr->SetMachineOperand(0, MachineOperand::MO_SignExtendedImmed, C); + (*mvecI)->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, + vmInstrNode->leftChild()->getValue()); + ptrOpNum = 1; + offsetOpNum = 2; } else { - minstr = new MachineInstr(SETUW); - minstr->SetMachineOperand(0, MachineOperand::MO_UnextendedImmed, C); + ptrOpNum = 0; + offsetOpNum = 1; + (*mvecI)->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, + memInst); } - minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, dest); - - return minstr; -} - - -static MachineInstr* -MakeLoadConstInstr(Instruction* vmInstr, - Value* val, - TmpInstruction*& tmpReg, - MachineInstr*& getMinstr2) -{ - assert(val->isConstant()); - - MachineInstr* minstr; - - getMinstr2 = NULL; - - // Create a TmpInstruction to mark the hidden register used for the constant - tmpReg = new TmpInstruction(Instruction::UserOp1, val, NULL); - vmInstr->getMachineInstrVec().addTempValue(tmpReg); + (*mvecI)->SetMachineOperandVal(ptrOpNum, MachineOperand::MO_VirtualRegister, + ptrVal); - // Use a "set" instruction for known constants that can go in an integer reg. - // Use a "set" instruction followed by a int-to-float conversion for known - // constants that must go in a floating point reg but have an integer value. - // Use a "load" instruction for all other constants, in particular, - // floating point constants. - // - const Type* valType = val->getType(); - - if (valType->isIntegral() || - valType->isPointerType() || - valType == Type::BoolTy) + if (offsetOpType == MachineOperand::MO_VirtualRegister) { - bool isValidConstant; - int64_t C = GetConstantValueAsSignedInt(val, isValidConstant); - assert(isValidConstant && "Unrecognized constant"); - - minstr = MakeIntSetInstruction(C, valType->isSigned(), tmpReg); + assert(valueForRegOffset != NULL); + (*mvecI)->SetMachineOperandVal(offsetOpNum, offsetOpType, + valueForRegOffset); } else - { - assert(valType == Type::FloatTy || valType == Type::DoubleTy); - double dval = ((ConstPoolFP*) val)->getValue(); - if (dval == (int64_t) dval) - { - // The constant actually has an integer value, so use a - // [set; int-to-float] sequence instead of a load instruction. - // - TmpInstruction* tmpReg2 = NULL; - if (dval != 0.0) - { // First, create an integer constant of the same value as dval - ConstPoolSInt* ival = ConstPoolSInt::get(Type::IntTy, - (int64_t) dval); - // Create another TmpInstruction for the hidden integer register - TmpInstruction* tmpReg2 = - new TmpInstruction(Instruction::UserOp1, ival, NULL); - vmInstr->getMachineInstrVec().addTempValue(tmpReg2); - - // Create the `SET' instruction - minstr = MakeIntSetInstruction((int64_t)dval, true, tmpReg2); - } - - // In which variable do we put the second instruction? - MachineInstr*& instr2 = (minstr)? getMinstr2 : minstr; - - // Create the int-to-float instruction - instr2 = new MachineInstr(valType == Type::FloatTy? FITOS : FITOD); - - if (dval == 0.0) - instr2->SetMachineOperand(0, /*regNum %g0*/ (unsigned int) 0); - else - instr2->SetMachineOperand(0,MachineOperand::MO_VirtualRegister, - tmpReg2); - - instr2->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, - tmpReg); - } - else - { - // Make a Load instruction, and make `val' both the ptr value *and* - // the result value, and set the offset field to 0. Final code - // generation will have to generate the base+offset for the constant. - // - int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0 - minstr = new MachineInstr(ChooseLoadInstruction(val->getType())); - minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,val); - minstr->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed, - zeroOffset); - minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, - tmpReg); - } - } - - tmpReg->addMachineInstruction(minstr); - - assert(minstr); - return minstr; + (*mvecI)->SetMachineOperandConst(offsetOpNum, offsetOpType, + smallConstOffset); } + // // Substitute operand `operandNum' of the instruction in node `treeNode' -// in place the use(s) of that instruction in node `parent'. +// in place of the use(s) of that instruction in node `parent'. +// Check both explicit and implicit operands! +// Also make sure to skip over a parent who: +// (1) is a list node in the Burg tree, or +// (2) itself had its results forwarded to its parent // static void ForwardOperand(InstructionNode* treeNode, - InstrTreeNode* parent, - int operandNum) + InstrTreeNode* parent, + int operandNum) { assert(treeNode && parent && "Invalid invocation of ForwardOperand"); @@ -1272,47 +1087,94 @@ ForwardOperand(InstructionNode* treeNode, InstructionNode* parentInstrNode = (InstructionNode*) parent; Instruction* userInstr = parentInstrNode->getInstruction(); - MachineCodeForVMInstr& mvec = userInstr->getMachineInstrVec(); - for (unsigned i=0, N=mvec.size(); i < N; i++) + MachineCodeForInstruction &mvec = MachineCodeForInstruction::get(userInstr); + + // The parent's mvec would be empty if it was itself forwarded. + // Recursively call ForwardOperand in that case... + // + if (mvec.size() == 0) { - MachineInstr* minstr = mvec[i]; - for (unsigned i=0, numOps=minstr->getNumOperands(); i < numOps; i++) - { - const MachineOperand& mop = minstr->getOperand(i); - if (mop.getOperandType() == MachineOperand::MO_VirtualRegister && - mop.getVRegValue() == unusedOp) - { - minstr->SetMachineOperand(i, MachineOperand::MO_VirtualRegister, - fwdOp); - } - } + assert(parent->parent() != NULL && + "Parent could not have been forwarded, yet has no instructions?"); + ForwardOperand(treeNode, parent->parent(), operandNum); + } + else + { + for (unsigned i=0, N=mvec.size(); i < N; i++) + { + MachineInstr* minstr = mvec[i]; + for (unsigned i=0, numOps=minstr->getNumOperands(); i < numOps; ++i) + { + const MachineOperand& mop = minstr->getOperand(i); + if (mop.getOperandType() == MachineOperand::MO_VirtualRegister && + mop.getVRegValue() == unusedOp) + minstr->SetMachineOperandVal(i, + MachineOperand::MO_VirtualRegister, fwdOp); + } + + for (unsigned i=0,numOps=minstr->getNumImplicitRefs(); igetImplicitRef(i) == unusedOp) + minstr->setImplicitRef(i, fwdOp, + minstr->implicitRefIsDefined(i), + minstr->implicitRefIsDefinedAndUsed(i)); + } } } -// This function is currently unused and incomplete but will be -// used if we have a linear layout of basic blocks in LLVM code. -// It decides which branch should fall-through, and whether an -// extra unconditional branch is needed (when neither falls through). -// -void -ChooseBranchPattern(Instruction* vmInstr, BranchPattern& brPattern) +inline bool +AllUsesAreBranches(const Instruction* setccI) { - BranchInst* brInstr = (BranchInst*) vmInstr; - - brPattern.flipCondition = false; - brPattern.targetBB = brInstr->getSuccessor(0); - brPattern.extraBranch = NULL; - - assert(brInstr->getNumSuccessors() > 1 && - "Unnecessary analysis for unconditional branch"); - - assert(0 && "Fold branches in peephole optimization"); + for (Value::use_const_iterator UI=setccI->use_begin(), UE=setccI->use_end(); + UI != UE; ++UI) + if (! isa(*UI) // ignore tmp instructions here + && cast(*UI)->getOpcode() != Instruction::Br) + return false; + return true; } - //******************* Externally Visible Functions *************************/ +//------------------------------------------------------------------------ +// External Function: ThisIsAChainRule +// +// Purpose: +// Check if a given BURG rule is a chain rule. +//------------------------------------------------------------------------ + +extern bool +ThisIsAChainRule(int eruleno) +{ + switch(eruleno) + { + case 111: // stmt: reg + case 123: + case 124: + case 125: + case 126: + case 127: + case 128: + case 129: + case 130: + case 131: + case 132: + case 133: + case 155: + case 221: + case 222: + case 241: + case 242: + case 243: + case 244: + case 245: + case 321: + return true; break; + + default: + return false; break; + } +} + //------------------------------------------------------------------------ // External Function: GetInstructionsByRule @@ -1322,720 +1184,969 @@ ChooseBranchPattern(Instruction* vmInstr, BranchPattern& brPattern) // patterns chosen by the BURG-generated parser. //------------------------------------------------------------------------ -unsigned +void GetInstructionsByRule(InstructionNode* subtreeRoot, - int ruleForNode, - short* nts, - TargetMachine &target, - MachineInstr** mvec) + int ruleForNode, + short* nts, + TargetMachine &target, + vector& mvec) { - int numInstr = 1; // initialize for common case bool checkCast = false; // initialize here to use fall-through - Value *leftVal, *rightVal; - const Type* opType; + bool maskUnsignedResult = false; int nextRule; int forwardOperandNum = -1; - int64_t s0 = 0; // variables holding zero to avoid - uint64_t u0 = 0; // overloading ambiguities below + unsigned int allocaSize = 0; + MachineInstr* M, *M2; + unsigned int L; + + mvec.clear(); - mvec[0] = mvec[1] = mvec[2] = mvec[3] = NULL; // just for safety + // If the code for this instruction was folded into the parent (user), + // then do nothing! + if (subtreeRoot->isFoldedIntoParent()) + return; - switch(ruleForNode) { - case 1: // stmt: Ret - case 2: // stmt: RetValue(reg) - // NOTE: Prepass of register allocation is responsible - // for moving return value to appropriate register. - // Mark the return-address register as a hidden virtual reg. - { - Instruction* returnReg = new TmpInstruction(Instruction::UserOp1, - subtreeRoot->getInstruction(), NULL); - subtreeRoot->getInstruction()->getMachineInstrVec().addTempValue(returnReg); - - mvec[0] = new MachineInstr(RETURN); - mvec[0]->SetMachineOperand(0,MachineOperand::MO_VirtualRegister,returnReg); - mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed, s0); - - returnReg->addMachineInstruction(mvec[0]); - - mvec[numInstr++] = new MachineInstr(NOP); // delay slot - break; - } - - case 3: // stmt: Store(reg,reg) - case 4: // stmt: Store(reg,ptrreg) - mvec[0] = new MachineInstr(ChooseStoreInstruction(subtreeRoot->leftChild()->getValue()->getType())); - SetOperandsForMemInstr(mvec[0], subtreeRoot, target); - break; - - case 5: // stmt: BrUncond - mvec[0] = new MachineInstr(BA); - mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister, (Value*)NULL); - mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp, - ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0)); - - // delay slot - mvec[numInstr++] = new MachineInstr(NOP); - break; - - case 206: // stmt: BrCond(setCCconst) - // setCCconst => boolean was computed with `%b = setCC type reg1 constant' - // If the constant is ZERO, we can use the branch-on-integer-register - // instructions and avoid the SUBcc instruction entirely. - // Otherwise this is just the same as case 5, so just fall through. + // + // Let's check for chain rules outside the switch so that we don't have + // to duplicate the list of chain rule production numbers here again + // + if (ThisIsAChainRule(ruleForNode)) { - InstrTreeNode* constNode = subtreeRoot->leftChild()->rightChild(); - assert(constNode && constNode->getNodeType() ==InstrTreeNode::NTConstNode); - ConstPoolVal* constVal = (ConstPoolVal*) constNode->getValue(); - bool isValidConst; - - if ((constVal->getType()->isIntegral() - || constVal->getType()->isPointerType()) - && GetConstantValueAsSignedInt(constVal, isValidConst) == 0 - && isValidConst) - { - // That constant is a zero after all... - // Use the left child of the setCC instruction as the first argument! - mvec[0] = new MachineInstr(ChooseBprInstruction(subtreeRoot)); - mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, - subtreeRoot->leftChild()->leftChild()->getValue()); - mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp, - ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0)); - - // delay slot - mvec[numInstr++] = new MachineInstr(NOP); - - // false branch - mvec[numInstr++] = new MachineInstr(BA); - mvec[numInstr-1]->SetMachineOperand(0, MachineOperand::MO_CCRegister, - (Value*) NULL); - mvec[numInstr-1]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp, ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1)); - - // delay slot - mvec[numInstr++] = new MachineInstr(NOP); - - break; - } - // ELSE FALL THROUGH + // Chain rules have a single nonterminal on the RHS. + // Get the rule that matches the RHS non-terminal and use that instead. + // + assert(nts[0] && ! nts[1] + && "A chain rule should have only one RHS non-terminal!"); + nextRule = burm_rule(subtreeRoot->state, nts[0]); + nts = burm_nts[nextRule]; + GetInstructionsByRule(subtreeRoot, nextRule, nts, target, mvec); } - - case 6: // stmt: BrCond(bool) - // bool => boolean was computed with some boolean operator (setCC,Not,...) - // Need to check whether the type was a FP, signed int or unsigned int, - // and check the branching condition in order to choose the branch to use. - // + else { - bool isFPBranch; - mvec[0] = new MachineInstr(ChooseBccInstruction(subtreeRoot, isFPBranch)); - mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister, - subtreeRoot->leftChild()->getValue()); - mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp, - ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0)); - - // delay slot - mvec[numInstr++] = new MachineInstr(NOP); - - // false branch - mvec[numInstr++] = new MachineInstr(BA); - mvec[numInstr-1]->SetMachineOperand(0, MachineOperand::MO_CCRegister, - (Value*) NULL); - mvec[numInstr-1]->SetMachineOperand(0, MachineOperand::MO_PCRelativeDisp, - ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1)); - - // delay slot - mvec[numInstr++] = new MachineInstr(NOP); - break; - } - - case 8: // stmt: BrCond(boolreg) - case 208: // stmt: BrCond(boolconst) - // boolreg => boolean is stored in an existing register. - // boolconst => boolean is a constant; can be loaded into a register. - // Just use the branch-on-integer-register instruction! - // - mvec[0] = new MachineInstr(BRNZ); - mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, - subtreeRoot->leftChild()->getValue()); - mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp, - ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0)); - - // delay slot - mvec[numInstr++] = new MachineInstr(NOP); // delay slot - - // false branch - mvec[numInstr++] = new MachineInstr(BA); - mvec[numInstr-1]->SetMachineOperand(0, MachineOperand::MO_CCRegister, - (Value*) NULL); - mvec[numInstr-1]->SetMachineOperand(0, MachineOperand::MO_PCRelativeDisp, - ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1)); - - // delay slot - mvec[numInstr++] = new MachineInstr(NOP); - break; - - case 9: // stmt: Switch(reg) - assert(0 && "*** SWITCH instruction is not implemented yet."); - numInstr = 0; - break; - - case 10: // reg: VRegList(reg, reg) - assert(0 && "VRegList should never be the topmost non-chain rule"); - break; - - case 21: // reg: Not(reg): Implemented as reg = reg XOR-NOT 0 - mvec[0] = new MachineInstr(XNOR); - mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, - subtreeRoot->leftChild()->getValue()); - mvec[0]->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0); - mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, - subtreeRoot->getValue()); - break; - - case 322: // reg: ToBoolTy(bool): - case 22: // reg: ToBoolTy(reg): - opType = subtreeRoot->leftChild()->getValue()->getType(); - assert(opType->isIntegral() || opType == Type::BoolTy); - numInstr = 0; - forwardOperandNum = 0; - break; - - case 23: // reg: ToUByteTy(reg) - case 25: // reg: ToUShortTy(reg) - case 27: // reg: ToUIntTy(reg) - case 29: // reg: ToULongTy(reg) - opType = subtreeRoot->leftChild()->getValue()->getType(); - assert(opType->isIntegral() || - opType->isPointerType() || - opType == Type::BoolTy && "Ignoring cast: illegal for other types"); - numInstr = 0; - forwardOperandNum = 0; - break; - - case 24: // reg: ToSByteTy(reg) - case 26: // reg: ToShortTy(reg) - case 28: // reg: ToIntTy(reg) - case 30: // reg: ToLongTy(reg) - opType = subtreeRoot->leftChild()->getValue()->getType(); - if (opType->isIntegral() || opType == Type::BoolTy) - { - numInstr = 0; - forwardOperandNum = 0; + switch(ruleForNode) { + case 1: // stmt: Ret + case 2: // stmt: RetValue(reg) + { // NOTE: Prepass of register allocation is responsible + // for moving return value to appropriate register. + // Mark the return-address register as a hidden virtual reg. + // Mark the return value register as an implicit ref of + // the machine instruction. + // Finally put a NOP in the delay slot. + ReturnInst *returnInstr = + cast(subtreeRoot->getInstruction()); + assert(returnInstr->getOpcode() == Instruction::Ret); + + Instruction* returnReg = new TmpInstruction(returnInstr); + MachineCodeForInstruction::get(returnInstr).addTemp(returnReg); + + M = new MachineInstr(JMPLRET); + M->SetMachineOperandReg(0, MachineOperand::MO_VirtualRegister, + returnReg); + M->SetMachineOperandConst(1,MachineOperand::MO_SignExtendedImmed, + (int64_t)8); + M->SetMachineOperandReg(2, target.getRegInfo().getZeroRegNum()); + + if (returnInstr->getReturnValue() != NULL) + M->addImplicitRef(returnInstr->getReturnValue()); + + mvec.push_back(M); + mvec.push_back(new MachineInstr(NOP)); + + break; + } + + case 3: // stmt: Store(reg,reg) + case 4: // stmt: Store(reg,ptrreg) + mvec.push_back(new MachineInstr( + ChooseStoreInstruction( + subtreeRoot->leftChild()->getValue()->getType()))); + SetOperandsForMemInstr(mvec, subtreeRoot, target); + break; + + case 5: // stmt: BrUncond + M = new MachineInstr(BA); + M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp, + cast(subtreeRoot->getInstruction())->getSuccessor(0)); + mvec.push_back(M); + + // delay slot + mvec.push_back(new MachineInstr(NOP)); + break; + + case 206: // stmt: BrCond(setCCconst) + { // setCCconst => boolean was computed with `%b = setCC type reg1 const' + // If the constant is ZERO, we can use the branch-on-integer-register + // instructions and avoid the SUBcc instruction entirely. + // Otherwise this is just the same as case 5, so just fall through. + // + InstrTreeNode* constNode = subtreeRoot->leftChild()->rightChild(); + assert(constNode && + constNode->getNodeType() ==InstrTreeNode::NTConstNode); + Constant *constVal = cast(constNode->getValue()); + bool isValidConst; + + if ((constVal->getType()->isInteger() + || isa(constVal->getType())) + && GetConstantValueAsSignedInt(constVal, isValidConst) == 0 + && isValidConst) + { + // That constant is a zero after all... + // Use the left child of setCC as the first argument! + // Mark the setCC node so that no code is generated for it. + InstructionNode* setCCNode = (InstructionNode*) + subtreeRoot->leftChild(); + assert(setCCNode->getOpLabel() == SetCCOp); + setCCNode->markFoldedIntoParent(); + + BranchInst* brInst=cast(subtreeRoot->getInstruction()); + + M = new MachineInstr(ChooseBprInstruction(subtreeRoot)); + M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, + setCCNode->leftChild()->getValue()); + M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp, + brInst->getSuccessor(0)); + mvec.push_back(M); + + // delay slot + mvec.push_back(new MachineInstr(NOP)); + + // false branch + M = new MachineInstr(BA); + M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp, + brInst->getSuccessor(1)); + mvec.push_back(M); + + // delay slot + mvec.push_back(new MachineInstr(NOP)); + + break; + } + // ELSE FALL THROUGH } - else - { - mvec[0] =new MachineInstr(ChooseConvertToIntInstr(subtreeRoot,opType)); - Set2OperandsFromInstr(mvec[0], subtreeRoot, target); + + case 6: // stmt: BrCond(setCC) + { // bool => boolean was computed with SetCC. + // The branch to use depends on whether it is FP, signed, or unsigned. + // If it is an integer CC, we also need to find the unique + // TmpInstruction representing that CC. + // + BranchInst* brInst = cast(subtreeRoot->getInstruction()); + bool isFPBranch; + M = new MachineInstr(ChooseBccInstruction(subtreeRoot, isFPBranch)); + + Value* ccValue = GetTmpForCC(subtreeRoot->leftChild()->getValue(), + brInst->getParent()->getParent(), + isFPBranch? Type::FloatTy : Type::IntTy); + + M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister, ccValue); + M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp, + brInst->getSuccessor(0)); + mvec.push_back(M); + + // delay slot + mvec.push_back(new MachineInstr(NOP)); + + // false branch + M = new MachineInstr(BA); + M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp, + brInst->getSuccessor(1)); + mvec.push_back(M); + + // delay slot + mvec.push_back(new MachineInstr(NOP)); + break; } - break; - - case 31: // reg: ToFloatTy(reg): - case 32: // reg: ToDoubleTy(reg): - - // If this instruction has a parent (a user) in the tree - // and the user is translated as an FsMULd instruction, - // then the cast is unnecessary. So check that first. - // In the future, we'll want to do the same for the FdMULq instruction, - // so do the check here instead of only for ToFloatTy(reg). - // - if (subtreeRoot->parent() != NULL && - ((InstructionNode*) subtreeRoot->parent())->getInstruction()->getMachineInstrVec()[0]->getOpCode() == FSMULD) + + case 208: // stmt: BrCond(boolconst) { - numInstr = 0; - forwardOperandNum = 0; + // boolconst => boolean is a constant; use BA to first or second label + Constant* constVal = + cast(subtreeRoot->leftChild()->getValue()); + unsigned dest = cast(constVal)->getValue()? 0 : 1; + + M = new MachineInstr(BA); + M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp, + cast(subtreeRoot->getInstruction())->getSuccessor(dest)); + mvec.push_back(M); + + // delay slot + mvec.push_back(new MachineInstr(NOP)); + break; } - else + + case 8: // stmt: BrCond(boolreg) + { // boolreg => boolean is stored in an existing register. + // Just use the branch-on-integer-register instruction! + // + M = new MachineInstr(BRNZ); + M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, + subtreeRoot->leftChild()->getValue()); + M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp, + cast(subtreeRoot->getInstruction())->getSuccessor(0)); + mvec.push_back(M); + + // delay slot + mvec.push_back(new MachineInstr(NOP)); + + // false branch + M = new MachineInstr(BA); + M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp, + cast(subtreeRoot->getInstruction())->getSuccessor(1)); + mvec.push_back(M); + + // delay slot + mvec.push_back(new MachineInstr(NOP)); + break; + } + + case 9: // stmt: Switch(reg) + assert(0 && "*** SWITCH instruction is not implemented yet."); + break; + + case 10: // reg: VRegList(reg, reg) + assert(0 && "VRegList should never be the topmost non-chain rule"); + break; + + case 21: // bool: Not(bool,reg): Both these are implemented as: + case 421: // reg: BNot(reg,reg): reg = reg XOR-NOT 0 + { // First find the unary operand. It may be left or right, usually right. + Value* notArg = BinaryOperator::getNotArgument( + cast(subtreeRoot->getInstruction())); + mvec.push_back(Create3OperandInstr_Reg(XNOR, notArg, + target.getRegInfo().getZeroRegNum(), + subtreeRoot->getValue())); + break; + } + + case 22: // reg: ToBoolTy(reg): { - opType = subtreeRoot->leftChild()->getValue()->getType(); - MachineOpCode opCode = ChooseConvertToFloatInstr(subtreeRoot, opType); - if (opCode == INVALID_OPCODE) // no conversion needed - { - numInstr = 0; - forwardOperandNum = 0; - } - else - { - mvec[0] = new MachineInstr(opCode); - Set2OperandsFromInstr(mvec[0], subtreeRoot, target); - } + const Type* opType = subtreeRoot->leftChild()->getValue()->getType(); + assert(opType->isIntegral() || isa(opType)); + forwardOperandNum = 0; // forward first operand to user + break; } - break; - - case 19: // reg: ToArrayTy(reg): - case 20: // reg: ToPointerTy(reg): - numInstr = 0; - forwardOperandNum = 0; - break; - - case 233: // reg: Add(reg, Constant) - mvec[0] = CreateAddConstInstruction(subtreeRoot); - if (mvec[0] != NULL) - break; - // ELSE FALL THROUGH - - case 33: // reg: Add(reg, reg) - mvec[0] = new MachineInstr(ChooseAddInstruction(subtreeRoot)); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 234: // reg: Sub(reg, Constant) - mvec[0] = CreateSubConstInstruction(subtreeRoot); - if (mvec[0] != NULL) - break; - // ELSE FALL THROUGH - - case 34: // reg: Sub(reg, reg) - mvec[0] = new MachineInstr(ChooseSubInstruction(subtreeRoot)); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 135: // reg: Mul(todouble, todouble) - checkCast = true; - // FALL THROUGH - - case 35: // reg: Mul(reg, reg) - mvec[0] = new MachineInstr(ChooseMulInstruction(subtreeRoot, checkCast)); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 335: // reg: Mul(todouble, todoubleConst) - checkCast = true; - // FALL THROUGH - - case 235: // reg: Mul(reg, Constant) - mvec[0] = CreateMulConstInstruction(subtreeRoot, mvec[1]); - if (mvec[0] == NULL) + + case 23: // reg: ToUByteTy(reg) + case 24: // reg: ToSByteTy(reg) + case 25: // reg: ToUShortTy(reg) + case 26: // reg: ToShortTy(reg) + case 27: // reg: ToUIntTy(reg) + case 28: // reg: ToIntTy(reg) { - mvec[0]=new MachineInstr(ChooseMulInstruction(subtreeRoot, checkCast)); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); + //====================================================================== + // Rules for integer conversions: + // + //-------- + // From ISO 1998 C++ Standard, Sec. 4.7: + // + // 2. If the destination type is unsigned, the resulting value is + // the least unsigned integer congruent to the source integer + // (modulo 2n where n is the number of bits used to represent the + // unsigned type). [Note: In a two s complement representation, + // this conversion is conceptual and there is no change in the + // bit pattern (if there is no truncation). ] + // + // 3. If the destination type is signed, the value is unchanged if + // it can be represented in the destination type (and bitfield width); + // otherwise, the value is implementation-defined. + //-------- + // + // Since we assume 2s complement representations, this implies: + // + // -- if operand is smaller than destination, zero-extend or sign-extend + // according to the signedness of the *operand*: source decides. + // ==> we have to do nothing here! + // + // -- if operand is same size as or larger than destination, and the + // destination is *unsigned*, zero-extend the operand: dest. decides + // + // -- if operand is same size as or larger than destination, and the + // destination is *signed*, the choice is implementation defined: + // we sign-extend the operand: i.e., again dest. decides. + // Note: this matches both Sun's cc and gcc3.2. + //====================================================================== + + Instruction* destI = subtreeRoot->getInstruction(); + Value* opVal = subtreeRoot->leftChild()->getValue(); + const Type* opType = opVal->getType(); + if (opType->isIntegral() || isa(opType)) + { + unsigned opSize = target.DataLayout.getTypeSize(opType); + unsigned destSize = target.DataLayout.getTypeSize(destI->getType()); + if (opSize >= destSize) + { // Operand is same size as or larger than dest: + // zero- or sign-extend, according to the signeddness of + // the destination (see above). + if (destI->getType()->isSigned()) + target.getInstrInfo().CreateSignExtensionInstructions(target, + destI->getParent()->getParent(), opVal, destI, 8*destSize, + mvec, MachineCodeForInstruction::get(destI)); + else + target.getInstrInfo().CreateZeroExtensionInstructions(target, + destI->getParent()->getParent(), opVal, destI, 8*destSize, + mvec, MachineCodeForInstruction::get(destI)); + } + else + forwardOperandNum = 0; // forward first operand to user + } + else if (opType->isFloatingPoint()) + { + CreateCodeToConvertFloatToInt(target, opVal, destI, mvec, + MachineCodeForInstruction::get(destI)); + if (destI->getType()->isUnsigned()) + maskUnsignedResult = true; // not handled by fp->int code + } + else + assert(0 && "Unrecognized operand type for convert-to-unsigned"); + + break; } - else - if (mvec[1] != NULL) - ++numInstr; - break; - - case 236: // reg: Div(reg, Constant) - mvec[0] = CreateDivConstInstruction(subtreeRoot, mvec[1]); - if (mvec[0] != NULL) + + case 29: // reg: ToULongTy(reg) + case 30: // reg: ToLongTy(reg) { - if (mvec[1] != NULL) - ++numInstr; + Value* opVal = subtreeRoot->leftChild()->getValue(); + const Type* opType = opVal->getType(); + if (opType->isIntegral() || isa(opType)) + forwardOperandNum = 0; // forward first operand to user + else if (opType->isFloatingPoint()) + { + Instruction* destI = subtreeRoot->getInstruction(); + CreateCodeToConvertFloatToInt(target, opVal, destI, mvec, + MachineCodeForInstruction::get(destI)); + } + else + assert(0 && "Unrecognized operand type for convert-to-signed"); + break; } - else - // ELSE FALL THROUGH - - case 36: // reg: Div(reg, reg) - mvec[0] = new MachineInstr(ChooseDivInstruction(subtreeRoot)); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 37: // reg: Rem(reg, reg) - case 237: // reg: Rem(reg, Constant) - assert(0 && "REM instruction unimplemented for the SPARC."); - break; - - case 38: // reg: And(reg, reg) - case 238: // reg: And(reg, Constant) - mvec[0] = new MachineInstr(AND); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 138: // reg: And(reg, not) - mvec[0] = new MachineInstr(ANDN); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 39: // reg: Or(reg, reg) - case 239: // reg: Or(reg, Constant) - mvec[0] = new MachineInstr(ORN); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 139: // reg: Or(reg, not) - mvec[0] = new MachineInstr(ORN); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 40: // reg: Xor(reg, reg) - case 240: // reg: Xor(reg, Constant) - mvec[0] = new MachineInstr(XOR); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 140: // reg: Xor(reg, not) - mvec[0] = new MachineInstr(XNOR); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 41: // boolconst: SetCC(reg, Constant) - // Check if this is an integer comparison, and - // there is a parent, and the parent decided to use - // a branch-on-integer-register instead of branch-on-condition-code. - // If so, the SUBcc instruction is not required. - // (However, we must still check for constants to be loaded from - // the constant pool so that such a load can be associated with - // this instruction.) - // - // Otherwise this is just the same as case 42, so just fall through. - // - if (subtreeRoot->leftChild()->getValue()->getType()->isIntegral() && - subtreeRoot->parent() != NULL) + + case 31: // reg: ToFloatTy(reg): + case 32: // reg: ToDoubleTy(reg): + case 232: // reg: ToDoubleTy(Constant): + + // If this instruction has a parent (a user) in the tree + // and the user is translated as an FsMULd instruction, + // then the cast is unnecessary. So check that first. + // In the future, we'll want to do the same for the FdMULq instruction, + // so do the check here instead of only for ToFloatTy(reg). + // + if (subtreeRoot->parent() != NULL) + { + const MachineCodeForInstruction& mcfi = + MachineCodeForInstruction::get( + cast(subtreeRoot->parent())->getInstruction()); + if (mcfi.size() == 0 || mcfi.front()->getOpCode() == FSMULD) + forwardOperandNum = 0; // forward first operand to user + } + + if (forwardOperandNum != 0) // we do need the cast + { + Value* leftVal = subtreeRoot->leftChild()->getValue(); + const Type* opType = leftVal->getType(); + MachineOpCode opCode=ChooseConvertToFloatInstr( + subtreeRoot->getOpLabel(), opType); + if (opCode == INVALID_OPCODE) // no conversion needed + { + forwardOperandNum = 0; // forward first operand to user + } + else + { + // If the source operand is a non-FP type it must be + // first copied from int to float register via memory! + Instruction *dest = subtreeRoot->getInstruction(); + Value* srcForCast; + int n = 0; + if (! opType->isFloatingPoint()) + { + // Create a temporary to represent the FP register + // into which the integer will be copied via memory. + // The type of this temporary will determine the FP + // register used: single-prec for a 32-bit int or smaller, + // double-prec for a 64-bit int. + // + uint64_t srcSize = + target.DataLayout.getTypeSize(leftVal->getType()); + Type* tmpTypeToUse = + (srcSize <= 4)? Type::FloatTy : Type::DoubleTy; + srcForCast = new TmpInstruction(tmpTypeToUse, dest); + MachineCodeForInstruction &destMCFI = + MachineCodeForInstruction::get(dest); + destMCFI.addTemp(srcForCast); + + target.getInstrInfo().CreateCodeToCopyIntToFloat(target, + dest->getParent()->getParent(), + leftVal, cast(srcForCast), + mvec, destMCFI); + } + else + srcForCast = leftVal; + + M = new MachineInstr(opCode); + M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, + srcForCast); + M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, + dest); + mvec.push_back(M); + } + } + break; + + case 19: // reg: ToArrayTy(reg): + case 20: // reg: ToPointerTy(reg): + forwardOperandNum = 0; // forward first operand to user + break; + + case 233: // reg: Add(reg, Constant) + maskUnsignedResult = true; + M = CreateAddConstInstruction(subtreeRoot); + if (M != NULL) + { + mvec.push_back(M); + break; + } + // ELSE FALL THROUGH + + case 33: // reg: Add(reg, reg) + maskUnsignedResult = true; + mvec.push_back(new MachineInstr(ChooseAddInstruction(subtreeRoot))); + Set3OperandsFromInstr(mvec.back(), subtreeRoot, target); + break; + + case 234: // reg: Sub(reg, Constant) + maskUnsignedResult = true; + M = CreateSubConstInstruction(subtreeRoot); + if (M != NULL) + { + mvec.push_back(M); + break; + } + // ELSE FALL THROUGH + + case 34: // reg: Sub(reg, reg) + maskUnsignedResult = true; + mvec.push_back(new MachineInstr(ChooseSubInstructionByType( + subtreeRoot->getInstruction()->getType()))); + Set3OperandsFromInstr(mvec.back(), subtreeRoot, target); + break; + + case 135: // reg: Mul(todouble, todouble) + checkCast = true; + // FALL THROUGH + + case 35: // reg: Mul(reg, reg) { - InstructionNode* parentNode = (InstructionNode*) subtreeRoot->parent(); - assert(parentNode->getNodeType() == InstrTreeNode::NTInstructionNode); - const vector& - minstrVec = parentNode->getInstruction()->getMachineInstrVec(); - MachineOpCode parentOpCode; - if (parentNode->getInstruction()->getOpcode() == Instruction::Br && - (parentOpCode = minstrVec[0]->getOpCode()) >= BRZ && - parentOpCode <= BRGEZ) - { - numInstr = 0; // don't forward the operand! - break; - } + maskUnsignedResult = true; + MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot)) + ? FSMULD + : INVALID_MACHINE_OPCODE); + Instruction* mulInstr = subtreeRoot->getInstruction(); + CreateMulInstruction(target, mulInstr->getParent()->getParent(), + subtreeRoot->leftChild()->getValue(), + subtreeRoot->rightChild()->getValue(), + mulInstr, mvec, + MachineCodeForInstruction::get(mulInstr),forceOp); + break; } - // ELSE FALL THROUGH - - case 42: // bool: SetCC(reg, reg): - { - // If result of the SetCC is only used for a branch, we can - // discard the result. otherwise, it must go into an integer register. - // Note that the user may or may not be in the same tree, so we have - // to follow SSA def-use edges here, not BURG tree edges. - // - Instruction* result = subtreeRoot->getInstruction(); - Value* firstUse = result->use_empty() ? 0 : *result->use_begin(); - bool discardResult = - (result->use_size() == 1 - && firstUse->isInstruction() - && ((Instruction*) firstUse)->getOpcode() == Instruction::Br); - - bool mustClearReg; - int valueToMove; - MachineOpCode movOpCode; - - if (subtreeRoot->leftChild()->getValue()->getType()->isIntegral() || - subtreeRoot->leftChild()->getValue()->getType()->isPointerType()) + case 335: // reg: Mul(todouble, todoubleConst) + checkCast = true; + // FALL THROUGH + + case 235: // reg: Mul(reg, Constant) { - // Integer condition: destination should be %g0 or integer register. - // If result must be saved but condition is not SetEQ then we need - // a separate instruction to compute the bool result, so discard - // result of SUBcc instruction anyway. - // - mvec[0] = new MachineInstr(SUBcc); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target, discardResult); - - // mark the 4th operand as being a CC register, and a "result" - mvec[0]->SetMachineOperand(3, MachineOperand::MO_CCRegister, - subtreeRoot->getValue(), /*def*/ true); - - if (!discardResult) - { // recompute bool if needed, using the integer condition codes - if (result->getOpcode() == Instruction::SetNE) - discardResult = true; - else - movOpCode = - ChooseMovpccAfterSub(subtreeRoot, mustClearReg, valueToMove); - } + maskUnsignedResult = true; + MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot)) + ? FSMULD + : INVALID_MACHINE_OPCODE); + Instruction* mulInstr = subtreeRoot->getInstruction(); + CreateMulInstruction(target, mulInstr->getParent()->getParent(), + subtreeRoot->leftChild()->getValue(), + subtreeRoot->rightChild()->getValue(), + mulInstr, mvec, + MachineCodeForInstruction::get(mulInstr), + forceOp); + break; } - else + case 236: // reg: Div(reg, Constant) + maskUnsignedResult = true; + L = mvec.size(); + CreateDivConstInstruction(target, subtreeRoot, mvec); + if (mvec.size() > L) + break; + // ELSE FALL THROUGH + + case 36: // reg: Div(reg, reg) + maskUnsignedResult = true; + mvec.push_back(new MachineInstr(ChooseDivInstruction(target, subtreeRoot))); + Set3OperandsFromInstr(mvec.back(), subtreeRoot, target); + break; + + case 37: // reg: Rem(reg, reg) + case 237: // reg: Rem(reg, Constant) { - // FP condition: dest of FCMP should be some FCCn register - mvec[0] = new MachineInstr(ChooseFcmpInstruction(subtreeRoot)); - mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister, - subtreeRoot->getValue()); - mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, - subtreeRoot->leftChild()->getValue()); - mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, - subtreeRoot->rightChild()->getValue()); - - if (!discardResult) - {// recompute bool using the FP condition codes - mustClearReg = true; - valueToMove = 1; - movOpCode = ChooseMovFpccInstruction(subtreeRoot); - } + maskUnsignedResult = true; + Instruction* remInstr = subtreeRoot->getInstruction(); + + TmpInstruction* quot = new TmpInstruction( + subtreeRoot->leftChild()->getValue(), + subtreeRoot->rightChild()->getValue()); + TmpInstruction* prod = new TmpInstruction( + quot, + subtreeRoot->rightChild()->getValue()); + MachineCodeForInstruction::get(remInstr).addTemp(quot).addTemp(prod); + + M = new MachineInstr(ChooseDivInstruction(target, subtreeRoot)); + Set3OperandsFromInstr(M, subtreeRoot, target); + M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,quot); + mvec.push_back(M); + + M = Create3OperandInstr(ChooseMulInstructionByType( + subtreeRoot->getInstruction()->getType()), + quot, subtreeRoot->rightChild()->getValue(), + prod); + mvec.push_back(M); + + M = new MachineInstr(ChooseSubInstructionByType( + subtreeRoot->getInstruction()->getType())); + Set3OperandsFromInstr(M, subtreeRoot, target); + M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,prod); + mvec.push_back(M); + + break; + } + + case 38: // bool: And(bool, bool) + case 238: // bool: And(bool, boolconst) + case 338: // reg : BAnd(reg, reg) + case 538: // reg : BAnd(reg, Constant) + mvec.push_back(new MachineInstr(AND)); + Set3OperandsFromInstr(mvec.back(), subtreeRoot, target); + break; + + case 138: // bool: And(bool, not) + case 438: // bool: BAnd(bool, bnot) + { // Use the argument of NOT as the second argument! + // Mark the NOT node so that no code is generated for it. + InstructionNode* notNode = (InstructionNode*) subtreeRoot->rightChild(); + Value* notArg = BinaryOperator::getNotArgument( + cast(notNode->getInstruction())); + notNode->markFoldedIntoParent(); + mvec.push_back(Create3OperandInstr(ANDN, + subtreeRoot->leftChild()->getValue(), + notArg, subtreeRoot->getValue())); + break; } - - if (!discardResult) + + case 39: // bool: Or(bool, bool) + case 239: // bool: Or(bool, boolconst) + case 339: // reg : BOr(reg, reg) + case 539: // reg : BOr(reg, Constant) + mvec.push_back(new MachineInstr(OR)); + Set3OperandsFromInstr(mvec.back(), subtreeRoot, target); + break; + + case 139: // bool: Or(bool, not) + case 439: // bool: BOr(bool, bnot) + { // Use the argument of NOT as the second argument! + // Mark the NOT node so that no code is generated for it. + InstructionNode* notNode = (InstructionNode*) subtreeRoot->rightChild(); + Value* notArg = BinaryOperator::getNotArgument( + cast(notNode->getInstruction())); + notNode->markFoldedIntoParent(); + mvec.push_back(Create3OperandInstr(ORN, + subtreeRoot->leftChild()->getValue(), + notArg, subtreeRoot->getValue())); + break; + } + + case 40: // bool: Xor(bool, bool) + case 240: // bool: Xor(bool, boolconst) + case 340: // reg : BXor(reg, reg) + case 540: // reg : BXor(reg, Constant) + mvec.push_back(new MachineInstr(XOR)); + Set3OperandsFromInstr(mvec.back(), subtreeRoot, target); + break; + + case 140: // bool: Xor(bool, not) + case 440: // bool: BXor(bool, bnot) + { // Use the argument of NOT as the second argument! + // Mark the NOT node so that no code is generated for it. + InstructionNode* notNode = (InstructionNode*) subtreeRoot->rightChild(); + Value* notArg = BinaryOperator::getNotArgument( + cast(notNode->getInstruction())); + notNode->markFoldedIntoParent(); + mvec.push_back(Create3OperandInstr(XNOR, + subtreeRoot->leftChild()->getValue(), + notArg, subtreeRoot->getValue())); + break; + } + + case 41: // boolconst: SetCC(reg, Constant) + // + // If the SetCC was folded into the user (parent), it will be + // caught above. All other cases are the same as case 42, + // so just fall through. + // + case 42: // bool: SetCC(reg, reg): { - if (mustClearReg) - {// Unconditionally set register to 0 - int n = numInstr++; - mvec[n] = new MachineInstr(SETHI); - mvec[n]->SetMachineOperand(0,MachineOperand::MO_UnextendedImmed,s0); - mvec[n]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, - subtreeRoot->getValue()); - } - - // Now conditionally move `valueToMove' (0 or 1) into the register - int n = numInstr++; - mvec[n] = new MachineInstr(movOpCode); - mvec[n]->SetMachineOperand(0, MachineOperand::MO_CCRegister, - subtreeRoot->getValue()); - mvec[n]->SetMachineOperand(1, MachineOperand::MO_UnextendedImmed, - valueToMove); - mvec[n]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, - subtreeRoot->getValue()); + // This generates a SUBCC instruction, putting the difference in + // a result register, and setting a condition code. + // + // If the boolean result of the SetCC is used by anything other + // than a branch instruction, or if it is used outside the current + // basic block, the boolean must be + // computed and stored in the result register. Otherwise, discard + // the difference (by using %g0) and keep only the condition code. + // + // To compute the boolean result in a register we use a conditional + // move, unless the result of the SUBCC instruction can be used as + // the bool! This assumes that zero is FALSE and any non-zero + // integer is TRUE. + // + InstructionNode* parentNode = (InstructionNode*) subtreeRoot->parent(); + Instruction* setCCInstr = subtreeRoot->getInstruction(); + + bool keepBoolVal = parentNode == NULL || + ! AllUsesAreBranches(setCCInstr); + bool subValIsBoolVal = setCCInstr->getOpcode() == Instruction::SetNE; + bool keepSubVal = keepBoolVal && subValIsBoolVal; + bool computeBoolVal = keepBoolVal && ! subValIsBoolVal; + + bool mustClearReg; + int valueToMove; + MachineOpCode movOpCode = 0; + + // Mark the 4th operand as being a CC register, and as a def + // A TmpInstruction is created to represent the CC "result". + // Unlike other instances of TmpInstruction, this one is used + // by machine code of multiple LLVM instructions, viz., + // the SetCC and the branch. Make sure to get the same one! + // Note that we do this even for FP CC registers even though they + // are explicit operands, because the type of the operand + // needs to be a floating point condition code, not an integer + // condition code. Think of this as casting the bool result to + // a FP condition code register. + // + Value* leftVal = subtreeRoot->leftChild()->getValue(); + bool isFPCompare = leftVal->getType()->isFloatingPoint(); + + TmpInstruction* tmpForCC = GetTmpForCC(setCCInstr, + setCCInstr->getParent()->getParent(), + isFPCompare ? Type::FloatTy : Type::IntTy); + MachineCodeForInstruction::get(setCCInstr).addTemp(tmpForCC); + + if (! isFPCompare) + { + // Integer condition: dest. should be %g0 or an integer register. + // If result must be saved but condition is not SetEQ then we need + // a separate instruction to compute the bool result, so discard + // result of SUBcc instruction anyway. + // + M = new MachineInstr(SUBcc); + Set3OperandsFromInstr(M, subtreeRoot, target, ! keepSubVal); + M->SetMachineOperandVal(3, MachineOperand::MO_CCRegister, + tmpForCC, /*def*/true); + mvec.push_back(M); + + if (computeBoolVal) + { // recompute bool using the integer condition codes + movOpCode = + ChooseMovpccAfterSub(subtreeRoot,mustClearReg,valueToMove); + } + } + else + { + // FP condition: dest of FCMP should be some FCCn register + M = new MachineInstr(ChooseFcmpInstruction(subtreeRoot)); + M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister, + tmpForCC); + M->SetMachineOperandVal(1,MachineOperand::MO_VirtualRegister, + subtreeRoot->leftChild()->getValue()); + M->SetMachineOperandVal(2,MachineOperand::MO_VirtualRegister, + subtreeRoot->rightChild()->getValue()); + mvec.push_back(M); + + if (computeBoolVal) + {// recompute bool using the FP condition codes + mustClearReg = true; + valueToMove = 1; + movOpCode = ChooseMovFpccInstruction(subtreeRoot); + } + } + + if (computeBoolVal) + { + if (mustClearReg) + {// Unconditionally set register to 0 + M = new MachineInstr(SETHI); + M->SetMachineOperandConst(0,MachineOperand::MO_UnextendedImmed, + (int64_t)0); + M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, + setCCInstr); + mvec.push_back(M); + } + + // Now conditionally move `valueToMove' (0 or 1) into the register + // Mark the register as a use (as well as a def) because the old + // value should be retained if the condition is false. + M = new MachineInstr(movOpCode); + M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister, + tmpForCC); + M->SetMachineOperandConst(1, MachineOperand::MO_UnextendedImmed, + valueToMove); + M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, + setCCInstr, /*isDef*/ true, + /*isDefAndUse*/ true); + mvec.push_back(M); + } + break; + } + + case 51: // reg: Load(reg) + case 52: // reg: Load(ptrreg) + mvec.push_back(new MachineInstr(ChooseLoadInstruction( + subtreeRoot->getValue()->getType()))); + SetOperandsForMemInstr(mvec, subtreeRoot, target); + break; + + case 55: // reg: GetElemPtr(reg) + case 56: // reg: GetElemPtrIdx(reg,reg) + // If the GetElemPtr was folded into the user (parent), it will be + // caught above. For other cases, we have to compute the address. + mvec.push_back(new MachineInstr(ADD)); + SetOperandsForMemInstr(mvec, subtreeRoot, target); + break; + + case 57: // reg: Alloca: Implement as 1 instruction: + { // add %fp, offsetFromFP -> result + AllocationInst* instr = + cast(subtreeRoot->getInstruction()); + unsigned int tsize = + target.DataLayout.getTypeSize(instr->getAllocatedType()); + assert(tsize != 0); + CreateCodeForFixedSizeAlloca(target, instr, tsize, 1, mvec); + break; } - break; - } - - case 43: // boolreg: VReg - case 44: // boolreg: Constant - numInstr = 0; - break; - - case 51: // reg: Load(reg) - case 52: // reg: Load(ptrreg) - case 53: // reg: LoadIdx(reg,reg) - case 54: // reg: LoadIdx(ptrreg,reg) - mvec[0] = new MachineInstr(ChooseLoadInstruction(subtreeRoot->getValue()->getType())); - SetOperandsForMemInstr(mvec[0], subtreeRoot, target); - break; - - case 55: // reg: GetElemPtr(reg) - case 56: // reg: GetElemPtrIdx(reg,reg) - if (subtreeRoot->parent() != NULL) + + case 58: // reg: Alloca(reg): Implement as 3 instructions: + // mul num, typeSz -> tmp + // sub %sp, tmp -> %sp + { // add %sp, frameSizeBelowDynamicArea -> result + AllocationInst* instr = + cast(subtreeRoot->getInstruction()); + const Type* eltType = instr->getAllocatedType(); + + // If #elements is constant, use simpler code for fixed-size allocas + int tsize = (int) target.DataLayout.getTypeSize(eltType); + Value* numElementsVal = NULL; + bool isArray = instr->isArrayAllocation(); + + if (!isArray || + isa(numElementsVal = instr->getArraySize())) + { // total size is constant: generate code for fixed-size alloca + unsigned int numElements = isArray? + cast(numElementsVal)->getValue() : 1; + CreateCodeForFixedSizeAlloca(target, instr, tsize, + numElements, mvec); + } + else // total size is not constant. + CreateCodeForVariableSizeAlloca(target, instr, tsize, + numElementsVal, mvec); + break; + } + + case 61: // reg: Call + { // Generate a direct (CALL) or indirect (JMPL) call. + // Mark the return-address register, the indirection + // register (for indirect calls), the operands of the Call, + // and the return value (if any) as implicit operands + // of the machine instruction. + // + // If this is a varargs function, floating point arguments + // have to passed in integer registers so insert + // copy-float-to-int instructions for each float operand. + // + CallInst *callInstr = cast(subtreeRoot->getInstruction()); + Value *callee = callInstr->getCalledValue(); + + // Create hidden virtual register for return address with type void* + TmpInstruction* retAddrReg = + new TmpInstruction(PointerType::get(Type::VoidTy), callInstr); + MachineCodeForInstruction::get(callInstr).addTemp(retAddrReg); + + // Generate the machine instruction and its operands. + // Use CALL for direct function calls; this optimistically assumes + // the PC-relative address fits in the CALL address field (22 bits). + // Use JMPL for indirect calls. + // + if (isa(callee)) // direct function call + M = Create1OperandInstr_Addr(CALL, callee); + else // indirect function call + M = Create3OperandInstr_SImmed(JMPLCALL, callee, + (int64_t) 0, retAddrReg); + mvec.push_back(M); + + const FunctionType* funcType = + cast(cast(callee->getType()) + ->getElementType()); + bool isVarArgs = funcType->isVarArg(); + bool noPrototype = isVarArgs && funcType->getNumParams() == 0; + + // Use an annotation to pass information about call arguments + // to the register allocator. + CallArgsDescriptor* argDesc = new CallArgsDescriptor(callInstr, + retAddrReg, isVarArgs, noPrototype); + M->addAnnotation(argDesc); + + assert(callInstr->getOperand(0) == callee + && "This is assumed in the loop below!"); + + for (unsigned i=1, N=callInstr->getNumOperands(); i < N; ++i) + { + Value* argVal = callInstr->getOperand(i); + Instruction* intArgReg = NULL; + + // Check for FP arguments to varargs functions. + // Any such argument in the first $K$ args must be passed in an + // integer register, where K = #integer argument registers. + if (isVarArgs && argVal->getType()->isFloatingPoint()) + { + // If it is a function with no prototype, pass value + // as an FP value as well as a varargs value + if (noPrototype) + argDesc->getArgInfo(i-1).setUseFPArgReg(); + + // If this arg. is in the first $K$ regs, add a copy + // float-to-int instruction to pass the value as an integer. + if (i <= target.getRegInfo().GetNumOfIntArgRegs()) + { + MachineCodeForInstruction &destMCFI = + MachineCodeForInstruction::get(callInstr); + intArgReg = new TmpInstruction(Type::IntTy, argVal); + destMCFI.addTemp(intArgReg); + + vector copyMvec; + target.getInstrInfo().CreateCodeToCopyFloatToInt(target, + callInstr->getParent()->getParent(), + argVal, (TmpInstruction*) intArgReg, + copyMvec, destMCFI); + mvec.insert(mvec.begin(),copyMvec.begin(),copyMvec.end()); + + argDesc->getArgInfo(i-1).setUseIntArgReg(); + argDesc->getArgInfo(i-1).setArgCopy(intArgReg); + } + else + // Cannot fit in first $K$ regs so pass the arg on the stack + argDesc->getArgInfo(i-1).setUseStackSlot(); + } + + if (intArgReg) + mvec.back()->addImplicitRef(intArgReg); + + mvec.back()->addImplicitRef(argVal); + } + + // Add the return value as an implicit ref. The call operands + // were added above. + if (callInstr->getType() != Type::VoidTy) + mvec.back()->addImplicitRef(callInstr, /*isDef*/ true); + + // For the CALL instruction, the ret. addr. reg. is also implicit + if (isa(callee)) + mvec.back()->addImplicitRef(retAddrReg, /*isDef*/ true); + + // delay slot + mvec.push_back(new MachineInstr(NOP)); + break; + } + + case 62: // reg: Shl(reg, reg) { - // Check if the parent was an array access. - // If so, we still need to generate this instruction. - MemAccessInst* memInst =(MemAccessInst*) subtreeRoot->getInstruction(); - const PointerType* ptrType = - (const PointerType*) memInst->getPtrOperand()->getType(); - if (! ptrType->getValueType()->isArrayType()) - {// we don't need a separate instr - numInstr = 0; // don't forward operand! - break; - } + Value* argVal1 = subtreeRoot->leftChild()->getValue(); + Value* argVal2 = subtreeRoot->rightChild()->getValue(); + Instruction* shlInstr = subtreeRoot->getInstruction(); + + const Type* opType = argVal1->getType(); + assert((opType->isInteger() || isa(opType)) && + "Shl unsupported for other types"); + + CreateShiftInstructions(target, shlInstr->getParent()->getParent(), + (opType == Type::LongTy)? SLLX : SLL, + argVal1, argVal2, 0, shlInstr, mvec, + MachineCodeForInstruction::get(shlInstr)); + break; + } + + case 63: // reg: Shr(reg, reg) + { const Type* opType = subtreeRoot->leftChild()->getValue()->getType(); + assert((opType->isInteger() || isa(opType)) && + "Shr unsupported for other types"); + mvec.push_back(new MachineInstr((opType->isSigned() + ? ((opType == Type::LongTy)? SRAX : SRA) + : ((opType == Type::LongTy)? SRLX : SRL)))); + Set3OperandsFromInstr(mvec.back(), subtreeRoot, target); + break; } - // else in all other cases we need to a separate ADD instruction - mvec[0] = new MachineInstr(ADD); - SetOperandsForMemInstr(mvec[0], subtreeRoot, target); - break; - - case 57: // reg: Alloca: Implement as 2 instructions: - // sub %sp, tmp -> %sp - { // add %sp, 0 -> result - Instruction* instr = subtreeRoot->getInstruction(); - const PointerType* instrType = (const PointerType*) instr->getType(); - assert(instrType->isPointerType()); - int tsize = (int) target.findOptimalStorageSize(instrType->getValueType()); - assert(tsize != 0 && "Just to check when this can happen"); - // if (tsize == 0) - // { - // numInstr = 0; - // break; - // } - //else go on to create the instructions needed... - - // Create a temporary Value to hold the constant type-size - ConstPoolSInt* valueForTSize = ConstPoolSInt::get(Type::IntTy, tsize); - - // Instruction 1: sub %sp, tsize -> %sp - // tsize is always constant, but it may have to be put into a - // register if it doesn't fit in the immediate field. - // - mvec[0] = new MachineInstr(SUB); - mvec[0]->SetMachineOperand(0, /*regNum %sp = o6 = r[14]*/(unsigned int)14); - mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, valueForTSize); - mvec[0]->SetMachineOperand(2, /*regNum %sp = o6 = r[14]*/(unsigned int)14); - - // Instruction 2: add %sp, 0 -> result - numInstr++; - mvec[1] = new MachineInstr(ADD); - mvec[1]->SetMachineOperand(0, /*regNum %sp = o6 = r[14]*/(unsigned int)14); - mvec[1]->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0); - mvec[1]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, instr); - break; - } - - case 58: // reg: Alloca(reg): Implement as 3 instructions: - // mul num, typeSz -> tmp - // sub %sp, tmp -> %sp - { // add %sp, 0 -> result - Instruction* instr = subtreeRoot->getInstruction(); - const PointerType* instrType = (const PointerType*) instr->getType(); - assert(instrType->isPointerType() && - instrType->getValueType()->isArrayType()); - const Type* eltType = - ((ArrayType*) instrType->getValueType())->getElementType(); - int tsize = (int) target.findOptimalStorageSize(eltType); - - assert(tsize != 0 && "Just to check when this can happen"); - // if (tsize == 0) - // { - // numInstr = 0; - // break; - // } - //else go on to create the instructions needed... - - // Create a temporary Value to hold the constant type-size - ConstPoolSInt* valueForTSize = ConstPoolSInt::get(Type::IntTy, tsize); - - // Create a temporary value to hold `tmp' - Instruction* tmpInstr = new TmpInstruction(Instruction::UserOp1, - subtreeRoot->leftChild()->getValue(), - NULL /*could insert tsize here*/); - subtreeRoot->getInstruction()->getMachineInstrVec().addTempValue(tmpInstr); - - // Instruction 1: mul numElements, typeSize -> tmp - mvec[0] = new MachineInstr(MULX); - mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, - subtreeRoot->leftChild()->getValue()); - mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, valueForTSize); - mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,tmpInstr); - - tmpInstr->addMachineInstruction(mvec[0]); - - // Instruction 2: sub %sp, tmp -> %sp - numInstr++; - mvec[1] = new MachineInstr(SUB); - mvec[1]->SetMachineOperand(0, /*regNum %sp = o6 = r[14]*/(unsigned int)14); - mvec[1]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,tmpInstr); - mvec[1]->SetMachineOperand(2, /*regNum %sp = o6 = r[14]*/(unsigned int)14); - - // Instruction 3: add %sp, 0 -> result - numInstr++; - mvec[2] = new MachineInstr(ADD); - mvec[2]->SetMachineOperand(0, /*regNum %sp = o6 = r[14]*/(unsigned int)14); - mvec[2]->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0); - mvec[2]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, instr); - break; - } - - case 61: // reg: Call - // Generate a call-indirect (i.e., JMPL) for now to expose - // the potential need for registers. If an absolute address - // is available, replace this with a CALL instruction. - // Mark both the indirection register and the return-address - { // register as hidden virtual registers. - Instruction* jmpAddrReg = new TmpInstruction(Instruction::UserOp1, - ((CallInst*) subtreeRoot->getInstruction())->getCalledMethod(), NULL); - Instruction* retAddrReg = new TmpInstruction(Instruction::UserOp1, - subtreeRoot->getValue(), NULL); - subtreeRoot->getInstruction()->getMachineInstrVec().addTempValue(jmpAddrReg); - subtreeRoot->getInstruction()->getMachineInstrVec().addTempValue(retAddrReg); - - mvec[0] = new MachineInstr(JMPL); - mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, jmpAddrReg); - mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed, - (int64_t) 0); - mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, retAddrReg); - - // NOTE: jmpAddrReg will be loaded by a different instruction generated - // by the final code generator, so we just mark the CALL instruction - // as computing that value. - // The retAddrReg is actually computed by the CALL instruction. - // - jmpAddrReg->addMachineInstruction(mvec[0]); - retAddrReg->addMachineInstruction(mvec[0]); - - mvec[numInstr++] = new MachineInstr(NOP); // delay slot - break; + case 64: // reg: Phi(reg,reg) + break; // don't forward the value + + case 71: // reg: VReg + case 72: // reg: Constant + break; // don't forward the value + + default: + assert(0 && "Unrecognized BURG rule"); + break; + } } - - case 62: // reg: Shl(reg, reg) - opType = subtreeRoot->leftChild()->getValue()->getType(); - assert(opType->isIntegral() - || opType == Type::BoolTy - || opType->isPointerType() && "Shl unsupported for other types"); - mvec[0] = new MachineInstr((opType == Type::LongTy)? SLLX : SLL); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 63: // reg: Shr(reg, reg) - opType = subtreeRoot->leftChild()->getValue()->getType(); - assert(opType->isIntegral() - || opType == Type::BoolTy - || opType->isPointerType() && "Shr unsupported for other types"); - mvec[0] = new MachineInstr((opType->isSigned() - ? ((opType == Type::LongTy)? SRAX : SRA) - : ((opType == Type::LongTy)? SRLX : SRL))); - Set3OperandsFromInstr(mvec[0], subtreeRoot, target); - break; - - case 64: // reg: Phi(reg,reg) - { // This instruction has variable #operands, so resultPos is 0. - Instruction* phi = subtreeRoot->getInstruction(); - mvec[0] = new MachineInstr(PHI, 1 + phi->getNumOperands()); - mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, - subtreeRoot->getValue()); - for (unsigned i=0, N=phi->getNumOperands(); i < N; i++) - mvec[0]->SetMachineOperand(i+1, MachineOperand::MO_VirtualRegister, - phi->getOperand(i)); - break; - } - case 71: // reg: VReg - case 72: // reg: Constant - numInstr = 0; // don't forward the value - break; - - case 111: // stmt: reg - case 112: // stmt: boolconst - case 113: // stmt: bool - case 121: - case 122: - case 123: - case 124: - case 125: - case 126: - case 127: - case 128: - case 129: - case 130: - case 131: - case 132: - case 133: - case 153: - case 155: - case 221: - case 222: - case 232: - case 241: - case 242: - case 243: - case 244: - // - // These are all chain rules, which have a single nonterminal on the RHS. - // Get the rule that matches the RHS non-terminal and use that instead. - // - assert(ThisIsAChainRule(ruleForNode)); - assert(nts[0] && ! nts[1] - && "A chain rule should have only one RHS non-terminal!"); - nextRule = burm_rule(subtreeRoot->state, nts[0]); - nts = burm_nts[nextRule]; - numInstr = GetInstructionsByRule(subtreeRoot, nextRule, nts,target,mvec); - break; - - default: - assert(0 && "Unrecognized BURG rule"); - numInstr = 0; - break; - } - + if (forwardOperandNum >= 0) { // We did not generate a machine instruction but need to use operand. // If user is in the same tree, replace Value in its machine operand. // If not, insert a copy instruction which should get coalesced away // by register allocation. if (subtreeRoot->parent() != NULL) - ForwardOperand(subtreeRoot, subtreeRoot->parent(), forwardOperandNum); + ForwardOperand(subtreeRoot, subtreeRoot->parent(), forwardOperandNum); else - { - int n = numInstr++; - mvec[n] = new MachineInstr(ADD); - mvec[n]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, - subtreeRoot->getInstruction()->getOperand(forwardOperandNum)); - mvec[n]->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0); - mvec[n]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, - subtreeRoot->getInstruction()); - } + { + vector minstrVec; + Instruction* instr = subtreeRoot->getInstruction(); + target.getInstrInfo(). + CreateCopyInstructionsByType(target, + instr->getParent()->getParent(), + instr->getOperand(forwardOperandNum), + instr, minstrVec, + MachineCodeForInstruction::get(instr)); + assert(minstrVec.size() > 0); + mvec.insert(mvec.end(), minstrVec.begin(), minstrVec.end()); + } } - - if (! ThisIsAChainRule(ruleForNode)) - numInstr = FixConstantOperands(subtreeRoot, mvec, numInstr, target); - - return numInstr; -} - + if (maskUnsignedResult) + { // If result is unsigned and smaller than int reg size, + // we need to clear high bits of result value. + assert(forwardOperandNum < 0 && "Need mask but no instruction generated"); + Instruction* dest = subtreeRoot->getInstruction(); + if (dest->getType()->isUnsigned()) + { + unsigned destSize = target.DataLayout.getTypeSize(dest->getType()); + if (destSize <= 4) + { // Mask high bits. Use a TmpInstruction to represent the + // intermediate result before masking. Since those instructions + // have already been generated, go back and substitute tmpI + // for dest in the result position of each one of them. + TmpInstruction *tmpI = new TmpInstruction(dest->getType(), dest, + NULL, "maskHi"); + MachineCodeForInstruction::get(dest).addTemp(tmpI); + + for (unsigned i=0, N=mvec.size(); i < N; ++i) + mvec[i]->substituteValue(dest, tmpI); + + M = Create3OperandInstr_UImmed(SRL, tmpI, 8*(4-destSize), dest); + mvec.push_back(M); + } + else if (destSize < target.DataLayout.getIntegerRegize()) + assert(0 && "Unsupported type size: 32 < size < 64 bits"); + } + } +}