X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FSparcV9%2FSparcV9PrologEpilogInserter.cpp;h=1204dda85dd9a4adc9f402f63b2cca3b6e6d8927;hb=506d3dfa90cfee6ab4736a6a2c892e9059a7864d;hp=b74c7df344f3d1d9712ccb0bdcae5fa7e7ae7cde;hpb=bf3c4cfaad706db21ac82a4376e1899d0d7f0935;p=oota-llvm.git diff --git a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp index b74c7df344f..1204dda85dd 100644 --- a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp +++ b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp @@ -1,97 +1,107 @@ -//===-- PrologEpilogCodeInserter.cpp - Insert Prolog & Epilog code for fn -===// +//===-- SparcV9PrologEpilogCodeInserter.cpp - Insert Fn Prolog & Epilog ---===// // -// Insert SAVE/RESTORE instructions for the function +// The LLVM Compiler Infrastructure // -// Insert prolog code at the unique function entry point. -// Insert epilog code at each function exit point. -// InsertPrologEpilog invokes these only if the function is not compiled -// with the leaf function optimization. +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This is the SparcV9 target's own PrologEpilogInserter. It creates prolog and +// epilog instructions for functions which have not been compiled using "leaf +// function optimizations". These instructions include the SAVE and RESTORE +// instructions used to rotate the SPARC register windows. Prologs are +// attached to the unique function entry, and epilogs are attached to each +// function exit. // //===----------------------------------------------------------------------===// -#include "SparcInternals.h" -#include "SparcRegClassInfo.h" +#include "SparcV9Internals.h" +#include "SparcV9RegClassInfo.h" +#include "SparcV9RegisterInfo.h" +#include "SparcV9FrameInfo.h" +#include "MachineFunctionInfo.h" +#include "MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineFunctionInfo.h" -#include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/Pass.h" #include "llvm/Function.h" #include "llvm/DerivedTypes.h" #include "llvm/Intrinsics.h" +namespace llvm { + namespace { struct InsertPrologEpilogCode : public MachineFunctionPass { - const char *getPassName() const { return "Sparc Prolog/Epilog Inserter"; } - + const char *getPassName() const { return "SparcV9 Prolog/Epilog Inserter"; } + bool runOnMachineFunction(MachineFunction &F) { - if (!F.getInfo()->isCompiledAsLeafMethod()) { + if (!F.getInfo()->isCompiledAsLeafMethod()) { InsertPrologCode(F); InsertEpilogCode(F); } return false; } - + void InsertPrologCode(MachineFunction &F); void InsertEpilogCode(MachineFunction &F); }; } // End anonymous namespace -//------------------------------------------------------------------------ -// Create prolog and epilog code for procedure entry and exit -//------------------------------------------------------------------------ +static unsigned getStaticStackSize (MachineFunction &MF) { + const TargetFrameInfo& frameInfo = *MF.getTarget().getFrameInfo(); + unsigned staticStackSize = MF.getInfo()->getStaticStackSize(); + if (staticStackSize < (unsigned)SparcV9FrameInfo::MinStackFrameSize) + staticStackSize = SparcV9FrameInfo::MinStackFrameSize; + if (unsigned padsz = staticStackSize % + SparcV9FrameInfo::StackFrameSizeAlignment) + staticStackSize += SparcV9FrameInfo::StackFrameSizeAlignment - padsz; + return staticStackSize; +} void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF) { std::vector mvec; const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo& frameInfo = TM.getFrameInfo(); - + const TargetFrameInfo& frameInfo = *TM.getFrameInfo(); + // The second operand is the stack size. If it does not fit in the // immediate field, we have to use a free register to hold the size. // See the comments below for the choice of this register. - // - unsigned staticStackSize = MF.getInfo()->getStaticStackSize(); - - if (staticStackSize < (unsigned) frameInfo.getMinStackFrameSize()) - staticStackSize = (unsigned) frameInfo.getMinStackFrameSize(); - - if (unsigned padsz = (staticStackSize % - (unsigned) frameInfo.getStackFrameSizeAlignment())) - staticStackSize += frameInfo.getStackFrameSizeAlignment() - padsz; - + unsigned staticStackSize = getStaticStackSize (MF); int32_t C = - (int) staticStackSize; - int SP = TM.getRegInfo().getStackPointer(); - if (TM.getInstrInfo().constantFitsInImmedField(V9::SAVEi,staticStackSize)) { + int SP = TM.getRegInfo()->getStackPointer(); + if (TM.getInstrInfo()->constantFitsInImmedField(V9::SAVEi,staticStackSize)) { mvec.push_back(BuildMI(V9::SAVEi, 3).addMReg(SP).addSImm(C) - .addMReg(SP, MOTy::Def)); + .addMReg(SP, MachineOperand::Def)); } else { // We have to put the stack size value into a register before SAVE. // Use register %g1 since it is volatile across calls. Note that the // local (%l) and in (%i) registers cannot be used before the SAVE! // Do this by creating a code sequence equivalent to: // SETSW -(stackSize), %g1 - int uregNum = TM.getRegInfo().getUnifiedRegNum( - TM.getRegInfo().getRegClassIDOfType(Type::IntTy), - SparcIntRegClass::g1); + int uregNum = TM.getRegInfo()->getUnifiedRegNum( + TM.getRegInfo()->getRegClassIDOfType(Type::IntTy), + SparcV9IntRegClass::g1); MachineInstr* M = BuildMI(V9::SETHI, 2).addSImm(C) - .addMReg(uregNum, MOTy::Def); - M->setOperandHi32(0); + .addMReg(uregNum, MachineOperand::Def); + M->getOperand(0).markHi32(); mvec.push_back(M); - + M = BuildMI(V9::ORi, 3).addMReg(uregNum).addSImm(C) - .addMReg(uregNum, MOTy::Def); - M->setOperandLo32(1); + .addMReg(uregNum, MachineOperand::Def); + M->getOperand(1).markLo32(); mvec.push_back(M); - + M = BuildMI(V9::SRAi5, 3).addMReg(uregNum).addZImm(0) - .addMReg(uregNum, MOTy::Def); + .addMReg(uregNum, MachineOperand::Def); mvec.push_back(M); - + // Now generate the SAVE using the value in register %g1 - M = BuildMI(V9::SAVEr,3).addMReg(SP).addMReg(uregNum).addMReg(SP,MOTy::Def); + M = BuildMI(V9::SAVEr,3).addMReg(SP).addMReg(uregNum) + .addMReg(SP,MachineOperand::Def); mvec.push_back(M); } @@ -100,19 +110,18 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF) // The first K=6 arguments are always received via int arg regs // (%i0 ... %i5 if K=6) . // By copying the varargs arguments to the stack, va_arg() then can - // simply assume that all vararg arguments are in an array on the stack. - // + // simply assume that all vararg arguments are in an array on the stack. if (MF.getFunction()->getFunctionType()->isVarArg()) { int numFixedArgs = MF.getFunction()->getFunctionType()->getNumParams(); - int numArgRegs = TM.getRegInfo().getNumOfIntArgRegs(); + int numArgRegs = TM.getRegInfo()->getNumOfIntArgRegs(); if (numFixedArgs < numArgRegs) { - bool ignore; - int firstArgReg = TM.getRegInfo().getUnifiedRegNum( - TM.getRegInfo().getRegClassIDOfType(Type::IntTy), - SparcIntRegClass::i0); - int fpReg = TM.getFrameInfo().getIncomingArgBaseRegNum(); - int argSize = TM.getFrameInfo().getSizeOfEachArgOnStack(); - int firstArgOffset=TM.getFrameInfo().getFirstIncomingArgOffset(MF,ignore); + const TargetFrameInfo &FI = *TM.getFrameInfo(); + int firstArgReg = TM.getRegInfo()->getUnifiedRegNum( + TM.getRegInfo()->getRegClassIDOfType(Type::IntTy), + SparcV9IntRegClass::i0); + int fpReg = SparcV9::i6; + int argSize = 8; + int firstArgOffset= SparcV9FrameInfo::FirstIncomingArgOffsetFromFP; int nextArgOffset = firstArgOffset + numFixedArgs * argSize; for (int i=numFixedArgs; i < numArgRegs; ++i) { @@ -129,7 +138,7 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF) void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF) { const TargetMachine &TM = MF.getTarget(); - const TargetInstrInfo &MII = TM.getInstrInfo(); + const TargetInstrInfo &MII = *TM.getInstrInfo(); for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) { MachineBasicBlock &MBB = *I; @@ -137,36 +146,39 @@ void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF) const Instruction *TermInst = (Instruction*)BB.getTerminator(); if (TermInst->getOpcode() == Instruction::Ret) { - int ZR = TM.getRegInfo().getZeroRegNum(); - MachineInstr *Restore = - BuildMI(V9::RESTOREi, 3).addMReg(ZR).addSImm(0).addMReg(ZR, MOTy::Def); - + int ZR = TM.getRegInfo()->getZeroRegNum(); + MachineInstr *Restore = + BuildMI(V9::RESTOREi, 3).addMReg(ZR).addSImm(0) + .addMReg(ZR, MachineOperand::Def); + MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(TermInst); - + // Remove the NOPs in the delay slots of the return instruction unsigned numNOPs = 0; - while (termMvec.back()->getOpCode() == V9::NOP) + while (termMvec.back()->getOpcode() == V9::NOP) { - assert( termMvec.back() == MBB.back()); - delete MBB.pop_back(); + assert( termMvec.back() == &MBB.back()); termMvec.pop_back(); + MBB.erase(&MBB.back()); ++numNOPs; } - assert(termMvec.back() == MBB.back()); - + assert(termMvec.back() == &MBB.back()); + // Check that we found the right number of NOPs and have the right // number of instructions to replace them. - unsigned ndelays = MII.getNumDelaySlots(termMvec.back()->getOpCode()); + unsigned ndelays = MII.getNumDelaySlots(termMvec.back()->getOpcode()); assert(numNOPs == ndelays && "Missing NOPs in delay slots?"); assert(ndelays == 1 && "Cannot use epilog code for delay slots?"); - + // Append the epilog code to the end of the basic block. MBB.push_back(Restore); } } } -FunctionPass *UltraSparc::getPrologEpilogInsertionPass() { +FunctionPass *createPrologEpilogInsertionPass() { return new InsertPrologEpilogCode(); } + +} // End llvm namespace