X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FSparcV9%2FSparcV9RegInfo.cpp;h=d7b20c032f3a1e4821ca934e865eec3647624002;hb=edf3a727b7106cfa9f10aadd5e6f603bcc0b879f;hp=f55e56d1ac26ad6fccf72c6baadc51cfc54d6562;hpb=0c4e886dbf1cf7736819a49d5143ae1c2a0cfb79;p=oota-llvm.git diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp index f55e56d1ac2..d7b20c032f3 100644 --- a/lib/Target/SparcV9/SparcV9RegInfo.cpp +++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp @@ -26,7 +26,7 @@ using std::cerr; using std::vector; UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt) - : MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6), + : MachineRegInfo(tgt), NumOfIntArgRegs(6), NumOfFloatArgRegs(32), InvalidRegNum(1000) { MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID)); @@ -351,23 +351,21 @@ void UltraSparcRegInfo::suggestReg4RetAddr(MachineInstr *RetMI, // Suggests a register for the ret address in the JMPL/CALL machine instr. // Sparc ABI dictates that %o7 be used for this purpose. //--------------------------------------------------------------------------- -void UltraSparcRegInfo::suggestReg4CallAddr(MachineInstr * CallMI, - LiveRangeInfo& LRI, - std::vector RCList) const { +void +UltraSparcRegInfo::suggestReg4CallAddr(MachineInstr * CallMI, + LiveRangeInfo& LRI) const +{ CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI); const Value *RetAddrVal = argDesc->getReturnAddrReg(); - assert(RetAddrVal && "Return address value is required"); - - // create a new LR for the return address and color it - LiveRange * RetAddrLR = new LiveRange(); - RetAddrLR->insert( RetAddrVal ); - unsigned RegClassID = getRegClassIDOfValue( RetAddrVal ); - RetAddrLR->setRegClass( RCList[RegClassID] ); - RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID,SparcIntRegClass::o7)); - LRI.addLRToMap( RetAddrVal, RetAddrLR); - -} + assert(RetAddrVal && "INTERNAL ERROR: Return address value is required"); + + // A LR must already exist for the return address. + LiveRange *RetAddrLR = LRI.getLiveRangeForValue(RetAddrVal); + assert(RetAddrLR && "INTERNAL ERROR: No LR for return address of call!"); + unsigned RegClassID = RetAddrLR->getRegClass()->getID(); + RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID, SparcIntRegClass::o7)); +} @@ -565,39 +563,24 @@ void UltraSparcRegInfo::colorMethodArgs(const Function *Meth, // outgoing call args and the return value of the call. //--------------------------------------------------------------------------- void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI, - LiveRangeInfo& LRI, - std::vector RCList) const { - assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) ); + LiveRangeInfo& LRI) const { + assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) ); CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI); - suggestReg4CallAddr(CallMI, LRI, RCList); + suggestReg4CallAddr(CallMI, LRI); - // First color the return value of the call instruction. The return value - // will be in %o0 if the value is an integer type, or in %f0 if the - // value is a float type. - - // the return value cannot have a LR in machine instruction since it is - // only defined by the call instruction - - // if type is not void, create a new live range and set its - // register class and add to LRI + // First color the return value of the call instruction, if any. + // The return value will be in %o0 if the value is an integer type, + // or in %f0 if the value is a float type. + // + if (const Value *RetVal = argDesc->getReturnValue()) { + LiveRange *RetValLR = LRI.getLiveRangeForValue(RetVal); + assert(RetValLR && "No LR for return Value of call!"); - const Value *RetVal = argDesc->getReturnValue(); + unsigned RegClassID = RetValLR->getRegClass()->getID(); - if (RetVal) { - assert ((!LRI.getLiveRangeForValue(RetVal)) && - "LR for ret Value of call already definded!"); - - // create a new LR for the return value - LiveRange *RetValLR = new LiveRange(); - RetValLR->insert(RetVal); - unsigned RegClassID = getRegClassIDOfValue(RetVal); - RetValLR->setRegClass(RCList[RegClassID]); - LRI.addLRToMap(RetVal, RetValLR); - // now suggest a register depending on the register class of ret arg - if( RegClassID == IntRegClassID ) RetValLR->setSuggestedColor(SparcIntRegClass::o0); else if (RegClassID == FloatRegClassID ) @@ -605,7 +588,6 @@ void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI, else assert( 0 && "Unknown reg class for return value of call\n"); } - // Now suggest colors for arguments (operands) of the call instruction. // Colors are suggested only if the arg number is smaller than the // the number of registers allocated for argument passing. @@ -620,17 +602,12 @@ void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI, // get the LR of call operand (parameter) LiveRange *const LR = LRI.getLiveRangeForValue(CallArg); - - // not possible to have a null LR since all args (even consts) - // must be defined before - if (!LR) { - cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) << "\n"; - assert(0 && "NO LR for call arg"); - } - + assert (LR && "Must have a LR for all arguments since " + "all args (even consts) must be defined before"); + unsigned regType = getRegType( LR ); unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg (unused) - + // Choose a register for this arg depending on whether it is // an INT or FP value. Here we ignore whether or not it is a // varargs calls, because FP arguments will be explicitly copied @@ -773,7 +750,7 @@ void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI, PhyRegAlloc &PRA, const BasicBlock *BB) const { - assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) ); + assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) ); CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI); @@ -978,7 +955,7 @@ void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI, void UltraSparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI, LiveRangeInfo &LRI) const { - assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) ); + assert( (target.getInstrInfo()).isReturn( RetMI->getOpCode() ) ); suggestReg4RetAddr(RetMI, LRI); @@ -1016,7 +993,7 @@ void UltraSparcRegInfo::colorRetValue(MachineInstr *RetMI, LiveRangeInfo &LRI, AddedInstrns *RetAI) const { - assert((UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode())); + assert((target.getInstrInfo()).isReturn( RetMI->getOpCode())); // if there is an implicit ref, that has to be the ret value if(RetMI->getNumImplicitRefs() > 0) { @@ -1172,6 +1149,7 @@ UltraSparcRegInfo::cpReg2MemMI(vector& mvec, MachineInstr * MI = NULL; switch( RegType ) { case IntRegType: + assert(target.getInstrInfo().constantFitsInImmedField(STX, Offset)); MI = new MachineInstr(STX, 3); MI->SetMachineOperandReg(0, SrcReg, false); MI->SetMachineOperandReg(1, DestPtrReg, false); @@ -1181,6 +1159,7 @@ UltraSparcRegInfo::cpReg2MemMI(vector& mvec, break; case FPSingleRegType: + assert(target.getInstrInfo().constantFitsInImmedField(ST, Offset)); MI = new MachineInstr(ST, 3); MI->SetMachineOperandReg(0, SrcReg, false); MI->SetMachineOperandReg(1, DestPtrReg, false); @@ -1190,6 +1169,7 @@ UltraSparcRegInfo::cpReg2MemMI(vector& mvec, break; case FPDoubleRegType: + assert(target.getInstrInfo().constantFitsInImmedField(STD, Offset)); MI = new MachineInstr(STD, 3); MI->SetMachineOperandReg(0, SrcReg, false); MI->SetMachineOperandReg(1, DestPtrReg, false); @@ -1211,6 +1191,7 @@ UltraSparcRegInfo::cpReg2MemMI(vector& mvec, case FloatCCRegType: assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here"); + assert(target.getInstrInfo().constantFitsInImmedField(STXFSR, Offset)); MI = new MachineInstr(STXFSR, 3); MI->SetMachineOperandReg(0, SrcReg, false); MI->SetMachineOperandReg(1, DestPtrReg, false); @@ -1241,6 +1222,7 @@ UltraSparcRegInfo::cpMem2RegMI(vector& mvec, MachineInstr * MI = NULL; switch (RegType) { case IntRegType: + assert(target.getInstrInfo().constantFitsInImmedField(LDX, Offset)); MI = new MachineInstr(LDX, 3); MI->SetMachineOperandReg(0, SrcPtrReg, false); MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed, @@ -1250,6 +1232,7 @@ UltraSparcRegInfo::cpMem2RegMI(vector& mvec, break; case FPSingleRegType: + assert(target.getInstrInfo().constantFitsInImmedField(LD, Offset)); MI = new MachineInstr(LD, 3); MI->SetMachineOperandReg(0, SrcPtrReg, false); MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed, @@ -1259,6 +1242,7 @@ UltraSparcRegInfo::cpMem2RegMI(vector& mvec, break; case FPDoubleRegType: + assert(target.getInstrInfo().constantFitsInImmedField(LDD, Offset)); MI = new MachineInstr(LDD, 3); MI->SetMachineOperandReg(0, SrcPtrReg, false); MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed, @@ -1280,6 +1264,7 @@ UltraSparcRegInfo::cpMem2RegMI(vector& mvec, case FloatCCRegType: assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here"); + assert(target.getInstrInfo().constantFitsInImmedField(LDXFSR, Offset)); MI = new MachineInstr(LDXFSR, 3); MI->SetMachineOperandReg(0, SrcPtrReg, false); MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed, @@ -1365,7 +1350,7 @@ UltraSparcRegInfo::insertCallerSavingCode(vector& instrnsBefore, const BasicBlock *BB, PhyRegAlloc &PRA) const { - assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) ); + assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) ); // has set to record which registers were saved/restored // @@ -1748,9 +1733,8 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector &OrdVec, cpMem2RegMI(OrdVec, getFramePointer(), StackOff, DReg, RegType); - cerr << "\nFixed CIRCULAR references by reordering"; - if( DEBUG_RA ) { + cerr << "\nFixed CIRCULAR references by reordering:"; cerr << "\nBefore CIRCULAR Reordering:\n"; cerr << *UnordInst; cerr << *OrdInst;