X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FSparcV9%2FSparcV9RegInfo.cpp;h=f6ad9c69387ca1a5f97d5854e517242bf7600d97;hb=a2bae305fb5a870c4ef753ed290a7ddea73ec82b;hp=c321adc25fb6f25fa1b63c9133603e0ac4ed26d2;hpb=09ff1126dab045d68be7d9e8ae7ad0601002a718;p=oota-llvm.git diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp index c321adc25fb..f6ad9c69387 100644 --- a/lib/Target/SparcV9/SparcV9RegInfo.cpp +++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp @@ -8,7 +8,7 @@ #include "SparcInternals.h" #include "SparcRegClassInfo.h" #include "llvm/Target/Sparc.h" -#include "llvm/CodeGen/MachineCodeForMethod.h" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/PhyRegAlloc.h" #include "llvm/CodeGen/InstrSelection.h" #include "llvm/CodeGen/InstrSelectionSupport.h" @@ -26,7 +26,7 @@ using std::cerr; using std::vector; UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt) - : MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6), + : MachineRegInfo(tgt), NumOfIntArgRegs(6), NumOfFloatArgRegs(32), InvalidRegNum(1000) { MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID)); @@ -34,7 +34,7 @@ UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt) MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID)); MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID)); - assert(SparcFloatRegOrder::StartOfNonVolatileRegs == 32 && + assert(SparcFloatRegClass::StartOfNonVolatileRegs == 32 && "32 Float regs are used for float arg passing"); } @@ -43,16 +43,16 @@ UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt) // this is the unified register number // int UltraSparcRegInfo::getZeroRegNum() const { - return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, - SparcIntRegOrder::g0); + return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, + SparcIntRegClass::g0); } // getCallAddressReg - returns the reg used for pushing the address when a // method is called. This can be used for other purposes between calls // unsigned UltraSparcRegInfo::getCallAddressReg() const { - return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, - SparcIntRegOrder::o7); + return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, + SparcIntRegClass::o7); } // Returns the register containing the return address. @@ -60,22 +60,73 @@ unsigned UltraSparcRegInfo::getCallAddressReg() const { // value when a return instruction is reached. // unsigned UltraSparcRegInfo::getReturnAddressReg() const { - return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, - SparcIntRegOrder::i7); + return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, + SparcIntRegClass::i7); +} + +// Register get name implementations... + +// Int register names in same order as enum in class SparcIntRegClass +static const char * const IntRegNames[] = { + "o0", "o1", "o2", "o3", "o4", "o5", "o7", + "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", + "i0", "i1", "i2", "i3", "i4", "i5", + "i6", "i7", + "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", + "o6" +}; + +const char * const SparcIntRegClass::getRegName(unsigned reg) { + assert(reg < NumOfAllRegs); + return IntRegNames[reg]; +} + +static const char * const FloatRegNames[] = { + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", + "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", + "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", + "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", + "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", + "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", + "f60", "f61", "f62", "f63" +}; + +const char * const SparcFloatRegClass::getRegName(unsigned reg) { + assert (reg < NumOfAllRegs); + return FloatRegNames[reg]; +} + + +static const char * const IntCCRegNames[] = { + "xcc", "ccr" +}; + +const char * const SparcIntCCRegClass::getRegName(unsigned reg) { + assert(reg < 2); + return IntCCRegNames[reg]; +} + +static const char * const FloatCCRegNames[] = { + "fcc0", "fcc1", "fcc2", "fcc3" +}; + +const char * const SparcFloatCCRegClass::getRegName(unsigned reg) { + assert (reg < 4); + return FloatCCRegNames[reg]; } // given the unified register number, this gives the name // for generating assembly code or debugging. // -const std::string UltraSparcRegInfo::getUnifiedRegName(int reg) const { +const char * const UltraSparcRegInfo::getUnifiedRegName(int reg) const { if( reg < 32 ) - return SparcIntRegOrder::getRegName(reg); + return SparcIntRegClass::getRegName(reg); else if ( reg < (64 + 32) ) - return SparcFloatRegOrder::getRegName( reg - 32); + return SparcFloatRegClass::getRegName( reg - 32); else if( reg < (64+32+4) ) - return SparcFloatCCRegOrder::getRegName( reg -32 - 64); + return SparcFloatCCRegClass::getRegName( reg -32 - 64); else if( reg < (64+32+4+2) ) // two names: %xcc and %ccr - return SparcIntCCRegOrder::getRegName( reg -32 - 64 - 4); + return SparcIntCCRegClass::getRegName( reg -32 - 64 - 4); else if (reg== InvalidRegNum) //****** TODO: Remove */ return "<*NoReg*>"; else @@ -85,14 +136,14 @@ const std::string UltraSparcRegInfo::getUnifiedRegName(int reg) const { // Get unified reg number for frame pointer unsigned UltraSparcRegInfo::getFramePointer() const { - return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, - SparcIntRegOrder::i6); + return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, + SparcIntRegClass::i6); } // Get unified reg number for stack pointer unsigned UltraSparcRegInfo::getStackPointer() const { - return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, - SparcIntRegOrder::o6); + return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, + SparcIntRegClass::o6); } @@ -135,7 +186,7 @@ UltraSparcRegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall, if (argNo >= NumOfIntArgRegs) return InvalidRegNum; else - return argNo + (inCallee? SparcIntRegOrder::i0 : SparcIntRegOrder::o0); + return argNo + (inCallee? SparcIntRegClass::i0 : SparcIntRegClass::o0); } // Get the register number for the specified FP arg#, @@ -162,12 +213,13 @@ UltraSparcRegInfo::regNumForFPArg(unsigned regType, regClassId = FloatRegClassID; if (regType == FPSingleRegType) return (argNo*2+1 >= NumOfFloatArgRegs)? - InvalidRegNum : SparcFloatRegOrder::f0 + (argNo * 2 + 1); + InvalidRegNum : SparcFloatRegClass::f0 + (argNo * 2 + 1); else if (regType == FPDoubleRegType) return (argNo*2 >= NumOfFloatArgRegs)? - InvalidRegNum : SparcFloatRegOrder::f0 + (argNo * 2); + InvalidRegNum : SparcFloatRegClass::f0 + (argNo * 2); else assert(0 && "Illegal FP register type"); + return 0; } } @@ -224,7 +276,7 @@ int UltraSparcRegInfo::getRegType(int unifiedRegNum) const { // To find the register class used for a specified Type // unsigned UltraSparcRegInfo::getRegClassIDOfType(const Type *type, - bool isCCReg = false) const { + bool isCCReg) const { Type::PrimitiveID ty = type->getPrimitiveID(); unsigned res; @@ -278,7 +330,7 @@ void UltraSparcRegInfo::suggestReg4RetAddr(MachineInstr *RetMI, // return address is always mapped to i7 so set it immediately RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID, - SparcIntRegOrder::i7)); + SparcIntRegClass::i7)); // Possible Optimization: // Instead of setting the color, we can suggest one. In that case, @@ -299,23 +351,21 @@ void UltraSparcRegInfo::suggestReg4RetAddr(MachineInstr *RetMI, // Suggests a register for the ret address in the JMPL/CALL machine instr. // Sparc ABI dictates that %o7 be used for this purpose. //--------------------------------------------------------------------------- -void UltraSparcRegInfo::suggestReg4CallAddr(MachineInstr * CallMI, - LiveRangeInfo& LRI, - std::vector RCList) const { +void +UltraSparcRegInfo::suggestReg4CallAddr(MachineInstr * CallMI, + LiveRangeInfo& LRI) const +{ CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI); const Value *RetAddrVal = argDesc->getReturnAddrReg(); - assert(RetAddrVal && "Return address value is required"); - - // create a new LR for the return address and color it - LiveRange * RetAddrLR = new LiveRange(); - RetAddrLR->insert( RetAddrVal ); - unsigned RegClassID = getRegClassIDOfValue( RetAddrVal ); - RetAddrLR->setRegClass( RCList[RegClassID] ); - RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o7)); - LRI.addLRToMap( RetAddrVal, RetAddrLR); - -} + assert(RetAddrVal && "INTERNAL ERROR: Return address value is required"); + + // A LR must already exist for the return address. + LiveRange *RetAddrLR = LRI.getLiveRangeForValue(RetAddrVal); + assert(RetAddrLR && "INTERNAL ERROR: No LR for return address of call!"); + unsigned RegClassID = RetAddrLR->getRegClass()->getID(); + RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID, SparcIntRegClass::o7)); +} @@ -427,7 +477,7 @@ void UltraSparcRegInfo::colorMethodArgs(const Function *Meth, regClassIDOfArgReg == IntRegClassID && "This should only be an Int register for an FP argument"); - int TmpOff = MachineCodeForMethod::get(Meth).pushTempValue(target, + int TmpOff = MachineFunction::get(Meth).pushTempValue(target, getSpilledRegSize(regType)); cpReg2MemMI(FirstAI->InstrnsBefore, UniArgReg, getFramePointer(), TmpOff, IntRegType); @@ -446,7 +496,7 @@ void UltraSparcRegInfo::colorMethodArgs(const Function *Meth, // const MachineFrameInfo& frameInfo = target.getFrameInfo(); int offsetFromFP = - frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth), + frameInfo.getIncomingArgOffset(MachineFunction::get(Meth), argNo); cpMem2RegMI(FirstAI->InstrnsBefore, @@ -494,7 +544,7 @@ void UltraSparcRegInfo::colorMethodArgs(const Function *Meth, const MachineFrameInfo& frameInfo = target.getFrameInfo(); int offsetFromFP = - frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth), + frameInfo.getIncomingArgOffset(MachineFunction::get(Meth), argNo); LR->modifySpillOffFromFP( offsetFromFP ); @@ -513,47 +563,31 @@ void UltraSparcRegInfo::colorMethodArgs(const Function *Meth, // outgoing call args and the return value of the call. //--------------------------------------------------------------------------- void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI, - LiveRangeInfo& LRI, - std::vector RCList) const { - assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) ); + LiveRangeInfo& LRI) const { + assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) ); CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI); - suggestReg4CallAddr(CallMI, LRI, RCList); - - // First color the return value of the call instruction. The return value - // will be in %o0 if the value is an integer type, or in %f0 if the - // value is a float type. - - // the return value cannot have a LR in machine instruction since it is - // only defined by the call instruction + suggestReg4CallAddr(CallMI, LRI); - // if type is not void, create a new live range and set its - // register class and add to LRI + // First color the return value of the call instruction, if any. + // The return value will be in %o0 if the value is an integer type, + // or in %f0 if the value is a float type. + // + if (const Value *RetVal = argDesc->getReturnValue()) { + LiveRange *RetValLR = LRI.getLiveRangeForValue(RetVal); + assert(RetValLR && "No LR for return Value of call!"); - const Value *RetVal = argDesc->getReturnValue(); + unsigned RegClassID = RetValLR->getRegClass()->getID(); - if (RetVal) { - assert ((!LRI.getLiveRangeForValue(RetVal)) && - "LR for ret Value of call already definded!"); - - // create a new LR for the return value - LiveRange *RetValLR = new LiveRange(); - RetValLR->insert(RetVal); - unsigned RegClassID = getRegClassIDOfValue(RetVal); - RetValLR->setRegClass(RCList[RegClassID]); - LRI.addLRToMap(RetVal, RetValLR); - // now suggest a register depending on the register class of ret arg - if( RegClassID == IntRegClassID ) - RetValLR->setSuggestedColor(SparcIntRegOrder::o0); + RetValLR->setSuggestedColor(SparcIntRegClass::o0); else if (RegClassID == FloatRegClassID ) - RetValLR->setSuggestedColor(SparcFloatRegOrder::f0 ); + RetValLR->setSuggestedColor(SparcFloatRegClass::f0 ); else assert( 0 && "Unknown reg class for return value of call\n"); } - // Now suggest colors for arguments (operands) of the call instruction. // Colors are suggested only if the arg number is smaller than the // the number of registers allocated for argument passing. @@ -568,17 +602,12 @@ void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI, // get the LR of call operand (parameter) LiveRange *const LR = LRI.getLiveRangeForValue(CallArg); - - // not possible to have a null LR since all args (even consts) - // must be defined before - if (!LR) { - cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) << "\n"; - assert(0 && "NO LR for call arg"); - } - + assert (LR && "Must have a LR for all arguments since " + "all args (even consts) must be defined before"); + unsigned regType = getRegType( LR ); unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg (unused) - + // Choose a register for this arg depending on whether it is // an INT or FP value. Here we ignore whether or not it is a // varargs calls, because FP arguments will be explicitly copied @@ -599,7 +628,7 @@ void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI, const Value *argCopy = argDesc->getArgInfo(i).getArgCopy(); if (argCopy != NULL) { - assert(regType != IntRegType && argCopy->getType()->isIntegral() + assert(regType != IntRegType && argCopy->getType()->isInteger() && "Must be passing copy of FP argument in int register"); int copyRegNum = regNumForIntArg(/*inCallee*/false, /*isVarArgs*/false, argNo, intArgNo, fpArgNo-1, @@ -634,7 +663,7 @@ UltraSparcRegInfo::InitializeOutgoingArg(MachineInstr* CallMI, { isArgInReg = true; UniArgReg = (unsigned) UniArgRegOrNone; - CallMI->getRegsUsed().insert(UniArgReg); // mark the reg as used + CallMI->insertUsedReg(UniArgReg); // mark the reg as used } if (LR->hasColor()) { @@ -654,7 +683,7 @@ UltraSparcRegInfo::InitializeOutgoingArg(MachineInstr* CallMI, else { // Copy UniLRReg to the stack to pass the arg on stack. const MachineFrameInfo& frameInfo = target.getFrameInfo(); - int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo); + int argOffset = frameInfo.getOutgoingArgOffset(PRA.MF, argNo); cpReg2MemMI(CallAI->InstrnsBefore, UniLRReg, getStackPointer(), argOffset, regType); } @@ -676,10 +705,10 @@ UltraSparcRegInfo::InitializeOutgoingArg(MachineInstr* CallMI, // Use TmpOff to save TReg, since that may have a live value. // int TReg = PRA.getUniRegNotUsedByThisInst( LR->getRegClass(), CallMI ); - int TmpOff = PRA.mcInfo.pushTempValue(target, - getSpilledRegSize(getRegType(LR))); + int TmpOff = PRA.MF.pushTempValue(target, + getSpilledRegSize(getRegType(LR))); const MachineFrameInfo& frameInfo = target.getFrameInfo(); - int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo); + int argOffset = frameInfo.getOutgoingArgOffset(PRA.MF, argNo); MachineInstr *Ad1, *Ad2, *Ad3, *Ad4; @@ -721,7 +750,7 @@ void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI, PhyRegAlloc &PRA, const BasicBlock *BB) const { - assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) ); + assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) ); CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI); @@ -747,19 +776,19 @@ void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI, unsigned UniRetReg; // unified number for CorrectCol if(RegClassID == IntRegClassID) - CorrectCol = SparcIntRegOrder::o0; + CorrectCol = SparcIntRegClass::o0; else if(RegClassID == FloatRegClassID) - CorrectCol = SparcFloatRegOrder::f0; + CorrectCol = SparcFloatRegClass::f0; else { assert( 0 && "Unknown RegClass"); return; } // convert to unified number - UniRetReg = this->getUnifiedRegNum( RegClassID, CorrectCol); + UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol); // Mark the register as used by this instruction - CallMI->getRegsUsed().insert(UniRetReg); + CallMI->insertUsedReg(UniRetReg); // if the LR received the correct color, NOTHING to do recvCorrectColor = RetValLR->hasColor()? RetValLR->getColor() == CorrectCol @@ -855,7 +884,7 @@ void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI, const Value *argCopy = argDesc->getArgInfo(i).getArgCopy(); if (argCopy != NULL) { - assert(regType != IntRegType && argCopy->getType()->isIntegral() + assert(regType != IntRegType && argCopy->getType()->isInteger() && "Must be passing copy of FP argument in int register"); unsigned copyRegClassID = getRegClassIDOfValue(argCopy); @@ -926,7 +955,7 @@ void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI, void UltraSparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI, LiveRangeInfo &LRI) const { - assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) ); + assert( (target.getInstrInfo()).isReturn( RetMI->getOpCode() ) ); suggestReg4RetAddr(RetMI, LRI); @@ -946,9 +975,9 @@ void UltraSparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI, unsigned RegClassID = (LR->getRegClass())->getID(); if (RegClassID == IntRegClassID) - LR->setSuggestedColor(SparcIntRegOrder::i0); + LR->setSuggestedColor(SparcIntRegClass::i0); else if (RegClassID == FloatRegClassID) - LR->setSuggestedColor(SparcFloatRegOrder::f0); + LR->setSuggestedColor(SparcFloatRegClass::f0); } } @@ -964,7 +993,7 @@ void UltraSparcRegInfo::colorRetValue(MachineInstr *RetMI, LiveRangeInfo &LRI, AddedInstrns *RetAI) const { - assert((UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode())); + assert((target.getInstrInfo()).isReturn( RetMI->getOpCode())); // if there is an implicit ref, that has to be the ret value if(RetMI->getNumImplicitRefs() > 0) { @@ -985,19 +1014,19 @@ void UltraSparcRegInfo::colorRetValue(MachineInstr *RetMI, unsigned CorrectCol; if(RegClassID == IntRegClassID) - CorrectCol = SparcIntRegOrder::i0; + CorrectCol = SparcIntRegClass::i0; else if(RegClassID == FloatRegClassID) - CorrectCol = SparcFloatRegOrder::f0; + CorrectCol = SparcFloatRegClass::f0; else { assert (0 && "Unknown RegClass"); return; } // convert to unified number - unsigned UniRetReg = this->getUnifiedRegNum(RegClassID, CorrectCol); + unsigned UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol); // Mark the register as used by this instruction - RetMI->getRegsUsed().insert(UniRetReg); + RetMI->insertUsedReg(UniRetReg); // if the LR received the correct color, NOTHING to do @@ -1066,7 +1095,7 @@ UltraSparcRegInfo::cpReg2RegMI(vector& mvec, switch( RegType ) { case IntCCRegType: - if (this->getRegType(DestReg) == IntRegType) + if (getRegType(DestReg) == IntRegType) { // copy intCC reg to int reg // Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR MI = Create2OperandInstr_Reg(RDCCR, SrcReg+1, DestReg); @@ -1074,7 +1103,7 @@ UltraSparcRegInfo::cpReg2RegMI(vector& mvec, else { // copy int reg to intCC reg // Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR - assert(this->getRegType(SrcReg) == IntRegType + assert(getRegType(SrcReg) == IntRegType && "Can only copy CC reg to/from integer reg"); MI = Create2OperandInstr_Reg(WRCCR, SrcReg, DestReg+1); } @@ -1085,7 +1114,7 @@ UltraSparcRegInfo::cpReg2RegMI(vector& mvec, break; case IntRegType: - MI = Create3OperandInstr_Reg(ADD, SrcReg, this->getZeroRegNum(), DestReg); + MI = Create3OperandInstr_Reg(ADD, SrcReg, getZeroRegNum(), DestReg); break; case FPSingleRegType: @@ -1116,31 +1145,34 @@ UltraSparcRegInfo::cpReg2MemMI(vector& mvec, unsigned SrcReg, unsigned DestPtrReg, int Offset, int RegType, - int scratchReg = -1) const { + int scratchReg) const { MachineInstr * MI = NULL; switch( RegType ) { case IntRegType: + assert(target.getInstrInfo().constantFitsInImmedField(STX, Offset)); MI = new MachineInstr(STX, 3); - MI->SetMachineOperandReg(0, SrcReg, false); - MI->SetMachineOperandReg(1, DestPtrReg, false); + MI->SetMachineOperandReg(0, SrcReg); + MI->SetMachineOperandReg(1, DestPtrReg); MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed, (int64_t) Offset); mvec.push_back(MI); break; case FPSingleRegType: + assert(target.getInstrInfo().constantFitsInImmedField(ST, Offset)); MI = new MachineInstr(ST, 3); - MI->SetMachineOperandReg(0, SrcReg, false); - MI->SetMachineOperandReg(1, DestPtrReg, false); + MI->SetMachineOperandReg(0, SrcReg); + MI->SetMachineOperandReg(1, DestPtrReg); MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed, (int64_t) Offset); mvec.push_back(MI); break; case FPDoubleRegType: + assert(target.getInstrInfo().constantFitsInImmedField(STD, Offset)); MI = new MachineInstr(STD, 3); - MI->SetMachineOperandReg(0, SrcReg, false); - MI->SetMachineOperandReg(1, DestPtrReg, false); + MI->SetMachineOperandReg(0, SrcReg); + MI->SetMachineOperandReg(1, DestPtrReg); MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed, (int64_t) Offset); mvec.push_back(MI); @@ -1148,20 +1180,21 @@ UltraSparcRegInfo::cpReg2MemMI(vector& mvec, case IntCCRegType: assert(scratchReg >= 0 && "Need scratch reg to store %ccr to memory"); - assert(this->getRegType(scratchReg) ==IntRegType && "Invalid scratch reg"); + assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg"); // Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR MI = Create2OperandInstr_Reg(RDCCR, SrcReg+1, scratchReg); mvec.push_back(MI); - this->cpReg2MemMI(mvec, scratchReg, DestPtrReg, Offset, IntRegType); + cpReg2MemMI(mvec, scratchReg, DestPtrReg, Offset, IntRegType); break; case FloatCCRegType: assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here"); + assert(target.getInstrInfo().constantFitsInImmedField(STXFSR, Offset)); MI = new MachineInstr(STXFSR, 3); - MI->SetMachineOperandReg(0, SrcReg, false); - MI->SetMachineOperandReg(1, DestPtrReg, false); + MI->SetMachineOperandReg(0, SrcReg); + MI->SetMachineOperandReg(1, DestPtrReg); MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed, (int64_t) Offset); mvec.push_back(MI); @@ -1185,12 +1218,13 @@ UltraSparcRegInfo::cpMem2RegMI(vector& mvec, int Offset, unsigned DestReg, int RegType, - int scratchReg = -1) const { + int scratchReg) const { MachineInstr * MI = NULL; switch (RegType) { case IntRegType: + assert(target.getInstrInfo().constantFitsInImmedField(LDX, Offset)); MI = new MachineInstr(LDX, 3); - MI->SetMachineOperandReg(0, SrcPtrReg, false); + MI->SetMachineOperandReg(0, SrcPtrReg); MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed, (int64_t) Offset); MI->SetMachineOperandReg(2, DestReg, true); @@ -1198,8 +1232,9 @@ UltraSparcRegInfo::cpMem2RegMI(vector& mvec, break; case FPSingleRegType: + assert(target.getInstrInfo().constantFitsInImmedField(LD, Offset)); MI = new MachineInstr(LD, 3); - MI->SetMachineOperandReg(0, SrcPtrReg, false); + MI->SetMachineOperandReg(0, SrcPtrReg); MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed, (int64_t) Offset); MI->SetMachineOperandReg(2, DestReg, true); @@ -1207,8 +1242,9 @@ UltraSparcRegInfo::cpMem2RegMI(vector& mvec, break; case FPDoubleRegType: + assert(target.getInstrInfo().constantFitsInImmedField(LDD, Offset)); MI = new MachineInstr(LDD, 3); - MI->SetMachineOperandReg(0, SrcPtrReg, false); + MI->SetMachineOperandReg(0, SrcPtrReg); MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed, (int64_t) Offset); MI->SetMachineOperandReg(2, DestReg, true); @@ -1217,8 +1253,8 @@ UltraSparcRegInfo::cpMem2RegMI(vector& mvec, case IntCCRegType: assert(scratchReg >= 0 && "Need scratch reg to load %ccr from memory"); - assert(this->getRegType(scratchReg) ==IntRegType && "Invalid scratch reg"); - this->cpMem2RegMI(mvec, SrcPtrReg, Offset, scratchReg, IntRegType); + assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg"); + cpMem2RegMI(mvec, SrcPtrReg, Offset, scratchReg, IntRegType); // Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR MI = Create2OperandInstr_Reg(WRCCR, scratchReg, DestReg+1); @@ -1228,8 +1264,9 @@ UltraSparcRegInfo::cpMem2RegMI(vector& mvec, case FloatCCRegType: assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here"); + assert(target.getInstrInfo().constantFitsInImmedField(LDXFSR, Offset)); MI = new MachineInstr(LDXFSR, 3); - MI->SetMachineOperandReg(0, SrcPtrReg, false); + MI->SetMachineOperandReg(0, SrcPtrReg); MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed, (int64_t) Offset); MI->SetMachineOperandReg(2, DestReg, true); @@ -1261,30 +1298,29 @@ UltraSparcRegInfo::cpValue2Value(Value *Src, switch( RegType ) { case IntRegType: MI = new MachineInstr(ADD, 3); - MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false); - MI->SetMachineOperandReg(1, this->getZeroRegNum(), false); - MI->SetMachineOperandVal(2, MachineOperand:: MO_VirtualRegister, Dest, true); + MI->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, Src); + MI->SetMachineOperandReg(1, getZeroRegNum()); + MI->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, Dest, true); break; case FPSingleRegType: MI = new MachineInstr(FMOVS, 2); - MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false); - MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true); + MI->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, Src); + MI->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, Dest, true); break; case FPDoubleRegType: MI = new MachineInstr(FMOVD, 2); - MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false); - MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true); + MI->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, Src); + MI->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, Dest, true); break; default: assert(0 && "Unknow RegType in CpValu2Value"); } - if (MI) - mvec.push_back(MI); + mvec.push_back(MI); } @@ -1313,7 +1349,7 @@ UltraSparcRegInfo::insertCallerSavingCode(vector& instrnsBefore, const BasicBlock *BB, PhyRegAlloc &PRA) const { - assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) ); + assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) ); // has set to record which registers were saved/restored // @@ -1376,8 +1412,8 @@ UltraSparcRegInfo::insertCallerSavingCode(vector& instrnsBefore, // and add them to InstrnsBefore and InstrnsAfter of the // call instruction // - int StackOff = PRA.mcInfo.pushTempValue(target, - getSpilledRegSize(RegType)); + int StackOff = PRA.MF.pushTempValue(target, + getSpilledRegSize(RegType)); vector AdIBef, AdIAft; @@ -1389,14 +1425,14 @@ UltraSparcRegInfo::insertCallerSavingCode(vector& instrnsBefore, // the save code. int scratchRegType = -1; int scratchReg = -1; - if (this->regTypeNeedsScratchReg(RegType, scratchRegType)) + if (regTypeNeedsScratchReg(RegType, scratchRegType)) { // Find a register not live in the LVSet before CallMI const ValueSet &LVSetBef = PRA.LVI->getLiveVarSetBeforeMInst(CallMI, BB); scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetBef, CallMI, AdIBef, AdIAft); - assert(scratchReg != this->getInvalidRegNum()); - CallMI->getRegsUsed().insert(scratchReg); + assert(scratchReg != getInvalidRegNum()); + CallMI->insertUsedReg(scratchReg); } if (AdIBef.size() > 0) @@ -1419,12 +1455,12 @@ UltraSparcRegInfo::insertCallerSavingCode(vector& instrnsBefore, // scratchRegType = -1; scratchReg = -1; - if (this->regTypeNeedsScratchReg(RegType, scratchRegType)) + if (regTypeNeedsScratchReg(RegType, scratchRegType)) { // Find a register not live in the LVSet after CallMI scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetAft, CallMI, AdIBef, AdIAft); - assert(scratchReg != this->getInvalidRegNum()); - CallMI->getRegsUsed().insert(scratchReg); + assert(scratchReg != getInvalidRegNum()); + CallMI->insertUsedReg(scratchReg); } if (AdIBef.size() > 0) @@ -1479,12 +1515,12 @@ void UltraSparcRegInfo::printReg(const LiveRange *LR) { cerr << " colored with color "<< LR->getColor(); if (RegClassID == IntRegClassID) { - cerr<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) << "]\n"; + cerr<< " [" << SparcIntRegClass::getRegName(LR->getColor()) << "]\n"; } else if (RegClassID == FloatRegClassID) { - cerr << "[" << SparcFloatRegOrder::getRegName(LR->getColor()); + cerr << "[" << SparcFloatRegClass::getRegName(LR->getColor()); if( LR->getType() == Type::DoubleTy) - cerr << "+" << SparcFloatRegOrder::getRegName(LR->getColor()+1); + cerr << "+" << SparcFloatRegClass::getRegName(LR->getColor()+1); cerr << "]\n"; } } @@ -1562,11 +1598,10 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector &UnordVec, // last operand is the def (unless for a store which has no def reg) MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1); - if( DefOp.opIsDef() && - DefOp.getOperandType() == MachineOperand::MO_MachineRegister) { + if (DefOp.opIsDef() && + DefOp.getType() == MachineOperand::MO_MachineRegister) { // If the operand in DefInst is a def ... - bool DefEqUse = false; std::vector::iterator UseIt = DefIt; @@ -1580,8 +1615,8 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector &UnordVec, // for each inst (UseInst) that is below the DefInst do ... MachineOperand& UseOp = UseInst->getOperand(0); - if( ! UseOp.opIsDef() && - UseOp.getOperandType() == MachineOperand::MO_MachineRegister) { + if (!UseOp.opIsDef() && + UseOp.getType() == MachineOperand::MO_MachineRegister) { // if use is a register ... @@ -1641,8 +1676,8 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector &OrdVec, PhyRegAlloc &PRA) const { MachineOperand& UseOp = UnordInst->getOperand(0); - if( ! UseOp.opIsDef() && - UseOp.getOperandType() == MachineOperand::MO_MachineRegister) { + if (!UseOp.opIsDef() && + UseOp.getType() == MachineOperand::MO_MachineRegister) { // for the use of UnordInst, see whether there is a defining instr // before in the OrdVec @@ -1658,7 +1693,7 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector &OrdVec, OrdInst->getOperand(OrdInst->getNumOperands()-1); if( DefOp.opIsDef() && - DefOp.getOperandType() == MachineOperand::MO_MachineRegister) { + DefOp.getType() == MachineOperand::MO_MachineRegister) { //cerr << "\nDefining Ord Inst: " << *OrdInst; @@ -1673,12 +1708,12 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector &OrdVec, // Now we are processing %ox of 1. // We have to - const int UReg = DefOp.getMachineRegNum(); - const int RegType = getRegType(UReg); + int UReg = DefOp.getMachineRegNum(); + int RegType = getRegType(UReg); MachineInstr *AdIBef, *AdIAft; - const int StackOff = PRA.mcInfo.pushTempValue(target, - getSpilledRegSize(RegType)); + const int StackOff = PRA.MF.pushTempValue(target, + getSpilledRegSize(RegType)); // Save the UReg (%ox) on stack before it's destroyed vector mvec; @@ -1696,9 +1731,8 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector &OrdVec, cpMem2RegMI(OrdVec, getFramePointer(), StackOff, DReg, RegType); - cerr << "\nFixed CIRCULAR references by reordering"; - if( DEBUG_RA ) { + cerr << "\nFixed CIRCULAR references by reordering:"; cerr << "\nBefore CIRCULAR Reordering:\n"; cerr << *UnordInst; cerr << *OrdInst;