X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FSparcV9%2FSparcV9RegInfo.cpp;h=f6ad9c69387ca1a5f97d5854e517242bf7600d97;hb=a2bae305fb5a870c4ef753ed290a7ddea73ec82b;hp=d06bba6f3a9b032231dec53ce369402d05588b52;hpb=87817653feb2c38656ad7b4f2e842b97aaf2bccf;p=oota-llvm.git diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp index d06bba6f3a9..f6ad9c69387 100644 --- a/lib/Target/SparcV9/SparcV9RegInfo.cpp +++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp @@ -8,7 +8,7 @@ #include "SparcInternals.h" #include "SparcRegClassInfo.h" #include "llvm/Target/Sparc.h" -#include "llvm/CodeGen/MachineCodeForMethod.h" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/PhyRegAlloc.h" #include "llvm/CodeGen/InstrSelection.h" #include "llvm/CodeGen/InstrSelectionSupport.h" @@ -26,7 +26,7 @@ using std::cerr; using std::vector; UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt) - : MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6), + : MachineRegInfo(tgt), NumOfIntArgRegs(6), NumOfFloatArgRegs(32), InvalidRegNum(1000) { MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID)); @@ -477,7 +477,7 @@ void UltraSparcRegInfo::colorMethodArgs(const Function *Meth, regClassIDOfArgReg == IntRegClassID && "This should only be an Int register for an FP argument"); - int TmpOff = MachineCodeForMethod::get(Meth).pushTempValue(target, + int TmpOff = MachineFunction::get(Meth).pushTempValue(target, getSpilledRegSize(regType)); cpReg2MemMI(FirstAI->InstrnsBefore, UniArgReg, getFramePointer(), TmpOff, IntRegType); @@ -496,7 +496,7 @@ void UltraSparcRegInfo::colorMethodArgs(const Function *Meth, // const MachineFrameInfo& frameInfo = target.getFrameInfo(); int offsetFromFP = - frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth), + frameInfo.getIncomingArgOffset(MachineFunction::get(Meth), argNo); cpMem2RegMI(FirstAI->InstrnsBefore, @@ -544,7 +544,7 @@ void UltraSparcRegInfo::colorMethodArgs(const Function *Meth, const MachineFrameInfo& frameInfo = target.getFrameInfo(); int offsetFromFP = - frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth), + frameInfo.getIncomingArgOffset(MachineFunction::get(Meth), argNo); LR->modifySpillOffFromFP( offsetFromFP ); @@ -564,7 +564,7 @@ void UltraSparcRegInfo::colorMethodArgs(const Function *Meth, //--------------------------------------------------------------------------- void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI, LiveRangeInfo& LRI) const { - assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) ); + assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) ); CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI); @@ -663,7 +663,7 @@ UltraSparcRegInfo::InitializeOutgoingArg(MachineInstr* CallMI, { isArgInReg = true; UniArgReg = (unsigned) UniArgRegOrNone; - CallMI->getRegsUsed().insert(UniArgReg); // mark the reg as used + CallMI->insertUsedReg(UniArgReg); // mark the reg as used } if (LR->hasColor()) { @@ -683,7 +683,7 @@ UltraSparcRegInfo::InitializeOutgoingArg(MachineInstr* CallMI, else { // Copy UniLRReg to the stack to pass the arg on stack. const MachineFrameInfo& frameInfo = target.getFrameInfo(); - int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo); + int argOffset = frameInfo.getOutgoingArgOffset(PRA.MF, argNo); cpReg2MemMI(CallAI->InstrnsBefore, UniLRReg, getStackPointer(), argOffset, regType); } @@ -705,10 +705,10 @@ UltraSparcRegInfo::InitializeOutgoingArg(MachineInstr* CallMI, // Use TmpOff to save TReg, since that may have a live value. // int TReg = PRA.getUniRegNotUsedByThisInst( LR->getRegClass(), CallMI ); - int TmpOff = PRA.mcInfo.pushTempValue(target, - getSpilledRegSize(getRegType(LR))); + int TmpOff = PRA.MF.pushTempValue(target, + getSpilledRegSize(getRegType(LR))); const MachineFrameInfo& frameInfo = target.getFrameInfo(); - int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo); + int argOffset = frameInfo.getOutgoingArgOffset(PRA.MF, argNo); MachineInstr *Ad1, *Ad2, *Ad3, *Ad4; @@ -750,7 +750,7 @@ void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI, PhyRegAlloc &PRA, const BasicBlock *BB) const { - assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) ); + assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) ); CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI); @@ -788,7 +788,7 @@ void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI, UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol); // Mark the register as used by this instruction - CallMI->getRegsUsed().insert(UniRetReg); + CallMI->insertUsedReg(UniRetReg); // if the LR received the correct color, NOTHING to do recvCorrectColor = RetValLR->hasColor()? RetValLR->getColor() == CorrectCol @@ -955,7 +955,7 @@ void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI, void UltraSparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI, LiveRangeInfo &LRI) const { - assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) ); + assert( (target.getInstrInfo()).isReturn( RetMI->getOpCode() ) ); suggestReg4RetAddr(RetMI, LRI); @@ -993,7 +993,7 @@ void UltraSparcRegInfo::colorRetValue(MachineInstr *RetMI, LiveRangeInfo &LRI, AddedInstrns *RetAI) const { - assert((UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode())); + assert((target.getInstrInfo()).isReturn( RetMI->getOpCode())); // if there is an implicit ref, that has to be the ret value if(RetMI->getNumImplicitRefs() > 0) { @@ -1026,7 +1026,7 @@ void UltraSparcRegInfo::colorRetValue(MachineInstr *RetMI, unsigned UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol); // Mark the register as used by this instruction - RetMI->getRegsUsed().insert(UniRetReg); + RetMI->insertUsedReg(UniRetReg); // if the LR received the correct color, NOTHING to do @@ -1149,27 +1149,30 @@ UltraSparcRegInfo::cpReg2MemMI(vector& mvec, MachineInstr * MI = NULL; switch( RegType ) { case IntRegType: + assert(target.getInstrInfo().constantFitsInImmedField(STX, Offset)); MI = new MachineInstr(STX, 3); - MI->SetMachineOperandReg(0, SrcReg, false); - MI->SetMachineOperandReg(1, DestPtrReg, false); + MI->SetMachineOperandReg(0, SrcReg); + MI->SetMachineOperandReg(1, DestPtrReg); MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed, (int64_t) Offset); mvec.push_back(MI); break; case FPSingleRegType: + assert(target.getInstrInfo().constantFitsInImmedField(ST, Offset)); MI = new MachineInstr(ST, 3); - MI->SetMachineOperandReg(0, SrcReg, false); - MI->SetMachineOperandReg(1, DestPtrReg, false); + MI->SetMachineOperandReg(0, SrcReg); + MI->SetMachineOperandReg(1, DestPtrReg); MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed, (int64_t) Offset); mvec.push_back(MI); break; case FPDoubleRegType: + assert(target.getInstrInfo().constantFitsInImmedField(STD, Offset)); MI = new MachineInstr(STD, 3); - MI->SetMachineOperandReg(0, SrcReg, false); - MI->SetMachineOperandReg(1, DestPtrReg, false); + MI->SetMachineOperandReg(0, SrcReg); + MI->SetMachineOperandReg(1, DestPtrReg); MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed, (int64_t) Offset); mvec.push_back(MI); @@ -1188,9 +1191,10 @@ UltraSparcRegInfo::cpReg2MemMI(vector& mvec, case FloatCCRegType: assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here"); + assert(target.getInstrInfo().constantFitsInImmedField(STXFSR, Offset)); MI = new MachineInstr(STXFSR, 3); - MI->SetMachineOperandReg(0, SrcReg, false); - MI->SetMachineOperandReg(1, DestPtrReg, false); + MI->SetMachineOperandReg(0, SrcReg); + MI->SetMachineOperandReg(1, DestPtrReg); MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed, (int64_t) Offset); mvec.push_back(MI); @@ -1218,8 +1222,9 @@ UltraSparcRegInfo::cpMem2RegMI(vector& mvec, MachineInstr * MI = NULL; switch (RegType) { case IntRegType: + assert(target.getInstrInfo().constantFitsInImmedField(LDX, Offset)); MI = new MachineInstr(LDX, 3); - MI->SetMachineOperandReg(0, SrcPtrReg, false); + MI->SetMachineOperandReg(0, SrcPtrReg); MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed, (int64_t) Offset); MI->SetMachineOperandReg(2, DestReg, true); @@ -1227,8 +1232,9 @@ UltraSparcRegInfo::cpMem2RegMI(vector& mvec, break; case FPSingleRegType: + assert(target.getInstrInfo().constantFitsInImmedField(LD, Offset)); MI = new MachineInstr(LD, 3); - MI->SetMachineOperandReg(0, SrcPtrReg, false); + MI->SetMachineOperandReg(0, SrcPtrReg); MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed, (int64_t) Offset); MI->SetMachineOperandReg(2, DestReg, true); @@ -1236,8 +1242,9 @@ UltraSparcRegInfo::cpMem2RegMI(vector& mvec, break; case FPDoubleRegType: + assert(target.getInstrInfo().constantFitsInImmedField(LDD, Offset)); MI = new MachineInstr(LDD, 3); - MI->SetMachineOperandReg(0, SrcPtrReg, false); + MI->SetMachineOperandReg(0, SrcPtrReg); MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed, (int64_t) Offset); MI->SetMachineOperandReg(2, DestReg, true); @@ -1257,8 +1264,9 @@ UltraSparcRegInfo::cpMem2RegMI(vector& mvec, case FloatCCRegType: assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here"); + assert(target.getInstrInfo().constantFitsInImmedField(LDXFSR, Offset)); MI = new MachineInstr(LDXFSR, 3); - MI->SetMachineOperandReg(0, SrcPtrReg, false); + MI->SetMachineOperandReg(0, SrcPtrReg); MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed, (int64_t) Offset); MI->SetMachineOperandReg(2, DestReg, true); @@ -1290,30 +1298,29 @@ UltraSparcRegInfo::cpValue2Value(Value *Src, switch( RegType ) { case IntRegType: MI = new MachineInstr(ADD, 3); - MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false); - MI->SetMachineOperandReg(1, getZeroRegNum(), false); - MI->SetMachineOperandVal(2, MachineOperand:: MO_VirtualRegister, Dest, true); + MI->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, Src); + MI->SetMachineOperandReg(1, getZeroRegNum()); + MI->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, Dest, true); break; case FPSingleRegType: MI = new MachineInstr(FMOVS, 2); - MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false); - MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true); + MI->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, Src); + MI->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, Dest, true); break; case FPDoubleRegType: MI = new MachineInstr(FMOVD, 2); - MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false); - MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true); + MI->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, Src); + MI->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, Dest, true); break; default: assert(0 && "Unknow RegType in CpValu2Value"); } - if (MI) - mvec.push_back(MI); + mvec.push_back(MI); } @@ -1342,7 +1349,7 @@ UltraSparcRegInfo::insertCallerSavingCode(vector& instrnsBefore, const BasicBlock *BB, PhyRegAlloc &PRA) const { - assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) ); + assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) ); // has set to record which registers were saved/restored // @@ -1405,8 +1412,8 @@ UltraSparcRegInfo::insertCallerSavingCode(vector& instrnsBefore, // and add them to InstrnsBefore and InstrnsAfter of the // call instruction // - int StackOff = PRA.mcInfo.pushTempValue(target, - getSpilledRegSize(RegType)); + int StackOff = PRA.MF.pushTempValue(target, + getSpilledRegSize(RegType)); vector AdIBef, AdIAft; @@ -1425,7 +1432,7 @@ UltraSparcRegInfo::insertCallerSavingCode(vector& instrnsBefore, scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetBef, CallMI, AdIBef, AdIAft); assert(scratchReg != getInvalidRegNum()); - CallMI->getRegsUsed().insert(scratchReg); + CallMI->insertUsedReg(scratchReg); } if (AdIBef.size() > 0) @@ -1453,7 +1460,7 @@ UltraSparcRegInfo::insertCallerSavingCode(vector& instrnsBefore, scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetAft, CallMI, AdIBef, AdIAft); assert(scratchReg != getInvalidRegNum()); - CallMI->getRegsUsed().insert(scratchReg); + CallMI->insertUsedReg(scratchReg); } if (AdIBef.size() > 0) @@ -1591,11 +1598,10 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector &UnordVec, // last operand is the def (unless for a store which has no def reg) MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1); - if( DefOp.opIsDef() && - DefOp.getOperandType() == MachineOperand::MO_MachineRegister) { + if (DefOp.opIsDef() && + DefOp.getType() == MachineOperand::MO_MachineRegister) { // If the operand in DefInst is a def ... - bool DefEqUse = false; std::vector::iterator UseIt = DefIt; @@ -1609,8 +1615,8 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector &UnordVec, // for each inst (UseInst) that is below the DefInst do ... MachineOperand& UseOp = UseInst->getOperand(0); - if( ! UseOp.opIsDef() && - UseOp.getOperandType() == MachineOperand::MO_MachineRegister) { + if (!UseOp.opIsDef() && + UseOp.getType() == MachineOperand::MO_MachineRegister) { // if use is a register ... @@ -1670,8 +1676,8 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector &OrdVec, PhyRegAlloc &PRA) const { MachineOperand& UseOp = UnordInst->getOperand(0); - if( ! UseOp.opIsDef() && - UseOp.getOperandType() == MachineOperand::MO_MachineRegister) { + if (!UseOp.opIsDef() && + UseOp.getType() == MachineOperand::MO_MachineRegister) { // for the use of UnordInst, see whether there is a defining instr // before in the OrdVec @@ -1687,7 +1693,7 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector &OrdVec, OrdInst->getOperand(OrdInst->getNumOperands()-1); if( DefOp.opIsDef() && - DefOp.getOperandType() == MachineOperand::MO_MachineRegister) { + DefOp.getType() == MachineOperand::MO_MachineRegister) { //cerr << "\nDefining Ord Inst: " << *OrdInst; @@ -1702,12 +1708,12 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector &OrdVec, // Now we are processing %ox of 1. // We have to - const int UReg = DefOp.getMachineRegNum(); - const int RegType = getRegType(UReg); + int UReg = DefOp.getMachineRegNum(); + int RegType = getRegType(UReg); MachineInstr *AdIBef, *AdIAft; - const int StackOff = PRA.mcInfo.pushTempValue(target, - getSpilledRegSize(RegType)); + const int StackOff = PRA.MF.pushTempValue(target, + getSpilledRegSize(RegType)); // Save the UReg (%ox) on stack before it's destroyed vector mvec; @@ -1725,9 +1731,8 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector &OrdVec, cpMem2RegMI(OrdVec, getFramePointer(), StackOff, DReg, RegType); - cerr << "\nFixed CIRCULAR references by reordering"; - if( DEBUG_RA ) { + cerr << "\nFixed CIRCULAR references by reordering:"; cerr << "\nBefore CIRCULAR Reordering:\n"; cerr << *UnordInst; cerr << *OrdInst;