X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FSparcV9%2FSparcV9TargetMachine.cpp;h=faed36c32a8e18fddde85239bb43f7330f564ab8;hb=601899d196db343670943285c8f989534710937e;hp=9524e80515999771fc5c12febd6607dc10e4d90c;hpb=d00982a81c7331ead82be99d9374eb6c6d4ce44a;p=oota-llvm.git diff --git a/lib/Target/SparcV9/SparcV9TargetMachine.cpp b/lib/Target/SparcV9/SparcV9TargetMachine.cpp index 9524e805159..faed36c32a8 100644 --- a/lib/Target/SparcV9/SparcV9TargetMachine.cpp +++ b/lib/Target/SparcV9/SparcV9TargetMachine.cpp @@ -1,191 +1,57 @@ -// $Id$ -//*************************************************************************** -// File: -// Sparc.cpp -// -// Purpose: -// -// History: -// 7/15/01 - Vikram Adve - Created -//**************************************************************************/ - +//===-- Sparc.cpp - General implementation file for the Sparc Target ------===// +// +// This file contains the code for the Sparc Target that does not fit in any of +// the other files in this directory. +// +//===----------------------------------------------------------------------===// #include "SparcInternals.h" -#include "llvm/Target/Sparc.h" -#include "llvm/CodeGen/InstrScheduling.h" +#include "llvm/Target/TargetMachineImpls.h" +#include "llvm/Function.h" +#include "llvm/PassManager.h" +#include "llvm/Transforms/Scalar.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/PreSelection.h" +#include "llvm/CodeGen/StackSlots.h" +#include "llvm/CodeGen/PeepholeOpts.h" #include "llvm/CodeGen/InstrSelection.h" -#include "llvm/CodeGen/PhyRegAlloc.h" -#include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h" -#include "llvm/Method.h" - +#include "llvm/CodeGen/InstrScheduling.h" +#include "llvm/CodeGen/RegisterAllocation.h" +#include "llvm/CodeGen/MachineCodeForInstruction.h" +#include "llvm/Reoptimizer/Mapping/MappingInfo.h" +#include "llvm/Reoptimizer/Mapping/FInfo.h" +#include "Support/CommandLine.h" +using std::cerr; // Build the MachineInstruction Description Array... const MachineInstrDescriptor SparcMachineInstrDesc[] = { #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \ NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \ { OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \ - NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS }, + NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS, 0 }, #include "SparcInstr.def" }; -//---------------------------------------------------------------------------- -// allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine -// that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface) -//---------------------------------------------------------------------------- -// - -TargetMachine *allocateSparcTargetMachine() { return new UltraSparc(); } - - -//---------------------------------------------------------------------------- -// Entry point for register allocation for a module -//---------------------------------------------------------------------------- - -void AllocateRegisters(Method *M, TargetMachine &target) -{ - - if ( (M)->isExternal() ) // don't process prototypes - return; - - if( DEBUG_RA ) { - cerr << endl << "******************** Method "<< (M)->getName(); - cerr << " ********************" <getEntryNode(); - unsigned N = GetInstructionsForProlog(entryBB, target, minstrVec); - assert(N <= MAX_INSTR_PER_VMINSTR); - if (N > 0) - { - MachineCodeForBasicBlock& bbMvec = entryBB->getMachineInstrVec(); - bbMvec.insert(bbMvec.begin(), minstrVec, minstrVec+N); - } -} - - -static void -InsertEpilogCode(Method* method, TargetMachine& target) -{ - for (Method::iterator I=method->begin(), E=method->end(); I != E; ++I) - if ((*I)->getTerminator()->getOpcode() == Instruction::Ret) - { - BasicBlock* exitBB = *I; - unsigned N = GetInstructionsForEpilog(exitBB, target, minstrVec); - - MachineCodeForBasicBlock& bbMvec = exitBB->getMachineInstrVec(); - MachineCodeForVMInstr& termMvec = - exitBB->getTerminator()->getMachineInstrVec(); - - // Remove the NOPs in the delay slots of the return instruction - const MachineInstrInfo& mii = target.getInstrInfo(); - unsigned numNOPs = 0; - while (termMvec.back()->getOpCode() == NOP) - { - assert( termMvec.back() == bbMvec.back()); - termMvec.pop_back(); - bbMvec.pop_back(); - ++numNOPs; - } - assert(termMvec.back() == bbMvec.back()); - - // Check that we found the right number of NOPs and have the right - // number of instructions to replace them. - unsigned ndelays = mii.getNumDelaySlots(termMvec.back()->getOpCode()); - assert(numNOPs == ndelays && "Missing NOPs in delay slots?"); - assert(N == ndelays && "Cannot use epilog code for delay slots?"); - - // Append the epilog code to the end of the basic block. - bbMvec.push_back(minstrVec[0]); - } -} - +static cl::opt DisablePreSelect("nopreselect", + cl::desc("Disable preselection pass")); -// Insert SAVE/RESTORE instructions for the method -static void -InsertPrologEpilog(Method *method, TargetMachine &target) -{ - MachineCodeForMethod& mcodeInfo = MachineCodeForMethod::get(method); - if (mcodeInfo.isCompiledAsLeafMethod()) - return; // nothing to do - - InsertPrologCode(method, target); - InsertEpilogCode(method, target); -} +static cl::opt DisableSched("nosched", + cl::desc("Disable local scheduling pass")); +static cl::opt DisablePeephole("nopeephole", + cl::desc("Disable peephole optimization pass")); -//--------------------------------------------------------------------------- -// class UltraSparcSchedInfo -// -// Purpose: -// Scheduling information for the UltraSPARC. -// Primarily just initializes machine-dependent parameters in -// class MachineSchedInfo. -//--------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +// allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine +// that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface) +//---------------------------------------------------------------------------- -/*ctor*/ -UltraSparcSchedInfo::UltraSparcSchedInfo(const TargetMachine& tgt) - : MachineSchedInfo(tgt, - (unsigned int) SPARC_NUM_SCHED_CLASSES, - SparcRUsageDesc, - SparcInstrUsageDeltas, - SparcInstrIssueDeltas, - sizeof(SparcInstrUsageDeltas)/sizeof(InstrRUsageDelta), - sizeof(SparcInstrIssueDeltas)/sizeof(InstrIssueDelta)) -{ - maxNumIssueTotal = 4; - longestIssueConflict = 0; // computed from issuesGaps[] - - branchMispredictPenalty = 4; // 4 for SPARC IIi - branchTargetUnknownPenalty = 2; // 2 for SPARC IIi - l1DCacheMissPenalty = 8; // 7 or 9 for SPARC IIi - l1ICacheMissPenalty = 8; // ? for SPARC IIi - - inOrderLoads = true; // true for SPARC IIi - inOrderIssue = true; // true for SPARC IIi - inOrderExec = false; // false for most architectures - inOrderRetire= true; // true for most architectures - - // must be called after above parameters are initialized. - this->initializeResources(); -} +TargetMachine *allocateSparcTargetMachine() { return new UltraSparc(); } -void -UltraSparcSchedInfo::initializeResources() -{ - // Compute MachineSchedInfo::instrRUsages and MachineSchedInfo::issueGaps - MachineSchedInfo::initializeResources(); - - // Machine-dependent fixups go here. None for now. -} //--------------------------------------------------------------------------- @@ -198,7 +64,7 @@ UltraSparcSchedInfo::initializeResources() //--------------------------------------------------------------------------- int -UltraSparcFrameInfo::getFirstAutomaticVarOffset(MachineCodeForMethod& , +UltraSparcFrameInfo::getFirstAutomaticVarOffset(MachineFunction& , bool& pos) const { pos = false; // static stack area grows downwards @@ -206,41 +72,47 @@ UltraSparcFrameInfo::getFirstAutomaticVarOffset(MachineCodeForMethod& , } int -UltraSparcFrameInfo::getRegSpillAreaOffset(MachineCodeForMethod& mcInfo, +UltraSparcFrameInfo::getRegSpillAreaOffset(MachineFunction& mcInfo, bool& pos) const { + mcInfo.freezeAutomaticVarsArea(); // ensure no more auto vars are added + pos = false; // static stack area grows downwards unsigned int autoVarsSize = mcInfo.getAutomaticVarsSize(); - if (int mod = autoVarsSize % getStackFrameSizeAlignment()) - autoVarsSize += (getStackFrameSizeAlignment() - mod); return StaticAreaOffsetFromFP - autoVarsSize; } int -UltraSparcFrameInfo::getTmpAreaOffset(MachineCodeForMethod& mcInfo, +UltraSparcFrameInfo::getTmpAreaOffset(MachineFunction& mcInfo, bool& pos) const { + mcInfo.freezeAutomaticVarsArea(); // ensure no more auto vars are added + mcInfo.freezeSpillsArea(); // ensure no more spill slots are added + pos = false; // static stack area grows downwards unsigned int autoVarsSize = mcInfo.getAutomaticVarsSize(); unsigned int spillAreaSize = mcInfo.getRegSpillsSize(); int offset = autoVarsSize + spillAreaSize; - if (int mod = offset % getStackFrameSizeAlignment()) - offset += (getStackFrameSizeAlignment() - mod); return StaticAreaOffsetFromFP - offset; } int -UltraSparcFrameInfo::getDynamicAreaOffset(MachineCodeForMethod& mcInfo, +UltraSparcFrameInfo::getDynamicAreaOffset(MachineFunction& mcInfo, bool& pos) const { - // dynamic stack area grows downwards starting at top of opt-args area + // Dynamic stack area grows downwards starting at top of opt-args area. + // The opt-args, required-args, and register-save areas are empty except + // during calls and traps, so they are shifted downwards on each + // dynamic-size alloca. + pos = false; unsigned int optArgsSize = mcInfo.getMaxOptionalArgsSize(); + if (int extra = optArgsSize % getStackFrameSizeAlignment()) + optArgsSize += (getStackFrameSizeAlignment() - extra); int offset = optArgsSize + FirstOptionalOutgoingArgOffsetFromSP; - assert(offset % getStackFrameSizeAlignment() == 0); + assert((offset - OFFSET) % getStackFrameSizeAlignment() == 0); return offset; } - //--------------------------------------------------------------------------- // class UltraSparcMachine // @@ -253,60 +125,65 @@ UltraSparcFrameInfo::getDynamicAreaOffset(MachineCodeForMethod& mcInfo, //--------------------------------------------------------------------------- UltraSparc::UltraSparc() - : TargetMachine("UltraSparc-Native"), - instrInfo(*this), + : TargetMachine("UltraSparc-Native", 4), schedInfo(*this), regInfo(*this), frameInfo(*this), - cacheInfo(*this) -{ - optSizeForSubWordData = 4; - minMemOpWordSize = 8; - maxAtomicMemOpWordSize = 8; + cacheInfo(*this), + optInfo(*this) { } -void -ApplyPeepholeOptimizations(Method *method, TargetMachine &target) +// addPassesToEmitAssembly - This method controls the entire code generation +// process for the ultra sparc. +// +bool UltraSparc::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out) { - return; - - // OptimizeLeafProcedures(); - // DeleteFallThroughBranches(); - // RemoveChainedBranches(); // should be folded with previous - // RemoveRedundantOps(); // operations with %g0, NOP, etc. -} - + // Construct and initialize the MachineFunction object for this fn. + PM.add(createMachineCodeConstructionPass(*this)); + //Insert empty stackslots in the stack frame of each function + //so %fp+offset-8 and %fp+offset-16 are empty slots now! + PM.add(createStackSlotsPass(*this)); -bool -UltraSparc::compileMethod(Method *method) -{ - // Construct and initialize the MachineCodeForMethod object for this method. - (void) MachineCodeForMethod::construct(method, *this); - - if (SelectInstructionsForMethod(method, *this)) + // Specialize LLVM code for this target machine and then + // run basic dataflow optimizations on LLVM code. + if (!DisablePreSelect) { - cerr << "Instruction selection failed for method " << method->getName() - << "\n\n"; - return true; + PM.add(createPreSelectionPass(*this)); + /* PM.add(createReassociatePass()); */ + PM.add(createLICMPass()); + PM.add(createGCSEPass()); } - /* - if (ScheduleInstructionsWithSSA(method, *this)) - { - cerr << "Instruction scheduling before allocation failed for method " - << method->getName() << "\n\n"; - return true; - } - */ - + PM.add(createInstructionSelectionPass(*this)); - AllocateRegisters(method, *this); // allocate registers - - ApplyPeepholeOptimizations(method, *this); // machine-dependent peephole opts - - InsertPrologEpilog(method, *this); - + if (!DisableSched) + PM.add(createInstructionSchedulingWithSSAPass(*this)); + + PM.add(getRegisterAllocator(*this)); + + PM.add(getPrologEpilogInsertionPass()); + + if (!DisablePeephole) + PM.add(createPeepholeOptsPass(*this)); + + PM.add(MappingInfoForFunction(Out)); + + // Output assembly language to the .s file. Assembly emission is split into + // two parts: Function output and Global value output. This is because + // function output is pipelined with all of the rest of code generation stuff, + // allowing machine code representations for functions to be free'd after the + // function has been emitted. + // + PM.add(getFunctionAsmPrinterPass(Out)); + PM.add(createMachineCodeDestructionPass()); // Free stuff no longer needed + + // Emit Module level assembly after all of the functions have been processed. + PM.add(getModuleAsmPrinterPass(Out)); + + // Emit bytecode to the assembly file into its special section next + PM.add(getEmitBytecodeToAsmPass(Out)); + PM.add(getFunctionInfo(Out)); return false; }