X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FSystemZ%2FSystemZRegisterInfo.td;h=8795847a6c3c6a44bdd6e3f513961045c154862e;hb=b92187a4103dca24c3767c380f63593d1f6161a7;hp=bdff54262f9e9b076897e9f428e7aee2dfb22218;hpb=338cf05f16e3d0f1f0de1c0d8969f11bc7df1240;p=oota-llvm.git diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.td b/lib/Target/SystemZ/SystemZRegisterInfo.td index bdff54262f9..8795847a6c3 100644 --- a/lib/Target/SystemZ/SystemZRegisterInfo.td +++ b/lib/Target/SystemZ/SystemZRegisterInfo.td @@ -27,19 +27,29 @@ class GPR32 num, string n> : SystemZReg { } // GPR64 - One of the 16 64-bit general-purpose registers -class GPR64 num, string n, list subregs> +class GPR64 num, string n, list subregs, + list aliases = []> : SystemZRegWithSubregs { field bits<4> Num = num; + let Aliases = aliases; } // GPR128 - 8 even-odd register pairs -class GPR128 num, string n, list subregs> +class GPR128 num, string n, list subregs, + list aliases = []> : SystemZRegWithSubregs { field bits<4> Num = num; + let Aliases = aliases; } -// FPR - One of the 16 64-bit floating-point registers -class FPR num, string n> : SystemZReg { +// FPRS - Lower 32 bits of one of the 16 64-bit floating-point registers +class FPRS num, string n> : SystemZReg { + field bits<4> Num = num; +} + +// FPRL - One of the 16 64-bit floating-point registers +class FPRL num, string n, list subregs> + : SystemZRegWithSubregs { field bits<4> Num = num; } @@ -79,66 +89,89 @@ def R14D : GPR64<14, "r14", [R14W]>, DwarfRegNum<[14]>; def R15D : GPR64<15, "r15", [R15W]>, DwarfRegNum<[15]>; // Register pairs -def R0P : GPR64< 0, "r0", [R0W, R1W]>, DwarfRegNum<[0]>; -def R2P : GPR64< 2, "r2", [R2W, R3W]>, DwarfRegNum<[2]>; -def R4P : GPR64< 4, "r4", [R4W, R5W]>, DwarfRegNum<[4]>; -def R6P : GPR64< 6, "r6", [R6W, R7W]>, DwarfRegNum<[6]>; -def R8P : GPR64< 8, "r8", [R8W, R9W]>, DwarfRegNum<[8]>; -def R10P : GPR64<10, "r10", [R10W, R11W]>, DwarfRegNum<[10]>; -def R12P : GPR64<12, "r12", [R12W, R13W]>, DwarfRegNum<[12]>; -def R14P : GPR64<14, "r14", [R14W, R15W]>, DwarfRegNum<[14]>; - -def R0Q : GPR128< 0, "r0", [R0D, R1D]>, DwarfRegNum<[0]>; -def R2Q : GPR128< 2, "r2", [R2D, R3D]>, DwarfRegNum<[2]>; -def R4Q : GPR128< 4, "r4", [R4D, R5D]>, DwarfRegNum<[4]>; -def R6Q : GPR128< 6, "r6", [R6D, R7D]>, DwarfRegNum<[6]>; -def R8Q : GPR128< 8, "r8", [R8D, R9D]>, DwarfRegNum<[8]>; -def R10Q : GPR128<10, "r10", [R10D, R11D]>, DwarfRegNum<[10]>; -def R12Q : GPR128<12, "r12", [R12D, R13D]>, DwarfRegNum<[12]>; -def R14Q : GPR128<14, "r14", [R14D, R15D]>, DwarfRegNum<[14]>; +def R0P : GPR64< 0, "r0", [R0W, R1W], [R0D, R1D]>, DwarfRegNum<[0]>; +def R2P : GPR64< 2, "r2", [R2W, R3W], [R2D, R3D]>, DwarfRegNum<[2]>; +def R4P : GPR64< 4, "r4", [R4W, R5W], [R4D, R5D]>, DwarfRegNum<[4]>; +def R6P : GPR64< 6, "r6", [R6W, R7W], [R6D, R7D]>, DwarfRegNum<[6]>; +def R8P : GPR64< 8, "r8", [R8W, R9W], [R8D, R9D]>, DwarfRegNum<[8]>; +def R10P : GPR64<10, "r10", [R10W, R11W], [R10D, R11D]>, DwarfRegNum<[10]>; +def R12P : GPR64<12, "r12", [R12W, R13W], [R12D, R13D]>, DwarfRegNum<[12]>; +def R14P : GPR64<14, "r14", [R14W, R15W], [R14D, R15D]>, DwarfRegNum<[14]>; + +def R0Q : GPR128< 0, "r0", [R0D, R1D], [R0P]>, DwarfRegNum<[0]>; +def R2Q : GPR128< 2, "r2", [R2D, R3D], [R2P]>, DwarfRegNum<[2]>; +def R4Q : GPR128< 4, "r4", [R4D, R5D], [R4P]>, DwarfRegNum<[4]>; +def R6Q : GPR128< 6, "r6", [R6D, R7D], [R6P]>, DwarfRegNum<[6]>; +def R8Q : GPR128< 8, "r8", [R8D, R9D], [R8P]>, DwarfRegNum<[8]>; +def R10Q : GPR128<10, "r10", [R10D, R11D], [R10P]>, DwarfRegNum<[10]>; +def R12Q : GPR128<12, "r12", [R12D, R13D], [R12P]>, DwarfRegNum<[12]>; +def R14Q : GPR128<14, "r14", [R14D, R15D], [R14P]>, DwarfRegNum<[14]>; // Floating-point registers -def F0 : FPR< 0, "f0">, DwarfRegNum<[16]>; -def F1 : FPR< 1, "f1">, DwarfRegNum<[17]>; -def F2 : FPR< 2, "f2">, DwarfRegNum<[18]>; -def F3 : FPR< 3, "f3">, DwarfRegNum<[19]>; -def F4 : FPR< 4, "f4">, DwarfRegNum<[20]>; -def F5 : FPR< 5, "f5">, DwarfRegNum<[21]>; -def F6 : FPR< 6, "f6">, DwarfRegNum<[22]>; -def F7 : FPR< 7, "f7">, DwarfRegNum<[23]>; -def F8 : FPR< 8, "f8">, DwarfRegNum<[24]>; -def F9 : FPR< 9, "f9">, DwarfRegNum<[25]>; -def F10 : FPR<10, "f10">, DwarfRegNum<[26]>; -def F11 : FPR<11, "f11">, DwarfRegNum<[27]>; -def F12 : FPR<12, "f12">, DwarfRegNum<[28]>; -def F13 : FPR<13, "f13">, DwarfRegNum<[29]>; -def F14 : FPR<14, "f14">, DwarfRegNum<[30]>; -def F15 : FPR<15, "f15">, DwarfRegNum<[31]>; +def F0S : FPRS< 0, "f0">, DwarfRegNum<[16]>; +def F1S : FPRS< 1, "f1">, DwarfRegNum<[17]>; +def F2S : FPRS< 2, "f2">, DwarfRegNum<[18]>; +def F3S : FPRS< 3, "f3">, DwarfRegNum<[19]>; +def F4S : FPRS< 4, "f4">, DwarfRegNum<[20]>; +def F5S : FPRS< 5, "f5">, DwarfRegNum<[21]>; +def F6S : FPRS< 6, "f6">, DwarfRegNum<[22]>; +def F7S : FPRS< 7, "f7">, DwarfRegNum<[23]>; +def F8S : FPRS< 8, "f8">, DwarfRegNum<[24]>; +def F9S : FPRS< 9, "f9">, DwarfRegNum<[25]>; +def F10S : FPRS<10, "f10">, DwarfRegNum<[26]>; +def F11S : FPRS<11, "f11">, DwarfRegNum<[27]>; +def F12S : FPRS<12, "f12">, DwarfRegNum<[28]>; +def F13S : FPRS<13, "f13">, DwarfRegNum<[29]>; +def F14S : FPRS<14, "f14">, DwarfRegNum<[30]>; +def F15S : FPRS<15, "f15">, DwarfRegNum<[31]>; + +def F0L : FPRL< 0, "f0", [F0S]>, DwarfRegNum<[16]>; +def F1L : FPRL< 1, "f1", [F1S]>, DwarfRegNum<[17]>; +def F2L : FPRL< 2, "f2", [F2S]>, DwarfRegNum<[18]>; +def F3L : FPRL< 3, "f3", [F3S]>, DwarfRegNum<[19]>; +def F4L : FPRL< 4, "f4", [F4S]>, DwarfRegNum<[20]>; +def F5L : FPRL< 5, "f5", [F5S]>, DwarfRegNum<[21]>; +def F6L : FPRL< 6, "f6", [F6S]>, DwarfRegNum<[22]>; +def F7L : FPRL< 7, "f7", [F7S]>, DwarfRegNum<[23]>; +def F8L : FPRL< 8, "f8", [F8S]>, DwarfRegNum<[24]>; +def F9L : FPRL< 9, "f9", [F9S]>, DwarfRegNum<[25]>; +def F10L : FPRL<10, "f10", [F10S]>, DwarfRegNum<[26]>; +def F11L : FPRL<11, "f11", [F11S]>, DwarfRegNum<[27]>; +def F12L : FPRL<12, "f12", [F12S]>, DwarfRegNum<[28]>; +def F13L : FPRL<13, "f13", [F13S]>, DwarfRegNum<[29]>; +def F14L : FPRL<14, "f14", [F14S]>, DwarfRegNum<[30]>; +def F15L : FPRL<15, "f15", [F15S]>, DwarfRegNum<[31]>; // Status register def PSW : SystemZReg<"psw">; def subreg_32bit : PatLeaf<(i32 1)>; -def subreg_64even : PatLeaf<(i32 2)>; -def subreg_64odd : PatLeaf<(i32 3)>; -def subreg_32even : PatLeaf<(i32 4)>; -def subreg_32odd : PatLeaf<(i32 5)>; +def subreg_even32 : PatLeaf<(i32 1)>; +def subreg_odd32 : PatLeaf<(i32 2)>; +def subreg_even : PatLeaf<(i32 3)>; +def subreg_odd : PatLeaf<(i32 4)>; def : SubRegSet<1, [R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D, R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D], [R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W, R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>; -def : SubRegSet<2, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q], +def : SubRegSet<3, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q], [R0D, R2D, R4D, R6D, R8D, R10D, R12D, R14D]>; -def : SubRegSet<3, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q], +def : SubRegSet<4, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q], [R1D, R3D, R5D, R7D, R9D, R11D, R13D, R15D]>; -def : SubRegSet<4, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P], +def : SubRegSet<1, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P], [R0W, R2W, R4W, R6W, R8W, R10W, R12W, R14W]>; -def : SubRegSet<5, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P], +def : SubRegSet<2, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P], + [R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>; + +def : SubRegSet<1, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q], + [R0W, R2W, R4W, R6W, R8W, R10W, R12W, R14W]>; + +def : SubRegSet<2, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q], [R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>; /// Register classes @@ -330,7 +363,7 @@ def ADDR64 : RegisterClass<"SystemZ", [i64], 64, } // Even-odd register pairs -def GR64P : RegisterClass<"SystemZ", [i64], 64, +def GR64P : RegisterClass<"SystemZ", [v2i32], 64, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P]> { let SubRegClassList = [GR32, GR32]; @@ -366,10 +399,10 @@ def GR64P : RegisterClass<"SystemZ", [i64], 64, }]; } -def GR128 : RegisterClass<"SystemZ", [i128], 128, +def GR128 : RegisterClass<"SystemZ", [v2i64], 128, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q]> { - let SubRegClassList = [GR64, GR64]; + let SubRegClassList = [GR32, GR32, GR64, GR64]; let MethodProtos = [{ iterator allocation_order_begin(const MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const; @@ -402,8 +435,54 @@ def GR128 : RegisterClass<"SystemZ", [i128], 128, }]; } +def FP32 : RegisterClass<"SystemZ", [f32], 32, + [F0S, F1S, F2S, F3S, F4S, F5S, F6S, F7S, + F8S, F9S, F10S, F11S, F12S, F13S, F14S, F15S]> { + let MethodProtos = [{ + iterator allocation_order_begin(const MachineFunction &MF) const; + iterator allocation_order_end(const MachineFunction &MF) const; + }]; + let MethodBodies = [{ + static const unsigned SystemZ_REGFP32[] = { + SystemZ::F0S, SystemZ::F2S, SystemZ::F4S, SystemZ::F6S, + SystemZ::F1S, SystemZ::F3S, SystemZ::F5S, SystemZ::F7S, + SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, + SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S }; + FP32Class::iterator + FP32Class::allocation_order_begin(const MachineFunction &MF) const { + return SystemZ_REGFP32; + } + FP32Class::iterator + FP32Class::allocation_order_end(const MachineFunction &MF) const { + return SystemZ_REGFP32 + (sizeof(SystemZ_REGFP32) / sizeof(unsigned)); + } + }]; +} + def FP64 : RegisterClass<"SystemZ", [f64], 64, - [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15]>; + [F0L, F1L, F2L, F3L, F4L, F5L, F6L, F7L, + F8L, F9L, F10L, F11L, F12L, F13L, F14L, F15L]> { + let SubRegClassList = [FP32]; + let MethodProtos = [{ + iterator allocation_order_begin(const MachineFunction &MF) const; + iterator allocation_order_end(const MachineFunction &MF) const; + }]; + let MethodBodies = [{ + static const unsigned SystemZ_REGFP64[] = { + SystemZ::F0L, SystemZ::F2L, SystemZ::F4L, SystemZ::F6L, + SystemZ::F1L, SystemZ::F3L, SystemZ::F5L, SystemZ::F7L, + SystemZ::F8L, SystemZ::F9L, SystemZ::F10L, SystemZ::F11L, + SystemZ::F12L, SystemZ::F13L, SystemZ::F14L, SystemZ::F15L }; + FP64Class::iterator + FP64Class::allocation_order_begin(const MachineFunction &MF) const { + return SystemZ_REGFP64; + } + FP64Class::iterator + FP64Class::allocation_order_end(const MachineFunction &MF) const { + return SystemZ_REGFP64 + (sizeof(SystemZ_REGFP64) / sizeof(unsigned)); + } + }]; +} // Status flags registers. def CCR : RegisterClass<"SystemZ", [i64], 64, [PSW]> {