X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FTarget.td;h=4c846741caef0e362a030075c56760fa471c6ef5;hb=47622e37215429c20d8278ff57496d840811cc13;hp=14f975d5049af31fc55229179388cf132542da03;hpb=9222cdeca0b76d250e38ddb9b8615c6791e6dc60;p=oota-llvm.git diff --git a/lib/Target/Target.td b/lib/Target/Target.td index 14f975d5049..4c846741cae 100644 --- a/lib/Target/Target.td +++ b/lib/Target/Target.td @@ -12,60 +12,53 @@ // //===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// -// Value types - These values correspond to the register types defined in the -// ValueTypes.h file. If you update anything here, you must update it there as -// well! -// -class ValueType { - string Namespace = "MVT"; - int Size = size; - int Value = value; -} - -def OtherVT: ValueType<0 , 0>; // "Other" value -def i1 : ValueType<1 , 1>; // One bit boolean value -def i8 : ValueType<8 , 2>; // 8-bit integer value -def i16 : ValueType<16 , 3>; // 16-bit integer value -def i32 : ValueType<32 , 4>; // 32-bit integer value -def i64 : ValueType<64 , 5>; // 64-bit integer value -def i128 : ValueType<128, 5>; // 128-bit integer value -def f32 : ValueType<32 , 7>; // 32-bit floating point value -def f64 : ValueType<64 , 8>; // 64-bit floating point value -def f80 : ValueType<80 , 9>; // 80-bit floating point value -def f128 : ValueType<128, 9>; // 128-bit floating point value -def isVoid : ValueType<0 , 11>; // Produces no value +// Include all information about LLVM intrinsics. +include "llvm/Intrinsics.td" //===----------------------------------------------------------------------===// // Register file description - These classes are used to fill in the target -// description classes in llvm/Target/MRegisterInfo.h +// description classes. +class RegisterClass; // Forward def -// Register - You should define one instance of this class for each register in -// the target machine. -// -class Register { +// Register - You should define one instance of this class for each register +// in the target machine. String n will become the "name" of the register. +class Register { string Namespace = ""; - string Name = ""; -} - -// NamedReg - If the name for the 'def' of the register should not become the -// "name" of the register, you can use this to specify a custom name instead. -// -class NamedReg : Register { - let Name = n; + string Name = n; + + // SpillSize - If this value is set to a non-zero value, it is the size in + // bits of the spill slot required to hold this register. If this value is + // set to zero, the information is inferred from any register classes the + // register belongs to. + int SpillSize = 0; + + // SpillAlignment - This value is used to specify the alignment required for + // spilling the register. Like SpillSize, this should only be explicitly + // specified if the register is not in a register class. + int SpillAlignment = 0; + + // Aliases - A list of registers that this register overlaps with. A read or + // modification of this register can potentially read or modifie the aliased + // registers. + // + list Aliases = []; + + // DwarfNumber - Number used internally by gcc/gdb to identify the register. + // These values can be determined by locating the .h file in the + // directory llvmgcc/gcc/config// and looking for REGISTER_NAMES. The + // order of these names correspond to the enumeration used by gcc. A value of + // -1 indicates that the gcc number is undefined. + int DwarfNumber = -1; } -// RegisterAliases - You should define instances of this class to indicate which -// registers in the register file are aliased together. This allows the code -// generator to be careful not to put two values with overlapping live ranges -// into registers which alias. -// -class RegisterAliases aliases> { - Register Reg = reg; - list Aliases = aliases; +// RegisterGroup - This can be used to define instances of Register which +// need to specify aliases. +// List "aliases" specifies which registers are aliased to this one. This +// allows the code generator to be careful not to put two values with +// overlapping live ranges into registers which alias. +class RegisterGroup aliases> : Register { + let Aliases = aliases; } // RegisterClass - Now that all of the registers are defined, and aliases @@ -73,16 +66,22 @@ class RegisterAliases aliases> { // register classes. This also defines the default allocation order of // registers by register allocators. // -class RegisterClass regList> { +class RegisterClass regTypes, int alignment, + list regList> { + string Namespace = namespace; + // RegType - Specify the ValueType of the registers in this register class. // Note that all registers in a register class must have the same ValueType. // - ValueType RegType = regType; + list RegTypes = regTypes; + + // Size - Specify the spill size in bits of the registers. A default value of + // zero lets tablgen pick an appropriate size. + int Size = 0; // Alignment - Specify the alignment required of the registers when they are // stored or loaded to memory. // - int Size = RegType.Size; int Alignment = alignment; // MemberList - Specify which registers are in this class. If the @@ -91,15 +90,34 @@ class RegisterClass regList> { // list MemberList = regList; - // Methods - This member can be used to insert arbitrary code into a generated - // register class. The normal usage of this is to overload virtual methods. - code Methods = [{}]; + // MethodProtos/MethodBodies - These members can be used to insert arbitrary + // code into a generated register class. The normal usage of this is to + // overload virtual methods. + code MethodProtos = [{}]; + code MethodBodies = [{}]; +} + - // isDummyClass - If this is set to true, this register class is not really - // part of the target, it is just used for other purposes. - bit isDummyClass = 0; +//===----------------------------------------------------------------------===// +// DwarfRegNum - This class provides a mapping of the llvm register enumeration +// to the register numbering used by gcc and gdb. These values are used by a +// debug information writer (ex. DwarfWriter) to describe where values may be +// located during execution. +class DwarfRegNum { + // DwarfNumber - Number used internally by gcc/gdb to identify the register. + // These values can be determined by locating the .h file in the + // directory llvmgcc/gcc/config// and looking for REGISTER_NAMES. The + // order of these names correspond to the enumeration used by gcc. A value of + // -1 indicates that the gcc number is undefined. + int DwarfNumber = N; } +//===----------------------------------------------------------------------===// +// Pull in the common support for scheduling +// +include "../TargetSchedule.td" + +class Predicate; // Forward def //===----------------------------------------------------------------------===// // Instruction set description - These classes correspond to the C++ classes in @@ -122,29 +140,57 @@ class Instruction { list Uses = []; // Default to using no non-operand registers list Defs = []; // Default to modifying no non-operand registers + // Predicates - List of predicates which will be turned into isel matching + // code. + list Predicates = []; + // These bits capture information about the high-level semantics of the // instruction. bit isReturn = 0; // Is this instruction a return instruction? bit isBranch = 0; // Is this instruction a branch instruction? bit isBarrier = 0; // Can control flow fall through this instruction? bit isCall = 0; // Is this instruction a call instruction? + bit isLoad = 0; // Is this instruction a load instruction? + bit isStore = 0; // Is this instruction a store instruction? bit isTwoAddress = 0; // Is this a two address instruction? + bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? + bit isCommutable = 0; // Is this 3 operand instruction commutable? bit isTerminator = 0; // Is this part of the terminator for a basic block? + bit hasDelaySlot = 0; // Does this instruction have an delay slot? + bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help. + bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? + bit noResults = 0; // Does this instruction produce no results? + + InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. } +/// Predicates - These are extra conditionals which are turned into instruction +/// selector matching code. Currently each predicate is just a string. +class Predicate { + string CondString = cond; +} + +class Requires preds> { + list Predicates = preds; +} /// ops definition - This is just a simple marker used to identify the operands /// list for an instruction. This should be used like this: /// (ops R32:$dst, R32:$src) or something similar. def ops; +/// variable_ops definition - Mark this instruction as taking a variable number +/// of operands. +def variable_ops; + /// Operand Types - These provide the built-in operand types that may be used /// by a target. Targets can optionally provide their own operand types as /// needed, though this should not be needed for RISC targets. class Operand { - int NumMIOperands = 1; ValueType Type = ty; string PrintMethod = "printOperand"; + int NumMIOperands = 1; + dag MIOperandInfo = (ops); } def i1imm : Operand; @@ -157,14 +203,28 @@ def i64imm : Operand; // which are global to the the target machine. // class InstrInfo { - Instruction PHIInst; - // If the target wants to associate some target-specific information with each // instruction, it should provide these two lists to indicate how to assemble // the target specific information into the 32 bits available. // list TSFlagsFields = []; list TSFlagsShifts = []; + + // Target can specify its instructions in either big or little-endian formats. + // For instance, while both Sparc and PowerPC are big-endian platforms, the + // Sparc manual specifies its instructions in the format [31..0] (big), while + // PowerPC specifies them using the format [0..31] (little). + bit isLittleEndianEncoding = 0; +} + +// Standard Instructions. +def PHI : Instruction { + let OperandList = (ops variable_ops); + let AsmString = "PHINODE"; +} +def INLINEASM : Instruction { + let OperandList = (ops variable_ops); + let AsmString = ""; } //===----------------------------------------------------------------------===// @@ -183,6 +243,14 @@ class AsmWriter { // InstFormatName - AsmWriters can specify the name of the format string to // print instructions with. string InstFormatName = "AsmString"; + + // Variant - AsmWriters can be of multiple different variants. Variants are + // used to support targets that need to emit assembly code in ways that are + // mostly the same for different targets, but have minor differences in + // syntax. If the asmstring contains {|} characters in them, this integer + // will specify which alternative to use. For example "{x|y|z}" with Variant + // == 1, will expand to "y". + int Variant = 0; } def DefaultAsmWriter : AsmWriter; @@ -202,98 +270,53 @@ class Target { // InstructionSet - Instruction set description for this target. InstrInfo InstructionSet; - // AssemblyWriter - The AsmWriter instance to use for this target. - AsmWriter AssemblyWriter = DefaultAsmWriter; + // AssemblyWriters - The AsmWriter instances available for this target. + list AssemblyWriters = [DefaultAsmWriter]; } - //===----------------------------------------------------------------------===// -// DAG node definitions used by the instruction selector. -// -// NOTE: all of this is a work-in-progress and should be ignored for now. +// SubtargetFeature - A characteristic of the chip set. // -/* -class Expander result> { - dag Pattern = pattern; - list Result = result; -} - -class DagNodeValType; -def DNVT_any : DagNodeValType; // No constraint on tree node -def DNVT_void : DagNodeValType; // Tree node always returns void -def DNVT_val : DagNodeValType; // A non-void type -def DNVT_arg0 : DagNodeValType; // Tree node returns same type as Arg0 -def DNVT_arg1 : DagNodeValType; // Tree node returns same type as Arg1 -def DNVT_ptr : DagNodeValType; // The target pointer type -def DNVT_i8 : DagNodeValType; // Always have an i8 value - -class DagNode args> { - DagNodeValType RetType = ret; - list ArgTypes = args; - string EnumName = ?; -} - -// BuiltinDagNodes are built into the instruction selector and correspond to -// enum values. -class BuiltinDagNode Args, - string Ename> : DagNode { - let EnumName = Ename; +class SubtargetFeature { + // Name - Feature name. Used by command line (-mattr=) to determine the + // appropriate target chip. + // + string Name = n; + + // Attribute - Attribute to be set by feature. + // + string Attribute = a; + + // Value - Value the attribute to be set to by feature. + // + string Value = v; + + // Desc - Feature description. Used by command line (-mattr=) to display help + // information. + // + string Desc = d; } -// Magic nodes... -def Void : RegisterClass { let isDummyClass = 1; } -def set : DagNode; -def chain : BuiltinDagNode; -def blockchain : BuiltinDagNode; -def ChainExpander : Expander<(chain Void, Void), []>; -def BlockChainExpander : Expander<(blockchain Void, Void), []>; - - -// Terminals... -def imm : BuiltinDagNode; -def frameidx : BuiltinDagNode; -def basicblock : BuiltinDagNode; - -// Arithmetic... -def plus : BuiltinDagNode; -def minus : BuiltinDagNode; -def times : BuiltinDagNode; -def sdiv : BuiltinDagNode; -def udiv : BuiltinDagNode; -def srem : BuiltinDagNode; -def urem : BuiltinDagNode; -def and : BuiltinDagNode; -def or : BuiltinDagNode; -def xor : BuiltinDagNode; - -// Comparisons... -def seteq : BuiltinDagNode; -def setne : BuiltinDagNode; -def setlt : BuiltinDagNode; -def setle : BuiltinDagNode; -def setgt : BuiltinDagNode; -def setge : BuiltinDagNode; - -def load : BuiltinDagNode; -//def store : BuiltinDagNode; - -// Other... -def ret : BuiltinDagNode; -def retvoid : BuiltinDagNode; -def br : BuiltinDagNode; -def brcond : BuiltinDagNode; - -def unspec1 : BuiltinDagNode; -def unspec2 : BuiltinDagNode; - //===----------------------------------------------------------------------===// -// DAG nonterminals definitions used by the instruction selector... +// Processor chip sets - These values represent each of the chip sets supported +// by the scheduler. Each Processor definition requires corresponding +// instruction itineraries. // -class Nonterminal { - dag Pattern = pattern; - bit BuiltIn = 0; +class Processor f> { + // Name - Chip set name. Used by command line (-mcpu=) to determine the + // appropriate target chip. + // + string Name = n; + + // ProcItin - The scheduling information for the target processor. + // + ProcessorItineraries ProcItin = pi; + + // Features - list of + list Features = f; } -*/ +//===----------------------------------------------------------------------===// +// Pull in the common support for DAG isel generation +// +include "../TargetSelectionDAG.td"