X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FTarget.td;h=4c846741caef0e362a030075c56760fa471c6ef5;hb=47622e37215429c20d8278ff57496d840811cc13;hp=fcfdf8d7db3e128bb496ba20ecdfdf32cf74b5ba;hpb=f338dd881fe6133d6835325a7feb88cf4a1a9414;p=oota-llvm.git diff --git a/lib/Target/Target.td b/lib/Target/Target.td index fcfdf8d7db3..4c846741cae 100644 --- a/lib/Target/Target.td +++ b/lib/Target/Target.td @@ -12,43 +12,8 @@ // //===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// -// Value types - These values correspond to the register types defined in the -// ValueTypes.h file. If you update anything here, you must update it there as -// well! -// -class ValueType { - string Namespace = "MVT"; - int Size = size; - int Value = value; -} - -def OtherVT: ValueType<0 , 0>; // "Other" value -def i1 : ValueType<1 , 1>; // One bit boolean value -def i8 : ValueType<8 , 2>; // 8-bit integer value -def i16 : ValueType<16 , 3>; // 16-bit integer value -def i32 : ValueType<32 , 4>; // 32-bit integer value -def i64 : ValueType<64 , 5>; // 64-bit integer value -def i128 : ValueType<128, 6>; // 128-bit integer value -def f32 : ValueType<32 , 7>; // 32-bit floating point value -def f64 : ValueType<64 , 8>; // 64-bit floating point value -def f80 : ValueType<80 , 9>; // 80-bit floating point value -def f128 : ValueType<128, 10>; // 128-bit floating point value -def FlagVT : ValueType<0 , 11>; // Condition code or machine flag -def isVoid : ValueType<0 , 12>; // Produces no value -def Vector : ValueType<0 , 13>; // Abstract vector value -def v8i8 : ValueType<64 , 14>; // 8 x i8 vector value -def v4i16 : ValueType<64 , 15>; // 4 x i16 vector value -def v2i32 : ValueType<64 , 16>; // 2 x i32 vector value -def v16i8 : ValueType<128, 17>; // 16 x i8 vector value -def v8i16 : ValueType<128, 18>; // 8 x i16 vector value -def v4i32 : ValueType<128, 19>; // 4 x i32 vector value -def v2i64 : ValueType<128, 20>; // 2 x i64 vector value -def v2f32 : ValueType<64, 21>; // 2 x f32 vector value -def v4f32 : ValueType<128, 22>; // 4 x f32 vector value -def v2f64 : ValueType<128, 23>; // 2 x f64 vector value +// Include all information about LLVM intrinsics. +include "llvm/Intrinsics.td" //===----------------------------------------------------------------------===// // Register file description - These classes are used to fill in the target @@ -78,6 +43,13 @@ class Register { // registers. // list Aliases = []; + + // DwarfNumber - Number used internally by gcc/gdb to identify the register. + // These values can be determined by locating the .h file in the + // directory llvmgcc/gcc/config// and looking for REGISTER_NAMES. The + // order of these names correspond to the enumeration used by gcc. A value of + // -1 indicates that the gcc number is undefined. + int DwarfNumber = -1; } // RegisterGroup - This can be used to define instances of Register which @@ -126,6 +98,20 @@ class RegisterClass regTypes, int alignment, } +//===----------------------------------------------------------------------===// +// DwarfRegNum - This class provides a mapping of the llvm register enumeration +// to the register numbering used by gcc and gdb. These values are used by a +// debug information writer (ex. DwarfWriter) to describe where values may be +// located during execution. +class DwarfRegNum { + // DwarfNumber - Number used internally by gcc/gdb to identify the register. + // These values can be determined by locating the .h file in the + // directory llvmgcc/gcc/config// and looking for REGISTER_NAMES. The + // order of these names correspond to the enumeration used by gcc. A value of + // -1 indicates that the gcc number is undefined. + int DwarfNumber = N; +} + //===----------------------------------------------------------------------===// // Pull in the common support for scheduling //