X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FTarget.td;h=a268e164107f2f745aa2e2c1bba9a29ba77966e9;hb=6fa1c051dc515b6fd1f9a26ac12fed985469bff5;hp=15213ce2831a86f30b60cd360ca2ee621f029662;hpb=a3ca3149f2b59c512c50aab330b5a0d8efddeffa;p=oota-llvm.git diff --git a/lib/Target/Target.td b/lib/Target/Target.td index 15213ce2831..a268e164107 100644 --- a/lib/Target/Target.td +++ b/lib/Target/Target.td @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -25,6 +25,7 @@ class RegisterClass; // Forward def // in the target machine. String n will become the "name" of the register. class Register { string Namespace = ""; + string AsmName = n; string Name = n; // SpillSize - If this value is set to a non-zero value, it is the size in @@ -49,12 +50,13 @@ class Register { // not [AX, AH, AL]. list SubRegs = []; - // DwarfNumber - Number used internally by gcc/gdb to identify the register. + // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. // These values can be determined by locating the .h file in the // directory llvmgcc/gcc/config// and looking for REGISTER_NAMES. The // order of these names correspond to the enumeration used by gcc. A value of - // -1 indicates that the gcc number is undefined. - int DwarfNumber = -1; + // -1 indicates that the gcc number is undefined and -2 that register number + // is invalid for this mode/flavour. + list DwarfNumbers = []; } // RegisterWithSubRegs - This can be used to define instances of Register which @@ -133,13 +135,14 @@ class RegisterClass regTypes, int alignment, // to the register numbering used by gcc and gdb. These values are used by a // debug information writer (ex. DwarfWriter) to describe where values may be // located during execution. -class DwarfRegNum { - // DwarfNumber - Number used internally by gcc/gdb to identify the register. +class DwarfRegNum Numbers> { + // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. // These values can be determined by locating the .h file in the // directory llvmgcc/gcc/config// and looking for REGISTER_NAMES. The // order of these names correspond to the enumeration used by gcc. A value of - // -1 indicates that the gcc number is undefined. - int DwarfNumber = N; + // -1 indicates that the gcc number is undefined and -2 that register number is + // invalid for this mode/flavour. + list DwarfNumbers = Numbers; } //===----------------------------------------------------------------------===// @@ -154,7 +157,6 @@ class Predicate; // Forward def // the Target/TargetInstrInfo.h file. // class Instruction { - string Name = ""; // The opcode string for this instruction string Namespace = ""; dag OutOperandList; // An dag containing the MI def operand list. @@ -185,10 +187,12 @@ class Instruction { // instruction. bit isReturn = 0; // Is this instruction a return instruction? bit isBranch = 0; // Is this instruction a branch instruction? + bit isIndirectBranch = 0; // Is this instruction an indirect branch? bit isBarrier = 0; // Can control flow fall through this instruction? bit isCall = 0; // Is this instruction a call instruction? - bit isLoad = 0; // Is this instruction a load instruction? - bit isStore = 0; // Is this instruction a store instruction? + bit isSimpleLoad = 0; // Is this just a load instruction? + bit mayLoad = 0; // Is it possible for this inst to read memory? + bit mayStore = 0; // Is it possible for this inst to write memory? bit isTwoAddress = 0; // Is this a two address instruction? bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? bit isCommutable = 0; // Is this 3 operand instruction commutable? @@ -199,7 +203,25 @@ class Instruction { bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help. bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? - + bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. + + // Side effect flags - When set, the flags have these meanings: + // + // hasSideEffects - The instruction has side effects that are not + // captured by any operands of the instruction or other flags. + // + // mayHaveSideEffects - Some instances of the instruction can have side + // effects. The virtual method "isReallySideEffectFree" is called to + // determine this. Load instructions are an example of where this is + // useful. In general, loads always have side effects. However, loads from + // constant pools don't. Individual back ends make this determination. + // + // neverHasSideEffects - Set on an instruction with no pattern if it has no + // side effects. + bit hasSideEffects = 0; + bit mayHaveSideEffects = 0; + bit neverHasSideEffects = 0; + InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. string Constraints = ""; // OperandConstraint, e.g. $src = $dst. @@ -243,6 +265,10 @@ def variable_ops; /// flags. But currently we have but one flag. def ptr_rc; +/// unknown definition - Mark this operand as being of unknown type, causing +/// it to be resolved by inference in the context it is used. +def unknown; + /// Operand Types - These provide the built-in operand types that may be used /// by a target. Targets can optionally provide their own operand types as /// needed, though this should not be needed for RISC targets. @@ -258,6 +284,9 @@ def i16imm : Operand; def i32imm : Operand; def i64imm : Operand; +def f32imm : Operand; +def f64imm : Operand; + /// zero_reg definition - Special node to stand for the zero register. /// def zero_reg; @@ -315,22 +344,46 @@ def INLINEASM : Instruction { } def LABEL : Instruction { let OutOperandList = (ops); - let InOperandList = (ops i32imm:$id); + let InOperandList = (ops i32imm:$id, i32imm:$flavor); let AsmString = ""; let Namespace = "TargetInstrInfo"; let hasCtrlDep = 1; } -def EXTRACT_SUBREG : Instruction { - let OutOperandList = (ops variable_ops); +def DECLARE : Instruction { + let OutOperandList = (ops); let InOperandList = (ops variable_ops); let AsmString = ""; let Namespace = "TargetInstrInfo"; + let hasCtrlDep = 1; +} +def EXTRACT_SUBREG : Instruction { + let OutOperandList = (ops unknown:$dst); + let InOperandList = (ops unknown:$supersrc, i32imm:$subidx); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; + let neverHasSideEffects = 1; } def INSERT_SUBREG : Instruction { - let OutOperandList = (ops variable_ops); - let InOperandList = (ops variable_ops); + let OutOperandList = (ops unknown:$dst); + let InOperandList = (ops unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; + let neverHasSideEffects = 1; + let Constraints = "$supersrc = $dst"; +} +def IMPLICIT_DEF : Instruction { + let OutOperandList = (ops unknown:$dst); + let InOperandList = (ops); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; + let neverHasSideEffects = 1; +} +def SUBREG_TO_REG : Instruction { + let OutOperandList = (ops unknown:$dst); + let InOperandList = (ops unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); let AsmString = ""; let Namespace = "TargetInstrInfo"; + let neverHasSideEffects = 1; } //===----------------------------------------------------------------------===//