X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FTarget.td;h=cebac7a263650b8b01f7ea5043b73025fe7a3c74;hb=2b5fab67c1a2d3ec1184c065e0a6bdaaaec9253a;hp=d1f3e7455b215232091055f4d8ee57c27fa56714;hpb=b228657acc4afbdc74dc523e9f465d08935f9e8d;p=oota-llvm.git diff --git a/lib/Target/Target.td b/lib/Target/Target.td index d1f3e7455b2..cebac7a2636 100644 --- a/lib/Target/Target.td +++ b/lib/Target/Target.td @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -12,41 +12,20 @@ // //===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// -// Value types - These values correspond to the register types defined in the -// ValueTypes.h file. If you update anything here, you must update it there as -// well! -// -class ValueType { - string Namespace = "MVT"; - int Size = size; - int Value = value; -} - -def OtherVT: ValueType<0 , 0>; // "Other" value -def i1 : ValueType<1 , 1>; // One bit boolean value -def i8 : ValueType<8 , 2>; // 8-bit integer value -def i16 : ValueType<16 , 3>; // 16-bit integer value -def i32 : ValueType<32 , 4>; // 32-bit integer value -def i64 : ValueType<64 , 5>; // 64-bit integer value -def i128 : ValueType<128, 5>; // 128-bit integer value -def f32 : ValueType<32 , 7>; // 32-bit floating point value -def f64 : ValueType<64 , 8>; // 64-bit floating point value -def f80 : ValueType<80 , 9>; // 80-bit floating point value -def f128 : ValueType<128, 9>; // 128-bit floating point value -def isVoid : ValueType<0 , 11>; // Produces no value +// Include all information about LLVM intrinsics. +include "llvm/Intrinsics.td" //===----------------------------------------------------------------------===// // Register file description - These classes are used to fill in the target -// description classes in llvm/Target/MRegisterInfo.h +// description classes. +class RegisterClass; // Forward def // Register - You should define one instance of this class for each register // in the target machine. String n will become the "name" of the register. -class RegisterBase { +class Register { string Namespace = ""; + string AsmName = n; string Name = n; // SpillSize - If this value is set to a non-zero value, it is the size in @@ -59,19 +38,46 @@ class RegisterBase { // spilling the register. Like SpillSize, this should only be explicitly // specified if the register is not in a register class. int SpillAlignment = 0; -} -class Register : RegisterBase { - list Aliases = []; + // Aliases - A list of registers that this register overlaps with. A read or + // modification of this register can potentially read or modify the aliased + // registers. + list Aliases = []; + + // SubRegs - A list of registers that are parts of this register. Note these + // are "immediate" sub-registers and the registers within the list do not + // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], + // not [AX, AH, AL]. + list SubRegs = []; + + // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. + // These values can be determined by locating the .h file in the + // directory llvmgcc/gcc/config// and looking for REGISTER_NAMES. The + // order of these names correspond to the enumeration used by gcc. A value of + // -1 indicates that the gcc number is undefined and -2 that register number + // is invalid for this mode/flavour. + list DwarfNumbers = []; } -// RegisterGroup - This can be used to define instances of Register which -// need to specify aliases. -// List "aliases" specifies which registers are aliased to this one. This -// allows the code generator to be careful not to put two values with +// RegisterWithSubRegs - This can be used to define instances of Register which +// need to specify sub-registers. +// List "subregs" specifies which registers are sub-registers to this one. This +// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. +// This allows the code generator to be careful not to put two values with // overlapping live ranges into registers which alias. -class RegisterGroup aliases> : Register { - let Aliases = aliases; +class RegisterWithSubRegs subregs> : Register { + let SubRegs = subregs; +} + +// SubRegSet - This can be used to define a specific mapping of registers to +// indices, for use as named subregs of a particular physical register. Each +// register in 'subregs' becomes an addressable subregister at index 'n' of the +// corresponding register in 'regs'. +class SubRegSet regs, list subregs> { + int index = n; + + list From = regs; + list To = subregs; } // RegisterClass - Now that all of the registers are defined, and aliases @@ -79,39 +85,82 @@ class RegisterGroup aliases> : Register { // register classes. This also defines the default allocation order of // registers by register allocators. // -class RegisterClass regList> { - // RegType - Specify the ValueType of the registers in this register class. - // Note that all registers in a register class must have the same ValueType. +class RegisterClass regTypes, int alignment, + list regList> { + string Namespace = namespace; + + // RegType - Specify the list ValueType of the registers in this register + // class. Note that all registers in a register class must have the same + // ValueTypes. This is a list because some targets permit storing different + // types in same register, for example vector values with 128-bit total size, + // but different count/size of items, like SSE on x86. // - ValueType RegType = regType; + list RegTypes = regTypes; + + // Size - Specify the spill size in bits of the registers. A default value of + // zero lets tablgen pick an appropriate size. + int Size = 0; // Alignment - Specify the alignment required of the registers when they are // stored or loaded to memory. // - int Size = RegType.Size; int Alignment = alignment; + // CopyCost - This value is used to specify the cost of copying a value + // between two registers in this register class. The default value is one + // meaning it takes a single instruction to perform the copying. A negative + // value means copying is extremely expensive or impossible. + int CopyCost = 1; + // MemberList - Specify which registers are in this class. If the // allocation_order_* method are not specified, this also defines the order of // allocation used by the register allocator. // list MemberList = regList; + + // SubClassList - Specify which register classes correspond to subregisters + // of this class. The order should be by subregister set index. + list SubRegClassList = []; + + // MethodProtos/MethodBodies - These members can be used to insert arbitrary + // code into a generated register class. The normal usage of this is to + // overload virtual methods. + code MethodProtos = [{}]; + code MethodBodies = [{}]; +} - // Methods - This member can be used to insert arbitrary code into a generated - // register class. The normal usage of this is to overload virtual methods. - code Methods = [{}]; + +//===----------------------------------------------------------------------===// +// DwarfRegNum - This class provides a mapping of the llvm register enumeration +// to the register numbering used by gcc and gdb. These values are used by a +// debug information writer (ex. DwarfWriter) to describe where values may be +// located during execution. +class DwarfRegNum Numbers> { + // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. + // These values can be determined by locating the .h file in the + // directory llvmgcc/gcc/config// and looking for REGISTER_NAMES. The + // order of these names correspond to the enumeration used by gcc. A value of + // -1 indicates that the gcc number is undefined and -2 that register number is + // invalid for this mode/flavour. + list DwarfNumbers = Numbers; } +//===----------------------------------------------------------------------===// +// Pull in the common support for scheduling +// +include "TargetSchedule.td" + +class Predicate; // Forward def //===----------------------------------------------------------------------===// // Instruction set description - These classes correspond to the C++ classes in // the Target/TargetInstrInfo.h file. // class Instruction { - string Name = ""; // The opcode string for this instruction string Namespace = ""; - dag OperandList; // An dag containing the MI operand list. + dag OutOperandList; // An dag containing the MI def operand list. + dag InOperandList; // An dag containing the MI use operand list. string AsmString = ""; // The .s format to print the instruction with. // Pattern - Set to the DAG pattern for this instruction, if we know of one, @@ -124,29 +173,103 @@ class Instruction { list Uses = []; // Default to using no non-operand registers list Defs = []; // Default to modifying no non-operand registers + // Predicates - List of predicates which will be turned into isel matching + // code. + list Predicates = []; + + // Code size. + int CodeSize = 0; + + // Added complexity passed onto matching pattern. + int AddedComplexity = 0; + // These bits capture information about the high-level semantics of the // instruction. bit isReturn = 0; // Is this instruction a return instruction? bit isBranch = 0; // Is this instruction a branch instruction? + bit isIndirectBranch = 0; // Is this instruction an indirect branch? bit isBarrier = 0; // Can control flow fall through this instruction? bit isCall = 0; // Is this instruction a call instruction? + bit isSimpleLoad = 0; // Is this just a load instruction? + bit mayLoad = 0; // Is it possible for this inst to read memory? + bit mayStore = 0; // Is it possible for this inst to write memory? + bit isImplicitDef = 0; // Is this instruction an implicit def instruction? bit isTwoAddress = 0; // Is this a two address instruction? + bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? + bit isCommutable = 0; // Is this 3 operand instruction commutable? bit isTerminator = 0; // Is this part of the terminator for a basic block? + bit isReMaterializable = 0; // Is this instruction re-materializable? + bit isPredicable = 0; // Is this instruction predicable? + bit hasDelaySlot = 0; // Does this instruction have an delay slot? + bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help. + bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? + bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? + + // Side effect flags - When set, the flags have these meanings: + // + // hasSideEffects - The instruction has side effects that are not + // captured by any operands of the instruction or other flags. + // mayHaveSideEffects - Some instances of the instruction can have side + // effects. The virtual method "isReallySideEffectFree" is called to + // determine this. Load instructions are an example of where this is + // useful. In general, loads always have side effects. However, loads from + // constant pools don't. Individual back ends make this determination. + // neverHasSideEffects - Set on an instruction with no pattern if it has no + // side effects. + bit hasSideEffects = 0; + bit mayHaveSideEffects = 0; + bit neverHasSideEffects = 0; + + InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. + + string Constraints = ""; // OperandConstraint, e.g. $src = $dst. + + /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not + /// be encoded into the output machineinstr. + string DisableEncoding = ""; +} + +/// Predicates - These are extra conditionals which are turned into instruction +/// selector matching code. Currently each predicate is just a string. +class Predicate { + string CondString = cond; } +/// NoHonorSignDependentRounding - This predicate is true if support for +/// sign-dependent-rounding is not enabled. +def NoHonorSignDependentRounding + : Predicate<"!HonorSignDependentRoundingFPMath()">; + +class Requires preds> { + list Predicates = preds; +} /// ops definition - This is just a simple marker used to identify the operands -/// list for an instruction. This should be used like this: -/// (ops R32:$dst, R32:$src) or something similar. +/// list for an instruction. outs and ins are identical both syntatically and +/// semantically, they are used to define def operands and use operands to +/// improve readibility. This should be used like this: +/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. def ops; +def outs; +def ins; + +/// variable_ops definition - Mark this instruction as taking a variable number +/// of operands. +def variable_ops; + +/// ptr_rc definition - Mark this operand as being a pointer value whose +/// register class is resolved dynamically via a callback to TargetInstrInfo. +/// FIXME: We should probably change this to a class which contain a list of +/// flags. But currently we have but one flag. +def ptr_rc; /// Operand Types - These provide the built-in operand types that may be used /// by a target. Targets can optionally provide their own operand types as /// needed, though this should not be needed for RISC targets. class Operand { - int NumMIOperands = 1; ValueType Type = ty; string PrintMethod = "printOperand"; + dag MIOperandInfo = (ops); } def i1imm : Operand; @@ -155,18 +278,91 @@ def i16imm : Operand; def i32imm : Operand; def i64imm : Operand; +def f32imm : Operand; +def f64imm : Operand; + +/// zero_reg definition - Special node to stand for the zero register. +/// +def zero_reg; + +/// PredicateOperand - This can be used to define a predicate operand for an +/// instruction. OpTypes specifies the MIOperandInfo for the operand, and +/// AlwaysVal specifies the value of this predicate when set to "always +/// execute". +class PredicateOperand + : Operand { + let MIOperandInfo = OpTypes; + dag DefaultOps = AlwaysVal; +} + +/// OptionalDefOperand - This is used to define a optional definition operand +/// for an instruction. DefaultOps is the register the operand represents if none +/// is supplied, e.g. zero_reg. +class OptionalDefOperand + : Operand { + let MIOperandInfo = OpTypes; + dag DefaultOps = defaultops; +} + + // InstrInfo - This class should only be instantiated once to provide parameters // which are global to the the target machine. // class InstrInfo { - Instruction PHIInst; - // If the target wants to associate some target-specific information with each // instruction, it should provide these two lists to indicate how to assemble // the target specific information into the 32 bits available. // list TSFlagsFields = []; list TSFlagsShifts = []; + + // Target can specify its instructions in either big or little-endian formats. + // For instance, while both Sparc and PowerPC are big-endian platforms, the + // Sparc manual specifies its instructions in the format [31..0] (big), while + // PowerPC specifies them using the format [0..31] (little). + bit isLittleEndianEncoding = 0; +} + +// Standard Instructions. +def PHI : Instruction { + let OutOperandList = (ops); + let InOperandList = (ops variable_ops); + let AsmString = "PHINODE"; + let Namespace = "TargetInstrInfo"; +} +def INLINEASM : Instruction { + let OutOperandList = (ops); + let InOperandList = (ops variable_ops); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; +} +def LABEL : Instruction { + let OutOperandList = (ops); + let InOperandList = (ops i32imm:$id, i32imm:$flavor); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; + let hasCtrlDep = 1; +} +def DECLARE : Instruction { + let OutOperandList = (ops); + let InOperandList = (ops variable_ops); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; + let hasCtrlDep = 1; +} +def EXTRACT_SUBREG : Instruction { + let OutOperandList = (ops variable_ops); + let InOperandList = (ops variable_ops); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; + let neverHasSideEffects = 1; +} +def INSERT_SUBREG : Instruction { + let OutOperandList = (ops variable_ops); + let InOperandList = (ops variable_ops); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; + let neverHasSideEffects = 1; } //===----------------------------------------------------------------------===// @@ -185,6 +381,14 @@ class AsmWriter { // InstFormatName - AsmWriters can specify the name of the format string to // print instructions with. string InstFormatName = "AsmString"; + + // Variant - AsmWriters can be of multiple different variants. Variants are + // used to support targets that need to emit assembly code in ways that are + // mostly the same for different targets, but have minor differences in + // syntax. If the asmstring contains {|} characters in them, this integer + // will specify which alternative to use. For example "{x|y|z}" with Variant + // == 1, will expand to "y". + int Variant = 0; } def DefaultAsmWriter : AsmWriter; @@ -193,109 +397,67 @@ def DefaultAsmWriter : AsmWriter; // Target - This class contains the "global" target information // class Target { - // CalleeSavedRegisters - As you might guess, this is a list of the callee - // saved registers for a target. - list CalleeSavedRegisters = []; - - // PointerType - Specify the value type to be used to represent pointers in - // this target. Typically this is an i32 or i64 type. - ValueType PointerType; - // InstructionSet - Instruction set description for this target. InstrInfo InstructionSet; - // AssemblyWriter - The AsmWriter instance to use for this target. - AsmWriter AssemblyWriter = DefaultAsmWriter; + // AssemblyWriters - The AsmWriter instances available for this target. + list AssemblyWriters = [DefaultAsmWriter]; } - //===----------------------------------------------------------------------===// -// DAG node definitions used by the instruction selector. +// SubtargetFeature - A characteristic of the chip set. // -// NOTE: all of this is a work-in-progress and should be ignored for now. -// -/* -class Expander result> { - dag Pattern = pattern; - list Result = result; -} +class SubtargetFeature i = []> { + // Name - Feature name. Used by command line (-mattr=) to determine the + // appropriate target chip. + // + string Name = n; + + // Attribute - Attribute to be set by feature. + // + string Attribute = a; + + // Value - Value the attribute to be set to by feature. + // + string Value = v; + + // Desc - Feature description. Used by command line (-mattr=) to display help + // information. + // + string Desc = d; -class DagNodeValType; -def DNVT_any : DagNodeValType; // No constraint on tree node -def DNVT_void : DagNodeValType; // Tree node always returns void -def DNVT_val : DagNodeValType; // A non-void type -def DNVT_arg0 : DagNodeValType; // Tree node returns same type as Arg0 -def DNVT_arg1 : DagNodeValType; // Tree node returns same type as Arg1 -def DNVT_ptr : DagNodeValType; // The target pointer type -def DNVT_i8 : DagNodeValType; // Always have an i8 value - -class DagNode args> { - DagNodeValType RetType = ret; - list ArgTypes = args; - string EnumName = ?; + // Implies - Features that this feature implies are present. If one of those + // features isn't set, then this one shouldn't be set either. + // + list Implies = i; } -// BuiltinDagNodes are built into the instruction selector and correspond to -// enum values. -class BuiltinDagNode Args, - string Ename> : DagNode { - let EnumName = Ename; +//===----------------------------------------------------------------------===// +// Processor chip sets - These values represent each of the chip sets supported +// by the scheduler. Each Processor definition requires corresponding +// instruction itineraries. +// +class Processor f> { + // Name - Chip set name. Used by command line (-mcpu=) to determine the + // appropriate target chip. + // + string Name = n; + + // ProcItin - The scheduling information for the target processor. + // + ProcessorItineraries ProcItin = pi; + + // Features - list of + list Features = f; } -// Magic nodes... -def Void : RegisterClass { let isDummyClass = 1; } -def set : DagNode; -def chain : BuiltinDagNode; -def blockchain : BuiltinDagNode; -def ChainExpander : Expander<(chain Void, Void), []>; -def BlockChainExpander : Expander<(blockchain Void, Void), []>; - - -// Terminals... -def imm : BuiltinDagNode; -def frameidx : BuiltinDagNode; -def basicblock : BuiltinDagNode; - -// Arithmetic... -def plus : BuiltinDagNode; -def minus : BuiltinDagNode; -def times : BuiltinDagNode; -def sdiv : BuiltinDagNode; -def udiv : BuiltinDagNode; -def srem : BuiltinDagNode; -def urem : BuiltinDagNode; -def and : BuiltinDagNode; -def or : BuiltinDagNode; -def xor : BuiltinDagNode; - -// Comparisons... -def seteq : BuiltinDagNode; -def setne : BuiltinDagNode; -def setlt : BuiltinDagNode; -def setle : BuiltinDagNode; -def setgt : BuiltinDagNode; -def setge : BuiltinDagNode; - -def load : BuiltinDagNode; -//def store : BuiltinDagNode; - -// Other... -def ret : BuiltinDagNode; -def retvoid : BuiltinDagNode; -def br : BuiltinDagNode; -def brcond : BuiltinDagNode; - -def unspec1 : BuiltinDagNode; -def unspec2 : BuiltinDagNode; - //===----------------------------------------------------------------------===// -// DAG nonterminals definitions used by the instruction selector... +// Pull in the common support for calling conventions. // -class Nonterminal { - dag Pattern = pattern; - bit BuiltIn = 0; -} +include "TargetCallingConv.td" -*/ +//===----------------------------------------------------------------------===// +// Pull in the common support for DAG isel generation. +// +include "TargetSelectionDAG.td"