X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FTarget.td;h=cebac7a263650b8b01f7ea5043b73025fe7a3c74;hb=e6be34a53ecbe8c2ff9f0793b13d847e94c0de91;hp=3d6d8363e45de3ceb9282715b99f21f898b26b30;hpb=e496d78f16060ec4523a415bd62c8f010624dbac;p=oota-llvm.git diff --git a/lib/Target/Target.td b/lib/Target/Target.td index 3d6d8363e45..cebac7a2636 100644 --- a/lib/Target/Target.td +++ b/lib/Target/Target.td @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -25,6 +25,7 @@ class RegisterClass; // Forward def // in the target machine. String n will become the "name" of the register. class Register { string Namespace = ""; + string AsmName = n; string Name = n; // SpillSize - If this value is set to a non-zero value, it is the size in @@ -49,12 +50,13 @@ class Register { // not [AX, AH, AL]. list SubRegs = []; - // DwarfNumber - Number used internally by gcc/gdb to identify the register. + // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. // These values can be determined by locating the .h file in the // directory llvmgcc/gcc/config// and looking for REGISTER_NAMES. The // order of these names correspond to the enumeration used by gcc. A value of - // -1 indicates that the gcc number is undefined. - int DwarfNumber = -1; + // -1 indicates that the gcc number is undefined and -2 that register number + // is invalid for this mode/flavour. + list DwarfNumbers = []; } // RegisterWithSubRegs - This can be used to define instances of Register which @@ -104,6 +106,12 @@ class RegisterClass regTypes, int alignment, // int Alignment = alignment; + // CopyCost - This value is used to specify the cost of copying a value + // between two registers in this register class. The default value is one + // meaning it takes a single instruction to perform the copying. A negative + // value means copying is extremely expensive or impossible. + int CopyCost = 1; + // MemberList - Specify which registers are in this class. If the // allocation_order_* method are not specified, this also defines the order of // allocation used by the register allocator. @@ -127,13 +135,14 @@ class RegisterClass regTypes, int alignment, // to the register numbering used by gcc and gdb. These values are used by a // debug information writer (ex. DwarfWriter) to describe where values may be // located during execution. -class DwarfRegNum { - // DwarfNumber - Number used internally by gcc/gdb to identify the register. +class DwarfRegNum Numbers> { + // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. // These values can be determined by locating the .h file in the // directory llvmgcc/gcc/config// and looking for REGISTER_NAMES. The // order of these names correspond to the enumeration used by gcc. A value of - // -1 indicates that the gcc number is undefined. - int DwarfNumber = N; + // -1 indicates that the gcc number is undefined and -2 that register number is + // invalid for this mode/flavour. + list DwarfNumbers = Numbers; } //===----------------------------------------------------------------------===// @@ -148,10 +157,10 @@ class Predicate; // Forward def // the Target/TargetInstrInfo.h file. // class Instruction { - string Name = ""; // The opcode string for this instruction string Namespace = ""; - dag OperandList; // An dag containing the MI operand list. + dag OutOperandList; // An dag containing the MI def operand list. + dag InOperandList; // An dag containing the MI use operand list. string AsmString = ""; // The .s format to print the instruction with. // Pattern - Set to the DAG pattern for this instruction, if we know of one, @@ -178,10 +187,13 @@ class Instruction { // instruction. bit isReturn = 0; // Is this instruction a return instruction? bit isBranch = 0; // Is this instruction a branch instruction? + bit isIndirectBranch = 0; // Is this instruction an indirect branch? bit isBarrier = 0; // Can control flow fall through this instruction? bit isCall = 0; // Is this instruction a call instruction? - bit isLoad = 0; // Is this instruction a load instruction? - bit isStore = 0; // Is this instruction a store instruction? + bit isSimpleLoad = 0; // Is this just a load instruction? + bit mayLoad = 0; // Is it possible for this inst to read memory? + bit mayStore = 0; // Is it possible for this inst to write memory? + bit isImplicitDef = 0; // Is this instruction an implicit def instruction? bit isTwoAddress = 0; // Is this a two address instruction? bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? bit isCommutable = 0; // Is this 3 operand instruction commutable? @@ -191,9 +203,22 @@ class Instruction { bit hasDelaySlot = 0; // Does this instruction have an delay slot? bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help. bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? - bit noResults = 0; // Does this instruction produce no results? - bit clobbersPred = 0; // Does it clobbers condition code / predicate? bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? + + // Side effect flags - When set, the flags have these meanings: + // + // hasSideEffects - The instruction has side effects that are not + // captured by any operands of the instruction or other flags. + // mayHaveSideEffects - Some instances of the instruction can have side + // effects. The virtual method "isReallySideEffectFree" is called to + // determine this. Load instructions are an example of where this is + // useful. In general, loads always have side effects. However, loads from + // constant pools don't. Individual back ends make this determination. + // neverHasSideEffects - Set on an instruction with no pattern if it has no + // side effects. + bit hasSideEffects = 0; + bit mayHaveSideEffects = 0; + bit neverHasSideEffects = 0; InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. @@ -204,13 +229,6 @@ class Instruction { string DisableEncoding = ""; } -/// Imp - Helper class for specifying the implicit uses/defs set for an -/// instruction. -class Imp uses, list defs> { - list Uses = uses; - list Defs = defs; -} - /// Predicates - These are extra conditionals which are turned into instruction /// selector matching code. Currently each predicate is just a string. class Predicate { @@ -227,9 +245,13 @@ class Requires preds> { } /// ops definition - This is just a simple marker used to identify the operands -/// list for an instruction. This should be used like this: -/// (ops R32:$dst, R32:$src) or something similar. +/// list for an instruction. outs and ins are identical both syntatically and +/// semantically, they are used to define def operands and use operands to +/// improve readibility. This should be used like this: +/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. def ops; +def outs; +def ins; /// variable_ops definition - Mark this instruction as taking a variable number /// of operands. @@ -256,6 +278,9 @@ def i16imm : Operand; def i32imm : Operand; def i64imm : Operand; +def f32imm : Operand; +def f64imm : Operand; + /// zero_reg definition - Special node to stand for the zero register. /// def zero_reg; @@ -263,20 +288,13 @@ def zero_reg; /// PredicateOperand - This can be used to define a predicate operand for an /// instruction. OpTypes specifies the MIOperandInfo for the operand, and /// AlwaysVal specifies the value of this predicate when set to "always -/// execute". If isImmutable is true, then the operand should not change -/// after instruction selection. +/// execute". class PredicateOperand : Operand { let MIOperandInfo = OpTypes; - bit isImmutable = 0; dag DefaultOps = AlwaysVal; } -class ImmutablePredicateOperand - : PredicateOperand { - let isImmutable = 1; -} - /// OptionalDefOperand - This is used to define a optional definition operand /// for an instruction. DefaultOps is the register the operand represents if none /// is supplied, e.g. zero_reg. @@ -307,21 +325,45 @@ class InstrInfo { // Standard Instructions. def PHI : Instruction { - let OperandList = (ops variable_ops); + let OutOperandList = (ops); + let InOperandList = (ops variable_ops); let AsmString = "PHINODE"; let Namespace = "TargetInstrInfo"; } def INLINEASM : Instruction { - let OperandList = (ops variable_ops); + let OutOperandList = (ops); + let InOperandList = (ops variable_ops); let AsmString = ""; let Namespace = "TargetInstrInfo"; } def LABEL : Instruction { - let OperandList = (ops i32imm:$id); + let OutOperandList = (ops); + let InOperandList = (ops i32imm:$id, i32imm:$flavor); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; + let hasCtrlDep = 1; +} +def DECLARE : Instruction { + let OutOperandList = (ops); + let InOperandList = (ops variable_ops); let AsmString = ""; let Namespace = "TargetInstrInfo"; let hasCtrlDep = 1; } +def EXTRACT_SUBREG : Instruction { + let OutOperandList = (ops variable_ops); + let InOperandList = (ops variable_ops); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; + let neverHasSideEffects = 1; +} +def INSERT_SUBREG : Instruction { + let OutOperandList = (ops variable_ops); + let InOperandList = (ops variable_ops); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; + let neverHasSideEffects = 1; +} //===----------------------------------------------------------------------===// // AsmWriter - This class can be implemented by targets that need to customize