X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FTarget.td;h=cebac7a263650b8b01f7ea5043b73025fe7a3c74;hb=e6be34a53ecbe8c2ff9f0793b13d847e94c0de91;hp=fcfdf8d7db3e128bb496ba20ecdfdf32cf74b5ba;hpb=f338dd881fe6133d6835325a7feb88cf4a1a9414;p=oota-llvm.git diff --git a/lib/Target/Target.td b/lib/Target/Target.td index fcfdf8d7db3..cebac7a2636 100644 --- a/lib/Target/Target.td +++ b/lib/Target/Target.td @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -12,43 +12,8 @@ // //===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// -// Value types - These values correspond to the register types defined in the -// ValueTypes.h file. If you update anything here, you must update it there as -// well! -// -class ValueType { - string Namespace = "MVT"; - int Size = size; - int Value = value; -} - -def OtherVT: ValueType<0 , 0>; // "Other" value -def i1 : ValueType<1 , 1>; // One bit boolean value -def i8 : ValueType<8 , 2>; // 8-bit integer value -def i16 : ValueType<16 , 3>; // 16-bit integer value -def i32 : ValueType<32 , 4>; // 32-bit integer value -def i64 : ValueType<64 , 5>; // 64-bit integer value -def i128 : ValueType<128, 6>; // 128-bit integer value -def f32 : ValueType<32 , 7>; // 32-bit floating point value -def f64 : ValueType<64 , 8>; // 64-bit floating point value -def f80 : ValueType<80 , 9>; // 80-bit floating point value -def f128 : ValueType<128, 10>; // 128-bit floating point value -def FlagVT : ValueType<0 , 11>; // Condition code or machine flag -def isVoid : ValueType<0 , 12>; // Produces no value -def Vector : ValueType<0 , 13>; // Abstract vector value -def v8i8 : ValueType<64 , 14>; // 8 x i8 vector value -def v4i16 : ValueType<64 , 15>; // 4 x i16 vector value -def v2i32 : ValueType<64 , 16>; // 2 x i32 vector value -def v16i8 : ValueType<128, 17>; // 16 x i8 vector value -def v8i16 : ValueType<128, 18>; // 8 x i16 vector value -def v4i32 : ValueType<128, 19>; // 4 x i32 vector value -def v2i64 : ValueType<128, 20>; // 2 x i64 vector value -def v2f32 : ValueType<64, 21>; // 2 x f32 vector value -def v4f32 : ValueType<128, 22>; // 4 x f32 vector value -def v2f64 : ValueType<128, 23>; // 2 x f64 vector value +// Include all information about LLVM intrinsics. +include "llvm/Intrinsics.td" //===----------------------------------------------------------------------===// // Register file description - These classes are used to fill in the target @@ -60,6 +25,7 @@ class RegisterClass; // Forward def // in the target machine. String n will become the "name" of the register. class Register { string Namespace = ""; + string AsmName = n; string Name = n; // SpillSize - If this value is set to a non-zero value, it is the size in @@ -74,19 +40,44 @@ class Register { int SpillAlignment = 0; // Aliases - A list of registers that this register overlaps with. A read or - // modification of this register can potentially read or modifie the aliased + // modification of this register can potentially read or modify the aliased // registers. - // list Aliases = []; + + // SubRegs - A list of registers that are parts of this register. Note these + // are "immediate" sub-registers and the registers within the list do not + // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], + // not [AX, AH, AL]. + list SubRegs = []; + + // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. + // These values can be determined by locating the .h file in the + // directory llvmgcc/gcc/config// and looking for REGISTER_NAMES. The + // order of these names correspond to the enumeration used by gcc. A value of + // -1 indicates that the gcc number is undefined and -2 that register number + // is invalid for this mode/flavour. + list DwarfNumbers = []; } -// RegisterGroup - This can be used to define instances of Register which -// need to specify aliases. -// List "aliases" specifies which registers are aliased to this one. This -// allows the code generator to be careful not to put two values with +// RegisterWithSubRegs - This can be used to define instances of Register which +// need to specify sub-registers. +// List "subregs" specifies which registers are sub-registers to this one. This +// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. +// This allows the code generator to be careful not to put two values with // overlapping live ranges into registers which alias. -class RegisterGroup aliases> : Register { - let Aliases = aliases; +class RegisterWithSubRegs subregs> : Register { + let SubRegs = subregs; +} + +// SubRegSet - This can be used to define a specific mapping of registers to +// indices, for use as named subregs of a particular physical register. Each +// register in 'subregs' becomes an addressable subregister at index 'n' of the +// corresponding register in 'regs'. +class SubRegSet regs, list subregs> { + int index = n; + + list From = regs; + list To = subregs; } // RegisterClass - Now that all of the registers are defined, and aliases @@ -98,8 +89,11 @@ class RegisterClass regTypes, int alignment, list regList> { string Namespace = namespace; - // RegType - Specify the ValueType of the registers in this register class. - // Note that all registers in a register class must have the same ValueType. + // RegType - Specify the list ValueType of the registers in this register + // class. Note that all registers in a register class must have the same + // ValueTypes. This is a list because some targets permit storing different + // types in same register, for example vector values with 128-bit total size, + // but different count/size of items, like SSE on x86. // list RegTypes = regTypes; @@ -112,11 +106,21 @@ class RegisterClass regTypes, int alignment, // int Alignment = alignment; + // CopyCost - This value is used to specify the cost of copying a value + // between two registers in this register class. The default value is one + // meaning it takes a single instruction to perform the copying. A negative + // value means copying is extremely expensive or impossible. + int CopyCost = 1; + // MemberList - Specify which registers are in this class. If the // allocation_order_* method are not specified, this also defines the order of // allocation used by the register allocator. // list MemberList = regList; + + // SubClassList - Specify which register classes correspond to subregisters + // of this class. The order should be by subregister set index. + list SubRegClassList = []; // MethodProtos/MethodBodies - These members can be used to insert arbitrary // code into a generated register class. The normal usage of this is to @@ -126,10 +130,25 @@ class RegisterClass regTypes, int alignment, } +//===----------------------------------------------------------------------===// +// DwarfRegNum - This class provides a mapping of the llvm register enumeration +// to the register numbering used by gcc and gdb. These values are used by a +// debug information writer (ex. DwarfWriter) to describe where values may be +// located during execution. +class DwarfRegNum Numbers> { + // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. + // These values can be determined by locating the .h file in the + // directory llvmgcc/gcc/config// and looking for REGISTER_NAMES. The + // order of these names correspond to the enumeration used by gcc. A value of + // -1 indicates that the gcc number is undefined and -2 that register number is + // invalid for this mode/flavour. + list DwarfNumbers = Numbers; +} + //===----------------------------------------------------------------------===// // Pull in the common support for scheduling // -include "../TargetSchedule.td" +include "TargetSchedule.td" class Predicate; // Forward def @@ -138,10 +157,10 @@ class Predicate; // Forward def // the Target/TargetInstrInfo.h file. // class Instruction { - string Name = ""; // The opcode string for this instruction string Namespace = ""; - dag OperandList; // An dag containing the MI operand list. + dag OutOperandList; // An dag containing the MI def operand list. + dag InOperandList; // An dag containing the MI use operand list. string AsmString = ""; // The .s format to print the instruction with. // Pattern - Set to the DAG pattern for this instruction, if we know of one, @@ -158,24 +177,56 @@ class Instruction { // code. list Predicates = []; + // Code size. + int CodeSize = 0; + + // Added complexity passed onto matching pattern. + int AddedComplexity = 0; + // These bits capture information about the high-level semantics of the // instruction. bit isReturn = 0; // Is this instruction a return instruction? bit isBranch = 0; // Is this instruction a branch instruction? + bit isIndirectBranch = 0; // Is this instruction an indirect branch? bit isBarrier = 0; // Can control flow fall through this instruction? bit isCall = 0; // Is this instruction a call instruction? - bit isLoad = 0; // Is this instruction a load instruction? - bit isStore = 0; // Is this instruction a store instruction? + bit isSimpleLoad = 0; // Is this just a load instruction? + bit mayLoad = 0; // Is it possible for this inst to read memory? + bit mayStore = 0; // Is it possible for this inst to write memory? + bit isImplicitDef = 0; // Is this instruction an implicit def instruction? bit isTwoAddress = 0; // Is this a two address instruction? bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? bit isCommutable = 0; // Is this 3 operand instruction commutable? bit isTerminator = 0; // Is this part of the terminator for a basic block? + bit isReMaterializable = 0; // Is this instruction re-materializable? + bit isPredicable = 0; // Is this instruction predicable? bit hasDelaySlot = 0; // Does this instruction have an delay slot? bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help. bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? - bit noResults = 0; // Does this instruction produce no results? + bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? + + // Side effect flags - When set, the flags have these meanings: + // + // hasSideEffects - The instruction has side effects that are not + // captured by any operands of the instruction or other flags. + // mayHaveSideEffects - Some instances of the instruction can have side + // effects. The virtual method "isReallySideEffectFree" is called to + // determine this. Load instructions are an example of where this is + // useful. In general, loads always have side effects. However, loads from + // constant pools don't. Individual back ends make this determination. + // neverHasSideEffects - Set on an instruction with no pattern if it has no + // side effects. + bit hasSideEffects = 0; + bit mayHaveSideEffects = 0; + bit neverHasSideEffects = 0; InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. + + string Constraints = ""; // OperandConstraint, e.g. $src = $dst. + + /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not + /// be encoded into the output machineinstr. + string DisableEncoding = ""; } /// Predicates - These are extra conditionals which are turned into instruction @@ -184,26 +235,40 @@ class Predicate { string CondString = cond; } +/// NoHonorSignDependentRounding - This predicate is true if support for +/// sign-dependent-rounding is not enabled. +def NoHonorSignDependentRounding + : Predicate<"!HonorSignDependentRoundingFPMath()">; + class Requires preds> { list Predicates = preds; } /// ops definition - This is just a simple marker used to identify the operands -/// list for an instruction. This should be used like this: -/// (ops R32:$dst, R32:$src) or something similar. +/// list for an instruction. outs and ins are identical both syntatically and +/// semantically, they are used to define def operands and use operands to +/// improve readibility. This should be used like this: +/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. def ops; +def outs; +def ins; /// variable_ops definition - Mark this instruction as taking a variable number /// of operands. def variable_ops; +/// ptr_rc definition - Mark this operand as being a pointer value whose +/// register class is resolved dynamically via a callback to TargetInstrInfo. +/// FIXME: We should probably change this to a class which contain a list of +/// flags. But currently we have but one flag. +def ptr_rc; + /// Operand Types - These provide the built-in operand types that may be used /// by a target. Targets can optionally provide their own operand types as /// needed, though this should not be needed for RISC targets. class Operand { ValueType Type = ty; string PrintMethod = "printOperand"; - int NumMIOperands = 1; dag MIOperandInfo = (ops); } @@ -213,6 +278,33 @@ def i16imm : Operand; def i32imm : Operand; def i64imm : Operand; +def f32imm : Operand; +def f64imm : Operand; + +/// zero_reg definition - Special node to stand for the zero register. +/// +def zero_reg; + +/// PredicateOperand - This can be used to define a predicate operand for an +/// instruction. OpTypes specifies the MIOperandInfo for the operand, and +/// AlwaysVal specifies the value of this predicate when set to "always +/// execute". +class PredicateOperand + : Operand { + let MIOperandInfo = OpTypes; + dag DefaultOps = AlwaysVal; +} + +/// OptionalDefOperand - This is used to define a optional definition operand +/// for an instruction. DefaultOps is the register the operand represents if none +/// is supplied, e.g. zero_reg. +class OptionalDefOperand + : Operand { + let MIOperandInfo = OpTypes; + dag DefaultOps = defaultops; +} + + // InstrInfo - This class should only be instantiated once to provide parameters // which are global to the the target machine. // @@ -233,12 +325,44 @@ class InstrInfo { // Standard Instructions. def PHI : Instruction { - let OperandList = (ops variable_ops); + let OutOperandList = (ops); + let InOperandList = (ops variable_ops); let AsmString = "PHINODE"; + let Namespace = "TargetInstrInfo"; } def INLINEASM : Instruction { - let OperandList = (ops variable_ops); + let OutOperandList = (ops); + let InOperandList = (ops variable_ops); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; +} +def LABEL : Instruction { + let OutOperandList = (ops); + let InOperandList = (ops i32imm:$id, i32imm:$flavor); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; + let hasCtrlDep = 1; +} +def DECLARE : Instruction { + let OutOperandList = (ops); + let InOperandList = (ops variable_ops); let AsmString = ""; + let Namespace = "TargetInstrInfo"; + let hasCtrlDep = 1; +} +def EXTRACT_SUBREG : Instruction { + let OutOperandList = (ops variable_ops); + let InOperandList = (ops variable_ops); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; + let neverHasSideEffects = 1; +} +def INSERT_SUBREG : Instruction { + let OutOperandList = (ops variable_ops); + let InOperandList = (ops variable_ops); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; + let neverHasSideEffects = 1; } //===----------------------------------------------------------------------===// @@ -273,14 +397,6 @@ def DefaultAsmWriter : AsmWriter; // Target - This class contains the "global" target information // class Target { - // CalleeSavedRegisters - As you might guess, this is a list of the callee - // saved registers for a target. - list CalleeSavedRegisters = []; - - // PointerType - Specify the value type to be used to represent pointers in - // this target. Typically this is an i32 or i64 type. - ValueType PointerType; - // InstructionSet - Instruction set description for this target. InstrInfo InstructionSet; @@ -291,7 +407,8 @@ class Target { //===----------------------------------------------------------------------===// // SubtargetFeature - A characteristic of the chip set. // -class SubtargetFeature { +class SubtargetFeature i = []> { // Name - Feature name. Used by command line (-mattr=) to determine the // appropriate target chip. // @@ -309,6 +426,11 @@ class SubtargetFeature { // information. // string Desc = d; + + // Implies - Features that this feature implies are present. If one of those + // features isn't set, then this one shouldn't be set either. + // + list Implies = i; } //===----------------------------------------------------------------------===// @@ -331,6 +453,11 @@ class Processor f> { } //===----------------------------------------------------------------------===// -// Pull in the common support for DAG isel generation +// Pull in the common support for calling conventions. +// +include "TargetCallingConv.td" + +//===----------------------------------------------------------------------===// +// Pull in the common support for DAG isel generation. // -include "../TargetSelectionDAG.td" +include "TargetSelectionDAG.td"