X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FTargetInstrInfo.cpp;h=10a5cdb6247a9fb44aa02a660203960c72d6f2e1;hb=6fa1c051dc515b6fd1f9a26ac12fed985469bff5;hp=0ee891698f32294925555704f051eb1c111ded78;hpb=f73823000e2d5d6e1cf65bdf5a107297e18d35fb;p=oota-llvm.git

diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp
index 0ee891698f3..10a5cdb6247 100644
--- a/lib/Target/TargetInstrInfo.cpp
+++ b/lib/Target/TargetInstrInfo.cpp
@@ -12,15 +12,14 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/Constant.h"
 #include "llvm/DerivedTypes.h"
 using namespace llvm;
 
 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
 /// dest operand. Returns -1 if there isn't one.
-int TargetInstrDescriptor::findTiedToSrcOperand(unsigned OpNum) const {
-  for (unsigned i = 0, e = numOperands; i != e; ++i) {
+int TargetInstrDesc::findTiedToSrcOperand(unsigned OpNum) const {
+  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     if (i == OpNum)
       continue;
     if (getOperandConstraint(i, TOI::TIED_TO) == (int)OpNum)
@@ -30,64 +29,22 @@ int TargetInstrDescriptor::findTiedToSrcOperand(unsigned OpNum) const {
 }
 
 
-TargetInstrInfo::TargetInstrInfo(const TargetInstrDescriptor* Desc,
+TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc,
                                  unsigned numOpcodes)
-  : desc(Desc), NumOpcodes(numOpcodes) {
+  : Descriptors(Desc), NumOpcodes(numOpcodes) {
 }
 
 TargetInstrInfo::~TargetInstrInfo() {
 }
 
-// commuteInstruction - The default implementation of this method just exchanges
-// operand 1 and 2.
-MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const {
-  assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
-         "This only knows how to commute register operands so far");
-  unsigned Reg1 = MI->getOperand(1).getReg();
-  unsigned Reg2 = MI->getOperand(2).getReg();
-  bool Reg1IsKill = MI->getOperand(1).isKill();
-  bool Reg2IsKill = MI->getOperand(2).isKill();
-  MI->getOperand(2).setReg(Reg1);
-  MI->getOperand(1).setReg(Reg2);
-  MI->getOperand(2).setIsKill(Reg1IsKill);
-  MI->getOperand(1).setIsKill(Reg2IsKill);
-  return MI;
-}
-
-bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
-                                const std::vector<MachineOperand> &Pred) const {
-  bool MadeChange = false;
-  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
-  if (TID->Flags & M_PREDICABLE) {
-    for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
-      if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
-        MachineOperand &MO = MI->getOperand(i);
-        if (MO.isRegister()) {
-          MO.setReg(Pred[j].getReg());
-          MadeChange = true;
-        } else if (MO.isImmediate()) {
-          MO.setImm(Pred[j].getImm());
-          MadeChange = true;
-        } else if (MO.isMachineBasicBlock()) {
-          MO.setMachineBasicBlock(Pred[j].getMachineBasicBlock());
-          MadeChange = true;
-        }
-        ++j;
-      }
-    }
-  }
-  return MadeChange;
-}
-
 bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
-  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
-  if (TID->Flags & M_TERMINATOR_FLAG) {
-    // Conditional branch is a special case.
-    if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0)
-      return true;
-    if ((TID->Flags & M_PREDICABLE) == 0)
-      return true;
-    return !isPredicated(MI);
-  }
-  return false;
+  const TargetInstrDesc &TID = MI->getDesc();
+  if (!TID.isTerminator()) return false;
+  
+  // Conditional branch is a special case.
+  if (TID.isBranch() && !TID.isBarrier())
+    return true;
+  if (!TID.isPredicable())
+    return true;
+  return !isPredicated(MI);
 }