X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FTargetInstrInfo.cpp;h=c0ae56b0f306d17b290313d93d620c4617ec2efb;hb=1fb623e4edba8f5a417fa3de63671af09c10b9c9;hp=ca26718708e1fa08ddb4e418b767de637ba13d17;hpb=93fa70598c88fe14ebe4b3752daab4ea265233e1;p=oota-llvm.git

diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp
index ca26718708e..c0ae56b0f30 100644
--- a/lib/Target/TargetInstrInfo.cpp
+++ b/lib/Target/TargetInstrInfo.cpp
@@ -1,37 +1,46 @@
-//===-- TargetMachine.cpp - General Target Information ---------------------==//
+//===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
+// 
+//                     The LLVM Compiler Infrastructure
 //
-// This file describes the general parts of a Target machine.
-// This file also implements MachineInstrInfo and MachineCacheInfo.
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
+//
+// This file implements the TargetInstrInfo class.
 //
 //===----------------------------------------------------------------------===//
 
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/Constant.h"
 #include "llvm/DerivedTypes.h"
+using namespace llvm;
 
-//---------------------------------------------------------------------------
-// class MachineInstructionInfo
-//	Interface to description of machine instructions
-//---------------------------------------------------------------------------
-
+namespace llvm {
+  // External object describing the machine instructions Initialized only when
+  // the TargetMachine class is created and reset when that class is destroyed.
+  // 
+  // FIXME: UGLY SPARCV9 HACK!
+  const TargetInstrDescriptor* TargetInstrDescriptors = 0;
+}
 
-MachineInstrInfo::MachineInstrInfo(const TargetMachine& tgt,
-                                   const MachineInstrDescriptor* Desc,
-				   unsigned DescSize,
-				   unsigned NumRealOpCodes)
-  : target(tgt), desc(Desc), descSize(DescSize), numRealOpCodes(NumRealOpCodes) {
+TargetInstrInfo::TargetInstrInfo(const TargetInstrDescriptor* Desc,
+				 unsigned numOpcodes)
+  : desc(Desc), NumOpcodes(numOpcodes) {
   // FIXME: TargetInstrDescriptors should not be global
-  assert(TargetInstrDescriptors == NULL && desc != NULL);
+  assert(TargetInstrDescriptors == NULL && desc != NULL
+         && "TargetMachine data structure corrupt; maybe you tried to create another TargetMachine? (only one may exist in a program)");
   TargetInstrDescriptors = desc;	// initialize global variable
 }
 
-MachineInstrInfo::~MachineInstrInfo() {
+TargetInstrInfo::~TargetInstrInfo() {
   TargetInstrDescriptors = NULL;	// reset global variable
 }
 
-
-bool MachineInstrInfo::constantFitsInImmedField(MachineOpCode opCode,
-                                                int64_t intValue) const {
+// FIXME: SPARCV9 SPECIFIC!
+bool TargetInstrInfo::constantFitsInImmedField(MachineOpCode opCode,
+					       int64_t intValue) const {
   // First, check if opCode has an immed field.
   bool isSignExtended;
   uint64_t maxImmedValue = maxImmedConstant(opCode, isSignExtended);
@@ -50,7 +59,14 @@ bool MachineInstrInfo::constantFitsInImmedField(MachineOpCode opCode,
   return false;
 }
 
-bool MachineInstrInfo::ConstantTypeMustBeLoaded(const Constant* CV) const {
-  assert(CV->getType()->isPrimitiveType() || isa<PointerType>(CV->getType()));
-  return !(CV->getType()->isIntegral() || isa<PointerType>(CV->getType()));
+// commuteInstruction - The default implementation of this method just exchanges
+// operand 1 and 2.
+MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const {
+  assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
+         "This only knows how to commute register operands so far");
+  unsigned Reg1 = MI->getOperand(1).getReg();
+  unsigned Reg2 = MI->getOperand(1).getReg();
+  MI->SetMachineOperandReg(2, Reg1);
+  MI->SetMachineOperandReg(1, Reg2);
+  return MI;
 }