X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FTargetInstrInfo.cpp;h=f1d1d07c38aef048793903f90f9516679825148c;hb=b8720787015dc73d8a050b063366be6c3ad01946;hp=56b4e4194e5e0c24cea0ad5db19003edf611d878;hpb=6430bf0449e0ff5e8d344d3107f4ef2306de80ad;p=oota-llvm.git diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp index 56b4e4194e5..f1d1d07c38a 100644 --- a/lib/Target/TargetInstrInfo.cpp +++ b/lib/Target/TargetInstrInfo.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -12,52 +12,77 @@ //===----------------------------------------------------------------------===// #include "llvm/Target/TargetInstrInfo.h" -#include "llvm/CodeGen/MachineInstr.h" -#include "llvm/Constant.h" -#include "llvm/DerivedTypes.h" +#include "llvm/Target/TargetRegisterInfo.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCInstrItineraries.h" +#include "llvm/Support/ErrorHandling.h" +#include using namespace llvm; -TargetInstrInfo::TargetInstrInfo(const TargetInstrDescriptor* Desc, - unsigned numOpcodes) - : desc(Desc), NumOpcodes(numOpcodes) { -} +//===----------------------------------------------------------------------===// +// TargetInstrInfo +// +// Methods that depend on CodeGen are implemented in +// TargetInstrInfoImpl.cpp. Invoking them without linking libCodeGen raises a +// link error. +// ===----------------------------------------------------------------------===// TargetInstrInfo::~TargetInstrInfo() { } -/// findTiedToSrcOperand - Returns the operand that is tied to the specified -/// dest operand. Returns -1 if there isn't one. -int -TargetInstrInfo::findTiedToSrcOperand(MachineOpCode Opc, unsigned OpNum) const { - for (unsigned i = 0, e = getNumOperands(Opc); i != e; ++i) { - if (i == OpNum) - continue; - int ti = getOperandConstraint(Opc, i, TIED_TO); - if (ti == (int)OpNum) - return i; - } - return -1; +const TargetRegisterClass* +TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, + const TargetRegisterInfo *TRI, + const MachineFunction &MF) const { + if (OpNum >= MCID.getNumOperands()) + return 0; + + short RegClass = MCID.OpInfo[OpNum].RegClass; + if (MCID.OpInfo[OpNum].isLookupPtrRegClass()) + return TRI->getPointerRegClass(MF, RegClass); + + // Instructions like INSERT_SUBREG do not have fixed register classes. + if (RegClass < 0) + return 0; + + // Otherwise just look it up normally. + return TRI->getRegClass(RegClass); +} + +/// insertNoop - Insert a noop into the instruction stream at the specified +/// point. +void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI) const { + llvm_unreachable("Target didn't implement insertNoop!"); } +/// Measure the specified inline asm to determine an approximation of its +/// length. +/// Comments (which run till the next SeparatorString or newline) do not +/// count as an instruction. +/// Any other non-whitespace text is considered an instruction, with +/// multiple instructions separated by SeparatorString or newlines. +/// Variable-length instructions are not handled here; this function +/// may be overloaded in the target code to do that. +unsigned TargetInstrInfo::getInlineAsmLength(const char *Str, + const MCAsmInfo &MAI) const { + + + // Count the number of instructions in the asm. + bool atInsnStart = true; + unsigned Length = 0; + for (; *Str; ++Str) { + if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(), + strlen(MAI.getSeparatorString())) == 0) + atInsnStart = true; + if (atInsnStart && !std::isspace(*Str)) { + Length += MAI.getMaxInstLength(); + atInsnStart = false; + } + if (atInsnStart && strncmp(Str, MAI.getCommentString(), + strlen(MAI.getCommentString())) == 0) + atInsnStart = false; + } -// commuteInstruction - The default implementation of this method just exchanges -// operand 1 and 2. -MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const { - assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() && - "This only knows how to commute register operands so far"); - unsigned Reg1 = MI->getOperand(1).getReg(); - unsigned Reg2 = MI->getOperand(2).getReg(); - bool Reg1IsKill = MI->getOperand(1).isKill(); - bool Reg2IsKill = MI->getOperand(2).isKill(); - MI->getOperand(2).setReg(Reg1); - MI->getOperand(1).setReg(Reg2); - if (Reg1IsKill) - MI->getOperand(2).setIsKill(); - else - MI->getOperand(2).unsetIsKill(); - if (Reg2IsKill) - MI->getOperand(1).setIsKill(); - else - MI->getOperand(1).unsetIsKill(); - return MI; + return Length; }