X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FTargetRegisterInfo.cpp;h=67239b830eb55cb0c103888a493b4e01c6638e7e;hb=8f3af87e99b9556224480f1aa18d340fb343bbf6;hp=1c3f2dda33c74480fd453fa3c2a5414146839cb8;hpb=f462e3fac7ac67503657d63dc35330d0b19359b3;p=oota-llvm.git diff --git a/lib/Target/TargetRegisterInfo.cpp b/lib/Target/TargetRegisterInfo.cpp index 1c3f2dda33c..67239b830eb 100644 --- a/lib/Target/TargetRegisterInfo.cpp +++ b/lib/Target/TargetRegisterInfo.cpp @@ -20,21 +20,11 @@ using namespace llvm; -TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, +TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, - const char *const *subregindexnames, - int CFSO, int CFDO, - const unsigned* subregs, const unsigned subregsize, - const unsigned* aliases, const unsigned aliasessize) - : SubregHash(subregs), SubregHashSize(subregsize), - AliasesHash(aliases), AliasesHashSize(aliasessize), - Desc(D), SubRegIndexNames(subregindexnames), NumRegs(NR), + const char *const *subregindexnames) + : InfoDesc(ID), SubRegIndexNames(subregindexnames), RegClassBegin(RCB), RegClassEnd(RCE) { - assert(isPhysicalRegister(NumRegs) && - "Target has too many physical registers!"); - - CallFrameSetupOpcode = CFSO; - CallFrameDestroyOpcode = CFDO; } TargetRegisterInfo::~TargetRegisterInfo() {} @@ -83,14 +73,14 @@ TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const { /// registers for the specific register class. static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R){ - for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), - E = RC->allocation_order_end(MF); I != E; ++I) - R.set(*I); + ArrayRef Order = RC->getRawAllocationOrder(MF); + for (unsigned i = 0; i != Order.size(); ++i) + R.set(Order[i]); } BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC) const { - BitVector Allocatable(NumRegs); + BitVector Allocatable(getNumRegs()); if (RC) { getAllocatableSetForRC(MF, RC, Allocatable); } else { @@ -108,44 +98,25 @@ BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, } const TargetRegisterClass * -llvm::getCommonSubClass(const TargetRegisterClass *A, - const TargetRegisterClass *B) { - // First take care of the trivial cases +TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A, + const TargetRegisterClass *B) const { + // First take care of the trivial cases. if (A == B) return A; if (!A || !B) return 0; - // If B is a subclass of A, it will be handled in the loop below - if (B->hasSubClass(A)) - return A; + // Register classes are ordered topologically, so the largest common + // sub-class it the common sub-class with the smallest ID. + const unsigned *SubA = A->getSubClassMask(); + const unsigned *SubB = B->getSubClassMask(); - const TargetRegisterClass *Best = 0; - for (TargetRegisterClass::sc_iterator I = A->subclasses_begin(); - const TargetRegisterClass *X = *I; ++I) { - if (X == B) - return B; // B is a subclass of A - - // X must be a common subclass of A and B - if (!B->hasSubClass(X)) - continue; - - // A superclass is definitely better. - if (!Best || Best->hasSuperClass(X)) { - Best = X; - continue; - } - - // A subclass is definitely worse - if (Best->hasSubClass(X)) - continue; - - // Best and *I have no super/sub class relation - pick the larger class, or - // the smaller spill size. - int nb = std::distance(Best->begin(), Best->end()); - int ni = std::distance(X->begin(), X->end()); - if (ni>nb || (ni==nb && X->getSize() < Best->getSize())) - Best = X; - } - return Best; + // We could start the search from max(A.ID, B.ID), but we are only going to + // execute 2-3 iterations anyway. + for (unsigned Base = 0, BaseE = getNumRegClasses(); Base < BaseE; Base += 32) + if (unsigned Common = *SubA++ & *SubB++) + return getRegClass(Base + CountTrailingZeros_32(Common)); + + // No common sub-class exists. + return NULL; }