X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FTargetRegisterInfo.cpp;h=90a8f8d8fdcce8c9a968e30b97c5cfe6da5e63ee;hb=6b5b79c7e8aec3138727e102e85aaf1c3a01765e;hp=e69496f4b287ba372c2f4871a9c1d999d07027c6;hpb=1360b7d8f8d1969026870d18c582b4e3a7cff8b8;p=oota-llvm.git diff --git a/lib/Target/TargetRegisterInfo.cpp b/lib/Target/TargetRegisterInfo.cpp index e69496f4b28..90a8f8d8fdc 100644 --- a/lib/Target/TargetRegisterInfo.cpp +++ b/lib/Target/TargetRegisterInfo.cpp @@ -13,111 +13,129 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegisterInfo.h" -#include "llvm/Target/TargetFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/ADT/BitVector.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; -TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, +TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, - int CFSO, int CFDO) - : Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) { - assert(NumRegs < FirstVirtualRegister && - "Target has too many physical registers!"); - - CallFrameSetupOpcode = CFSO; - CallFrameDestroyOpcode = CFDO; - - for (unsigned i = 0; i < NumRegs; ++i) { - const TargetRegisterDesc* CurrReg = Desc + i; - - // Initialize the Subregs set, which stores pairs (a, b) where - // b is a subreg of a. - if (CurrReg->SubRegs) - for (const unsigned* CurrSR = CurrReg->SubRegs; *CurrSR; ++CurrSR) - Subregs.insert(std::make_pair(i, *CurrSR)); - } + const char *const *subregindexnames) + : InfoDesc(ID), SubRegIndexNames(subregindexnames), + RegClassBegin(RCB), RegClassEnd(RCE) { } TargetRegisterInfo::~TargetRegisterInfo() {} -namespace { - // Sort according to super- / sub- class relations. - // i.e. super- register class < sub- register class. - struct RCCompare { - bool operator()(const TargetRegisterClass* const &LHS, - const TargetRegisterClass* const &RHS) { - return RHS->hasSuperClass(LHS); - } - }; +void PrintReg::print(raw_ostream &OS) const { + if (!Reg) + OS << "%noreg"; + else if (TargetRegisterInfo::isStackSlot(Reg)) + OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg); + else if (TargetRegisterInfo::isVirtualRegister(Reg)) + OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg); + else if (TRI && Reg < TRI->getNumRegs()) + OS << '%' << TRI->getName(Reg); + else + OS << "%physreg" << Reg; + if (SubIdx) { + if (TRI) + OS << ':' << TRI->getSubRegIndexName(SubIdx); + else + OS << ":sub(" << SubIdx << ')'; + } } -/// getPhysicalRegisterRegClass - Returns the Register Class of a physical -/// register of the given type. If type is MVT::Other, then just return any -/// register class the register belongs to. +/// getMinimalPhysRegClass - Returns the Register Class of a physical +/// register of the given type, picking the most sub register class of +/// the right type that contains this physreg. const TargetRegisterClass * -TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, MVT VT) const { +TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const { assert(isPhysicalRegister(reg) && "reg must be a physical register"); - // Pick the register class of the right type that contains this physreg. - SmallVector RCs; + // Pick the most sub register class of the right type that contains + // this physreg. + const TargetRegisterClass* BestRC = 0; for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){ - if ((VT == MVT::Other || (*I)->hasType(VT)) && (*I)->contains(reg)) - RCs.push_back(*I); - } - - if (RCs.size() == 1) - return RCs[0]; - - if (RCs.size()) { - // Multiple compatible register classes. Get the super- class. - std::stable_sort(RCs.begin(), RCs.end(), RCCompare()); - return RCs[0]; + const TargetRegisterClass* RC = *I; + if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) && + (!BestRC || BestRC->hasSubClass(RC))) + BestRC = RC; } - assert(false && "Couldn't find the register class"); - return 0; + assert(BestRC && "Couldn't find the register class"); + return BestRC; } /// getAllocatableSetForRC - Toggle the bits that represent allocatable /// registers for the specific register class. -static void getAllocatableSetForRC(MachineFunction &MF, - const TargetRegisterClass *RC, BitVector &R){ - for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), - E = RC->allocation_order_end(MF); I != E; ++I) - R.set(*I); +static void getAllocatableSetForRC(const MachineFunction &MF, + const TargetRegisterClass *RC, BitVector &R){ + ArrayRef Order = RC->getRawAllocationOrder(MF); + for (unsigned i = 0; i != Order.size(); ++i) + R.set(Order[i]); } -BitVector TargetRegisterInfo::getAllocatableSet(MachineFunction &MF, +BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC) const { - BitVector Allocatable(NumRegs); + BitVector Allocatable(getNumRegs()); if (RC) { getAllocatableSetForRC(MF, RC, Allocatable); - return Allocatable; + } else { + for (TargetRegisterInfo::regclass_iterator I = regclass_begin(), + E = regclass_end(); I != E; ++I) + if ((*I)->isAllocatable()) + getAllocatableSetForRC(MF, *I, Allocatable); } - for (TargetRegisterInfo::regclass_iterator I = regclass_begin(), - E = regclass_end(); I != E; ++I) - getAllocatableSetForRC(MF, *I, Allocatable); + // Mask out the reserved registers + BitVector Reserved = getReservedRegs(MF); + Allocatable &= Reserved.flip(); + return Allocatable; } -/// getFrameIndexOffset - Returns the displacement from the frame register to -/// the stack frame of the specified index. This is the default implementation -/// which is likely incorrect for the target. -int TargetRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const { - const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - return MFI->getObjectOffset(FI) + MFI->getStackSize() - - TFI.getOffsetOfLocalArea() + MFI->getOffsetAdjustment(); -} +const TargetRegisterClass * +llvm::getCommonSubClass(const TargetRegisterClass *A, + const TargetRegisterClass *B) { + // First take care of the trivial cases + if (A == B) + return A; + if (!A || !B) + return 0; + + // If B is a subclass of A, it will be handled in the loop below + if (B->hasSubClass(A)) + return A; + + const TargetRegisterClass *Best = 0; + for (TargetRegisterClass::sc_iterator I = A->subclasses_begin(); + const TargetRegisterClass *X = *I; ++I) { + if (X == B) + return B; // B is a subclass of A + + // X must be a common subclass of A and B + if (!B->hasSubClass(X)) + continue; + + // A superclass is definitely better. + if (!Best || Best->hasSuperClass(X)) { + Best = X; + continue; + } -/// getInitialFrameState - Returns a list of machine moves that are assumed -/// on entry to a function. -void -TargetRegisterInfo::getInitialFrameState(std::vector &Moves) const { - // Default is to do nothing. -} + // A subclass is definitely worse + if (Best->hasSubClass(X)) + continue; + // Best and *I have no super/sub class relation - pick the larger class, or + // the smaller spill size. + int nb = std::distance(Best->begin(), Best->end()); + int ni = std::distance(X->begin(), X->end()); + if (ni>nb || (ni==nb && X->getSize() < Best->getSize())) + Best = X; + } + return Best; +}