X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FTargetSchedInfo.cpp;h=a7ec1b545a374ab1777b63eb014af0c4b17e86a9;hb=6d92caddc4aa5fc946b294259e00cc35536e61e8;hp=f9dca290b06460f903f0932f21e7cff6cd796a48;hpb=7a2f1e7c5d29682a772af75e78621e6c431e3e4c;p=oota-llvm.git diff --git a/lib/Target/TargetSchedInfo.cpp b/lib/Target/TargetSchedInfo.cpp index f9dca290b06..a7ec1b545a3 100644 --- a/lib/Target/TargetSchedInfo.cpp +++ b/lib/Target/TargetSchedInfo.cpp @@ -1,19 +1,40 @@ //===-- SchedInfo.cpp - Generic code to support target schedulers ----------==// // +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// // This file implements the generic part of a Scheduler description for a // target. This functionality is defined in the llvm/Target/SchedInfo.h file. // //===----------------------------------------------------------------------===// -#include "llvm/Target/MachineSchedInfo.h" +#include "llvm/Config/alloca.h" +#include "llvm/Target/TargetSchedInfo.h" +#include "llvm/Target/TargetMachine.h" +#include +#include +using namespace llvm; + +resourceId_t llvm::CPUResource::nextId = 0; +static std::vector *CPUResourceMap = 0; + +CPUResource::CPUResource(const std::string& resourceName, int maxUsers) + : rname(resourceName), rid(nextId++), maxNumUsers(maxUsers) { + if(!CPUResourceMap) + CPUResourceMap = new std::vector; -// External object describing the machine instructions -// Initialized only when the TargetMachine class is created -// and reset when that class is destroyed. -// -const MachineInstrDescriptor* TargetInstrDescriptors = 0; + //Put Resource in the map + CPUResourceMap->push_back(this); +} -resourceId_t MachineResource::nextId = 0; +///Get CPUResource if you only have the resource ID +CPUResource* CPUResource::getCPUResource(resourceId_t id) { + return (*CPUResourceMap)[id]; +} // Check if fromRVec and toRVec have *any* common entries. // Assume the vectors are sorted in increasing order. @@ -21,121 +42,116 @@ resourceId_t MachineResource::nextId = 0; // (stl_algo.h). // inline static bool -RUConflict(const vector& fromRVec, - const vector& toRVec) +RUConflict(const std::vector& fromRVec, + const std::vector& toRVec) { - - unsigned fN = fromRVec.size(), tN = toRVec.size(); + + unsigned fN = fromRVec.size(), tN = toRVec.size(); unsigned fi = 0, ti = 0; - while (fi < fN && ti < tN) - { - if (fromRVec[fi] < toRVec[ti]) - ++fi; - else if (toRVec[ti] < fromRVec[fi]) - ++ti; - else - return true; - } + while (fi < fN && ti < tN) { + if (fromRVec[fi] < toRVec[ti]) + ++fi; + else if (toRVec[ti] < fromRVec[fi]) + ++ti; + else + return true; + } return false; } -static cycles_t -ComputeMinGap(const InstrRUsage &fromRU, - const InstrRUsage &toRU) +static CycleCount_t +ComputeMinGap(const InstrRUsage &fromRU, + const InstrRUsage &toRU) { - cycles_t minGap = 0; - + CycleCount_t minGap = 0; + if (fromRU.numBubbles > 0) minGap = fromRU.numBubbles; - - if (minGap < fromRU.numCycles) - { - // only need to check from cycle `minGap' onwards - for (cycles_t gap=minGap; gap <= fromRU.numCycles-1; gap++) - { - // check if instr. #2 can start executing `gap' cycles after #1 - // by checking for resource conflicts in each overlapping cycle - cycles_t numOverlap = min(fromRU.numCycles - gap, toRU.numCycles); - for (cycles_t c = 0; c <= numOverlap-1; c++) - if (RUConflict(fromRU.resourcesByCycle[gap + c], - toRU.resourcesByCycle[c])) - { - // conflict found so minGap must be more than `gap' - minGap = gap+1; - break; - } - } + + if (minGap < fromRU.numCycles) { + // only need to check from cycle `minGap' onwards + for (CycleCount_t gap=minGap; gap <= fromRU.numCycles-1; gap++) { + // check if instr. #2 can start executing `gap' cycles after #1 + // by checking for resource conflicts in each overlapping cycle + CycleCount_t numOverlap =std::min(fromRU.numCycles - gap, toRU.numCycles); + for (CycleCount_t c = 0; c <= numOverlap-1; c++) + if (RUConflict(fromRU.resourcesByCycle[gap + c], + toRU.resourcesByCycle[c])) { + // conflict found so minGap must be more than `gap' + minGap = gap+1; + break; + } } - + } + return minGap; } //--------------------------------------------------------------------------- -// class MachineSchedInfo -// Interface to machine description for instruction scheduling +// class TargetSchedInfo +// Interface to machine description for instruction scheduling //--------------------------------------------------------------------------- -MachineSchedInfo::MachineSchedInfo(const TargetMachine& tgt, - int NumSchedClasses, - const InstrClassRUsage* ClassRUsages, - const InstrRUsageDelta* UsageDeltas, - const InstrIssueDelta* IssueDeltas, - unsigned int NumUsageDeltas, - unsigned int NumIssueDeltas) +TargetSchedInfo::TargetSchedInfo(const TargetMachine& tgt, + int NumSchedClasses, + const InstrClassRUsage* ClassRUsages, + const InstrRUsageDelta* UsageDeltas, + const InstrIssueDelta* IssueDeltas, + unsigned NumUsageDeltas, + unsigned NumIssueDeltas) : target(tgt), - numSchedClasses(NumSchedClasses), mii(& tgt.getInstrInfo()), + numSchedClasses(NumSchedClasses), mii(tgt.getInstrInfo()), classRUsages(ClassRUsages), usageDeltas(UsageDeltas), issueDeltas(IssueDeltas), numUsageDeltas(NumUsageDeltas), numIssueDeltas(NumIssueDeltas) {} void -MachineSchedInfo::initializeResources() +TargetSchedInfo::initializeResources() { - assert(MAX_NUM_SLOTS >= (int)getMaxNumIssueTotal() - && "Insufficient slots for static data! Increase MAX_NUM_SLOTS"); - + assert(MAX_NUM_SLOTS >= (int)getMaxNumIssueTotal() && + "Insufficient slots for static data! Increase MAX_NUM_SLOTS"); + // First, compute common resource usage info for each class because // most instructions will probably behave the same as their class. // Cannot allocate a vector of InstrRUsage so new each one. - // - vector instrRUForClasses; + // + std::vector instrRUForClasses; instrRUForClasses.resize(numSchedClasses); for (InstrSchedClass sc = 0; sc < numSchedClasses; sc++) { // instrRUForClasses.push_back(new InstrRUsage); instrRUForClasses[sc].setMaxSlots(getMaxNumIssueTotal()); - instrRUForClasses[sc] = classRUsages[sc]; + instrRUForClasses[sc].setTo(classRUsages[sc]); } - + computeInstrResources(instrRUForClasses); computeIssueGaps(instrRUForClasses); } void -MachineSchedInfo::computeInstrResources(const vector& - instrRUForClasses) -{ - int numOpCodes = mii->getNumRealOpCodes(); +TargetSchedInfo::computeInstrResources(const std::vector& + instrRUForClasses) { + int numOpCodes = mii->getNumOpcodes(); instrRUsages.resize(numOpCodes); - + // First get the resource usage information from the class resource usages. for (MachineOpCode op = 0; op < numOpCodes; ++op) { InstrSchedClass sc = getSchedClass(op); - assert(sc >= 0 && sc < numSchedClasses); + assert(sc < numSchedClasses); instrRUsages[op] = instrRUForClasses[sc]; } - + // Now, modify the resource usages as specified in the deltas. for (unsigned i = 0; i < numUsageDeltas; ++i) { MachineOpCode op = usageDeltas[i].opCode; assert(op < numOpCodes); instrRUsages[op].addUsageDelta(usageDeltas[i]); } - + // Then modify the issue restrictions as specified in the deltas. for (unsigned i = 0; i < numIssueDeltas; ++i) { MachineOpCode op = issueDeltas[i].opCode; @@ -146,48 +162,105 @@ MachineSchedInfo::computeInstrResources(const vector& void -MachineSchedInfo::computeIssueGaps(const vector& - instrRUForClasses) -{ - int numOpCodes = mii->getNumRealOpCodes(); - instrRUsages.resize(numOpCodes); - - assert(numOpCodes < (1 << MAX_OPCODE_SIZE) - 1 - && "numOpCodes invalid for implementation of class OpCodePair!"); - +TargetSchedInfo::computeIssueGaps(const std::vector& + instrRUForClasses) { + int numOpCodes = mii->getNumOpcodes(); + issueGaps.resize(numOpCodes); + conflictLists.resize(numOpCodes); + // First, compute issue gaps between pairs of classes based on common // resources usages for each class, because most instruction pairs will // usually behave the same as their class. - // - int classPairGaps[numSchedClasses][numSchedClasses]; + // + int* classPairGaps = + static_cast(alloca(sizeof(int) * numSchedClasses * numSchedClasses)); for (InstrSchedClass fromSC=0; fromSC < numSchedClasses; fromSC++) - for (InstrSchedClass toSC=0; toSC < numSchedClasses; toSC++) - { - int classPairGap = ComputeMinGap(instrRUForClasses[fromSC], - instrRUForClasses[toSC]); - classPairGaps[fromSC][toSC] = classPairGap; - } - + for (InstrSchedClass toSC=0; toSC < numSchedClasses; toSC++) { + int classPairGap = ComputeMinGap(instrRUForClasses[fromSC], + instrRUForClasses[toSC]); + classPairGaps[fromSC*numSchedClasses + toSC] = classPairGap; + } + // Now, for each pair of instructions, use the class pair gap if both // instructions have identical resource usage as their respective classes. // If not, recompute the gap for the pair from scratch. - + longestIssueConflict = 0; - + for (MachineOpCode fromOp=0; fromOp < numOpCodes; fromOp++) - for (MachineOpCode toOp=0; toOp < numOpCodes; toOp++) - { - int instrPairGap = - (instrRUsages[fromOp].sameAsClass && instrRUsages[toOp].sameAsClass) - ? classPairGaps[getSchedClass(fromOp)][getSchedClass(toOp)] - : ComputeMinGap(instrRUsages[fromOp], instrRUsages[toOp]); - - if (instrPairGap > 0) - { - issueGaps[OpCodePair(fromOp,toOp)] = instrPairGap; - conflictLists[fromOp].push_back(toOp); - longestIssueConflict = max(longestIssueConflict, instrPairGap); - } + for (MachineOpCode toOp=0; toOp < numOpCodes; toOp++) { + int instrPairGap = + (instrRUsages[fromOp].sameAsClass && instrRUsages[toOp].sameAsClass) + ? classPairGaps[getSchedClass(fromOp)*numSchedClasses + getSchedClass(toOp)] + : ComputeMinGap(instrRUsages[fromOp], instrRUsages[toOp]); + + if (instrPairGap > 0) { + this->setGap(instrPairGap, fromOp, toOp); + conflictLists[fromOp].push_back(toOp); + longestIssueConflict=std::max(longestIssueConflict, instrPairGap); } + } +} + + +void InstrRUsage::setTo(const InstrClassRUsage& classRU) { + sameAsClass = true; + isSingleIssue = classRU.isSingleIssue; + breaksGroup = classRU.breaksGroup; + numBubbles = classRU.numBubbles; + + for (unsigned i=0; i < classRU.numSlots; i++) { + unsigned slot = classRU.feasibleSlots[i]; + assert(slot < feasibleSlots.size() && "Invalid slot specified!"); + this->feasibleSlots[slot] = true; + } + + numCycles = classRU.totCycles; + resourcesByCycle.resize(this->numCycles); + + for (unsigned i=0; i < classRU.numRUEntries; i++) + for (unsigned c=classRU.V[i].startCycle, NC = c + classRU.V[i].numCycles; + c < NC; c++) + this->resourcesByCycle[c].push_back(classRU.V[i].resourceId); + + // Sort each resource usage vector by resourceId_t to speed up conflict + // checking + for (unsigned i=0; i < this->resourcesByCycle.size(); i++) + std::sort(resourcesByCycle[i].begin(), resourcesByCycle[i].end()); } +// Add the extra resource usage requirements specified in the delta. +// Note that a negative value of `numCycles' means one entry for that +// resource should be deleted for each cycle. +// +void InstrRUsage::addUsageDelta(const InstrRUsageDelta &delta) { + int NC = delta.numCycles; + sameAsClass = false; + + // resize the resources vector if more cycles are specified + unsigned maxCycles = this->numCycles; + maxCycles = std::max(maxCycles, delta.startCycle + abs(NC) - 1); + if (maxCycles > this->numCycles) { + this->resourcesByCycle.resize(maxCycles); + this->numCycles = maxCycles; + } + + if (NC >= 0) + for (unsigned c=delta.startCycle, last=c+NC-1; c <= last; c++) + this->resourcesByCycle[c].push_back(delta.resourceId); + else + // Remove the resource from all NC cycles. + for (unsigned c=delta.startCycle, last=(c-NC)-1; c <= last; c++) { + // Look for the resource backwards so we remove the last entry + // for that resource in each cycle. + std::vector& rvec = this->resourcesByCycle[c]; + int r; + for (r = rvec.size() - 1; r >= 0; r--) + if (rvec[r] == delta.resourceId) { + // found last entry for the resource + rvec.erase(rvec.begin() + r); + break; + } + assert(r >= 0 && "Resource to remove was unused in cycle c!"); + } +}