X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FInstSelectSimple.cpp;h=217b219ba2a4ae47e6d7f5420d61147a06a5a9af;hb=d474e9cdce5aa061e9a340040246592737667cb5;hp=20fc69a91e10e2bbbf45b6380303334654f7b4b0;hpb=c11232a8c4477fc683a9947c6098e4845556fdd4;p=oota-llvm.git diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp index 20fc69a91e1..217b219ba2a 100644 --- a/lib/Target/X86/InstSelectSimple.cpp +++ b/lib/Target/X86/InstSelectSimple.cpp @@ -107,6 +107,7 @@ namespace { abort(); } + void promote32 (const unsigned targetReg, Value *v); /// copyConstantToRegister - Output the instructions required to put the /// specified constant into the specified register. @@ -132,8 +133,14 @@ namespace { // If this operand is a constant, emit the code to copy the constant into // the register here... // - if (Constant *C = dyn_cast(V)) + if (Constant *C = dyn_cast(V)) { copyConstantToRegister(C, Reg); + } else if (GlobalValue *GV = dyn_cast(V)) { + // Move the address of the global into the register + BuildMI(BB, X86::MOVir32, 1, Reg).addReg(GV); + } else if (Argument *A = dyn_cast(V)) { + std::cerr << "ERROR: Arguments not implemented in SimpleInstSel\n"; + } return Reg; } @@ -272,6 +279,38 @@ void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) { BuildMI (BB, X86::MOVrr8, 1, getReg(I)).addReg(X86::AL); } +/// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide +/// operand, in the specified target register. +void +ISel::promote32 (const unsigned targetReg, Value *v) +{ + unsigned vReg = getReg (v); + unsigned Class = getClass (v->getType ()); + bool isUnsigned = v->getType ()->isUnsigned (); + assert (((Class == cByte) || (Class == cShort) || (Class == cInt)) + && "Unpromotable operand class in promote32"); + switch (Class) + { + case cByte: + // Extend value into target register (8->32) + if (isUnsigned) + BuildMI (BB, X86::MOVZXr32r8, 1, targetReg).addReg (vReg); + else + BuildMI (BB, X86::MOVSXr32r8, 1, targetReg).addReg (vReg); + break; + case cShort: + // Extend value into target register (16->32) + if (isUnsigned) + BuildMI (BB, X86::MOVZXr32r16, 1, targetReg).addReg (vReg); + else + BuildMI (BB, X86::MOVSXr32r16, 1, targetReg).addReg (vReg); + break; + case cInt: + // Move value into target register (32->32) + BuildMI (BB, X86::MOVrr32, 1, targetReg).addReg (vReg); + break; + } +} /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such, /// we have the following possibilities: @@ -284,56 +323,43 @@ void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) { /// ret long, ulong : Move value into EAX/EDX and return /// ret float/double : Top of FP stack /// -void ISel::visitReturnInst (ReturnInst &I) { - if (I.getNumOperands() == 0) { - // Emit a 'ret' instruction - BuildMI(BB, X86::RET, 0); - return; - } - - unsigned val = getReg(I.getOperand(0)); - unsigned Class = getClass(I.getOperand(0)->getType()); - bool isUnsigned = I.getOperand(0)->getType()->isUnsigned(); - switch (Class) { - case cByte: - // ret sbyte, ubyte: Extend value into EAX and return - if (isUnsigned) - BuildMI (BB, X86::MOVZXr32r8, 1, X86::EAX).addReg (val); - else - BuildMI (BB, X86::MOVSXr32r8, 1, X86::EAX).addReg (val); - break; - case cShort: - // ret short, ushort: Extend value into EAX and return - if (isUnsigned) - BuildMI (BB, X86::MOVZXr32r16, 1, X86::EAX).addReg (val); - else - BuildMI (BB, X86::MOVSXr32r16, 1, X86::EAX).addReg (val); - break; - case cInt: - // ret int, uint, ptr: Move value into EAX and return - // MOV EAX, - BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(val); - break; - - // ret float/double: top of FP stack - // FLD - case cFloat: // Floats - BuildMI(BB, X86::FLDr4, 1).addReg(val); - break; - case cDouble: // Doubles - BuildMI(BB, X86::FLDr8, 1).addReg(val); - break; - case cLong: - // ret long: use EAX(least significant 32 bits)/EDX (most - // significant 32)...uh, I think so Brain, but how do i call - // up the two parts of the value from inside this mouse - // cage? *zort* - default: - visitInstruction(I); - } - +void +ISel::visitReturnInst (ReturnInst &I) +{ + if (I.getNumOperands () == 0) + { + // Emit a 'ret' instruction + BuildMI (BB, X86::RET, 0); + return; + } + Value *rv = I.getOperand (0); + unsigned Class = getClass (rv->getType ()); + switch (Class) + { + // integral return values: extend or move into EAX and return. + case cByte: + case cShort: + case cInt: + promote32 (X86::EAX, rv); + break; + // ret float/double: top of FP stack + // FLD + case cFloat: // Floats + BuildMI (BB, X86::FLDr4, 1).addReg (getReg (rv)); + break; + case cDouble: // Doubles + BuildMI (BB, X86::FLDr8, 1).addReg (getReg (rv)); + break; + case cLong: + // ret long: use EAX(least significant 32 bits)/EDX (most + // significant 32)...uh, I think so Brain, but how do i call + // up the two parts of the value from inside this mouse + // cage? *zort* + default: + visitInstruction (I); + } // Emit a 'ret' instruction - BuildMI(BB, X86::RET, 0); + BuildMI (BB, X86::RET, 0); } /// visitBranchInst - Handle conditional and unconditional branches here. Note @@ -363,10 +389,63 @@ ISel::visitBranchInst (BranchInst & BI) } } -/// visitCallInst - Have to push args and do a procedure call -/// instruction, if the target address is known. -void ISel::visitCallInst (CallInst &CI) { - visitInstruction (CI); +/// visitCallInst - Push args on stack and do a procedure call instruction. +void +ISel::visitCallInst (CallInst & CI) +{ + // keep a counter of how many bytes we pushed on the stack + unsigned bytesPushed = 0; + + // Push the arguments on the stack in reverse order, as specified by + // the ABI. + for (unsigned i = CI.getNumOperands()-1; i >= 1; --i) + { + Value *v = CI.getOperand (i); + switch (getClass (v->getType ())) + { + case cByte: + case cShort: + // Promote V to 32 bits wide, and move the result into EAX, + // then push EAX. + promote32 (X86::EAX, v); + BuildMI (BB, X86::PUSHr32, 1).addReg (X86::EAX); + bytesPushed += 4; + break; + case cInt: + case cFloat: { + unsigned Reg = getReg(v); + BuildMI (BB, X86::PUSHr32, 1).addReg(Reg); + bytesPushed += 4; + break; + } + default: + // FIXME: long/ulong/double args not handled. + visitInstruction (CI); + break; + } + } + // Emit a CALL instruction with PC-relative displacement. + BuildMI (BB, X86::CALLpcrel32, 1).addPCDisp (CI.getCalledValue ()); + + // Adjust the stack by `bytesPushed' amount if non-zero + if (bytesPushed > 0) + BuildMI (BB, X86::ADDri32, 2).addReg(X86::ESP).addZImm(bytesPushed); + + // If there is a return value, scavenge the result from the location the call + // leaves it in... + // + if (CI.getType() != Type::VoidTy) { + switch (getClass(CI.getType())) { + case cInt: + BuildMI(BB, X86::MOVrr32, 1, getReg(CI)).addReg(X86::EAX); + break; + + default: + std::cerr << "Cannot get return value for call of type '" + << *CI.getType() << "'\n"; + visitInstruction(CI); + } + } } /// visitSimpleBinary - Implement simple binary operators for integral types... @@ -457,7 +536,7 @@ void ISel::visitDivRem(BinaryOperator &I) { if (isSigned) { // Emit a sign extension instruction... - BuildMI(BB, ExtOpcode[Class], 1, ExtReg).addReg(Reg); + BuildMI(BB, ExtOpcode[Class], 0); } else { // If unsigned, emit a zeroing instruction... (reg = xor reg, reg) BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg); @@ -586,34 +665,73 @@ void ISel::visitPHINode(PHINode &PN) { void ISel::visitCastInst (CastInst &CI) { -//> cast larger int to smaller int --> copy least significant byte/word w/ mov? -// -//I'm not really sure what to do with this. We could insert a pseudo-op -//that says take the low X bits of a Y bit register, but for now we can just -//force the value into, say, EAX, then rip out AL or AX. The advantage of -//the former is that the register allocator could use any register it wants, -//but for now this obviously doesn't matter. :) - -// if target type is bool -// Emit Compare -// Emit Set-if-not-zero - -// if size of target type == size of source type -// Emit Mov reg(target) <- reg(source) - -// if size of target type > size of source type -// if both types are integer types -// if source type is signed -// sbyte to short, ushort: Emit movsx 8->16 -// sbyte to int, uint: Emit movsx 8->32 -// short to int, uint: Emit movsx 16->32 -// else if source type is unsigned -// ubyte to short, ushort: Emit movzx 8->16 -// ubyte to int, uint: Emit movzx 8->32 -// ushort to int, uint: Emit movzx 16->32 -// if both types are fp types -// float to double: Emit fstp, fld (???) - + const Type *targetType = CI.getType (); + Value *operand = CI.getOperand (0); + unsigned int operandReg = getReg (operand); + const Type *sourceType = operand->getType (); + unsigned int destReg = getReg (CI); + // + // Currently we handle: + // + // 1) cast * to bool + // + // 2) cast {sbyte, ubyte} to {sbyte, ubyte} + // cast {short, ushort} to {ushort, short} + // cast {int, uint, ptr} to {int, uint, ptr} + // + // 3) cast {sbyte, ubyte} to {ushort, short} + // cast {sbyte, ubyte} to {int, uint, ptr} + // cast {short, ushort} to {int, uint, ptr} + // + // 4) cast {int, uint, ptr} to {short, ushort} + // cast {int, uint, ptr} to {sbyte, ubyte} + // cast {short, ushort} to {sbyte, ubyte} + // + // 1) Implement casts to bool by using compare on the operand followed + // by set if not zero on the result. + if (targetType == Type::BoolTy) + { + BuildMI (BB, X86::CMPri8, 2).addReg (operandReg).addZImm (0); + BuildMI (BB, X86::SETNEr, 1, destReg); + return; + } + // 2) Implement casts between values of the same type class (as determined + // by getClass) by using a register-to-register move. + unsigned int srcClass = getClass (sourceType); + unsigned int targClass = getClass (targetType); + static const unsigned regRegMove[] = { + X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 + }; + if ((srcClass < 3) && (targClass < 3) && (srcClass == targClass)) + { + BuildMI (BB, regRegMove[srcClass], 1, destReg).addReg (operandReg); + return; + } + // 3) Handle cast of SMALLER int to LARGER int using a move with sign + // extension or zero extension, depending on whether the source type + // was signed. + if ((srcClass < 3) && (targClass < 3) && (srcClass < targClass)) + { + static const unsigned ops[] = { + X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16, + X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16 + }; + unsigned srcSigned = sourceType->isSigned (); + BuildMI (BB, ops[3 * srcSigned + srcClass + targClass - 1], 1, + destReg).addReg (operandReg); + return; + } + // 4) Handle cast of LARGER int to SMALLER int using a move to EAX + // followed by a move out of AX or AL. + if ((srcClass < 3) && (targClass < 3) && (srcClass > targClass)) + { + static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX }; + BuildMI (BB, regRegMove[srcClass], 1, + AReg[srcClass]).addReg (operandReg); + BuildMI (BB, regRegMove[targClass], 1, destReg).addReg (AReg[srcClass]); + return; + } + // Anything we haven't handled already, we can't (yet) handle at all. visitInstruction (CI); }