X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FInstSelectSimple.cpp;h=217b219ba2a4ae47e6d7f5420d61147a06a5a9af;hb=d474e9cdce5aa061e9a340040246592737667cb5;hp=44705586da935807ca83473a7f2a35f1a2d05229;hpb=d5a87f80b719065c87904bcee3c65ab9958ca9a5;p=oota-llvm.git diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp index 44705586da9..217b219ba2a 100644 --- a/lib/Target/X86/InstSelectSimple.cpp +++ b/lib/Target/X86/InstSelectSimple.cpp @@ -6,17 +6,25 @@ #include "X86.h" #include "X86InstrInfo.h" +#include "X86InstrBuilder.h" #include "llvm/Function.h" #include "llvm/iTerminators.h" +#include "llvm/iOperators.h" #include "llvm/iOther.h" +#include "llvm/iPHINode.h" +#include "llvm/iMemory.h" #include "llvm/Type.h" #include "llvm/Constants.h" #include "llvm/Pass.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/Target/TargetMachine.h" #include "llvm/Support/InstVisitor.h" +#include "llvm/Target/MRegisterInfo.h" #include +using namespace MOTy; // Get Use, Def, UseAndDef + namespace { struct ISel : public FunctionPass, InstVisitor { TargetMachine &TM; @@ -36,6 +44,7 @@ namespace { F = &MachineFunction::construct(&Fn, TM); visit(Fn); RegMap.clear(); + CurReg = MRegisterInfo::FirstVirtualRegister; F = 0; return false; // We never modify the LLVM itself. } @@ -54,15 +63,51 @@ namespace { // Visitation methods for various instructions. These methods simply emit // fixed X86 code for each instruction. // + + // Control flow operators void visitReturnInst(ReturnInst &RI); - void visitAdd(BinaryOperator &B); + void visitBranchInst(BranchInst &BI); + void visitCallInst(CallInst &I); + + // Arithmetic operators + void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass); + void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); } + void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); } + void visitMul(BinaryOperator &B); + + void visitDiv(BinaryOperator &B) { visitDivRem(B); } + void visitRem(BinaryOperator &B) { visitDivRem(B); } + void visitDivRem(BinaryOperator &B); + + // Bitwise operators + void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); } + void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); } + void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); } + + // Binary comparison operators + void visitSetCCInst(SetCondInst &I, unsigned OpNum); + void visitSetEQ(SetCondInst &I) { visitSetCCInst(I, 0); } + void visitSetNE(SetCondInst &I) { visitSetCCInst(I, 1); } + void visitSetLT(SetCondInst &I) { visitSetCCInst(I, 2); } + void visitSetGT(SetCondInst &I) { visitSetCCInst(I, 3); } + void visitSetLE(SetCondInst &I) { visitSetCCInst(I, 4); } + void visitSetGE(SetCondInst &I) { visitSetCCInst(I, 5); } + + // Memory Instructions + void visitLoadInst(LoadInst &I); + void visitStoreInst(StoreInst &I); + + // Other operators void visitShiftInst(ShiftInst &I); + void visitPHINode(PHINode &I); + void visitCastInst(CastInst &I); void visitInstruction(Instruction &I) { std::cerr << "Cannot instruction select: " << I; abort(); } + void promote32 (const unsigned targetReg, Value *v); /// copyConstantToRegister - Output the instructions required to put the /// specified constant into the specified register. @@ -76,20 +121,62 @@ namespace { unsigned getReg(Value &V) { return getReg(&V); } // Allow references unsigned getReg(Value *V) { unsigned &Reg = RegMap[V]; - if (Reg == 0) + if (Reg == 0) { Reg = CurReg++; + RegMap[V] = Reg; + + // Add the mapping of regnumber => reg class to MachineFunction + F->addRegMap(Reg, + TM.getRegisterInfo()->getRegClassForType(V->getType())); + } // If this operand is a constant, emit the code to copy the constant into // the register here... // - if (Constant *C = dyn_cast(V)) + if (Constant *C = dyn_cast(V)) { copyConstantToRegister(C, Reg); + } else if (GlobalValue *GV = dyn_cast(V)) { + // Move the address of the global into the register + BuildMI(BB, X86::MOVir32, 1, Reg).addReg(GV); + } else if (Argument *A = dyn_cast(V)) { + std::cerr << "ERROR: Arguments not implemented in SimpleInstSel\n"; + } return Reg; } }; } +/// TypeClass - Used by the X86 backend to group LLVM types by their basic X86 +/// Representation. +/// +enum TypeClass { + cByte, cShort, cInt, cLong, cFloat, cDouble +}; + +/// getClass - Turn a primitive type into a "class" number which is based on the +/// size of the type, and whether or not it is floating point. +/// +static inline TypeClass getClass(const Type *Ty) { + switch (Ty->getPrimitiveID()) { + case Type::SByteTyID: + case Type::UByteTyID: return cByte; // Byte operands are class #0 + case Type::ShortTyID: + case Type::UShortTyID: return cShort; // Short operands are class #1 + case Type::IntTyID: + case Type::UIntTyID: + case Type::PointerTyID: return cInt; // Int's and pointers are class #2 + + case Type::LongTyID: + case Type::ULongTyID: return cLong; // Longs are class #3 + case Type::FloatTyID: return cFloat; // Float is class #4 + case Type::DoubleTyID: return cDouble; // Doubles are class #5 + default: + assert(0 && "Invalid type to getClass!"); + return cByte; // not reached + } +} + /// copyConstantToRegister - Output the instructions required to put the /// specified constant into the specified register. @@ -97,29 +184,133 @@ namespace { void ISel::copyConstantToRegister(Constant *C, unsigned R) { assert (!isa(C) && "Constant expressions not yet handled!\n"); - switch (C->getType()->getPrimitiveID()) { - case Type::SByteTyID: - BuildMI(BB, X86::MOVir8, 1, R).addSImm(cast(C)->getValue()); - break; - case Type::UByteTyID: - BuildMI(BB, X86::MOVir8, 1, R).addZImm(cast(C)->getValue()); + if (C->getType()->isIntegral()) { + unsigned Class = getClass(C->getType()); + assert(Class != 3 && "Type not handled yet!"); + + static const unsigned IntegralOpcodeTab[] = { + X86::MOVir8, X86::MOVir16, X86::MOVir32 + }; + + if (C->getType()->isSigned()) { + ConstantSInt *CSI = cast(C); + BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addSImm(CSI->getValue()); + } else { + ConstantUInt *CUI = cast(C); + BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue()); + } + } else { + assert(0 && "Type not handled yet!"); + } +} + + +/// SetCC instructions - Here we just emit boilerplate code to set a byte-sized +/// register, then move it to wherever the result should be. +/// We handle FP setcc instructions by pushing them, doing a +/// compare-and-pop-twice, and then copying the concodes to the main +/// processor's concodes (I didn't make this up, it's in the Intel manual) +/// +void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) { + // The arguments are already supposed to be of the same type. + const Type *CompTy = I.getOperand(0)->getType(); + unsigned reg1 = getReg(I.getOperand(0)); + unsigned reg2 = getReg(I.getOperand(1)); + + unsigned Class = getClass(CompTy); + switch (Class) { + // Emit: cmp , (do the comparison). We can + // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with + // 32-bit. + case cByte: + BuildMI (BB, X86::CMPrr8, 2).addReg (reg1).addReg (reg2); break; - case Type::ShortTyID: - BuildMI(BB, X86::MOVir16, 1, R).addSImm(cast(C)->getValue()); + case cShort: + BuildMI (BB, X86::CMPrr16, 2).addReg (reg1).addReg (reg2); break; - case Type::UShortTyID: - BuildMI(BB, X86::MOVir16, 1, R).addZImm(cast(C)->getValue()); + case cInt: + BuildMI (BB, X86::CMPrr32, 2).addReg (reg1).addReg (reg2); break; - case Type::IntTyID: - BuildMI(BB, X86::MOVir32, 1, R).addSImm(cast(C)->getValue()); + + // Push the variables on the stack with fldl opcodes. + // FIXME: assuming var1, var2 are in memory, if not, spill to + // stack first + case cFloat: // Floats + BuildMI (BB, X86::FLDr4, 1).addReg (reg1); + BuildMI (BB, X86::FLDr4, 1).addReg (reg2); break; - case Type::UIntTyID: - BuildMI(BB, X86::MOVir32, 1, R).addZImm(cast(C)->getValue()); + case cDouble: // Doubles + BuildMI (BB, X86::FLDr8, 1).addReg (reg1); + BuildMI (BB, X86::FLDr8, 1).addReg (reg2); break; - default: assert(0 && "Type not handled yet!"); + case cLong: + default: + visitInstruction(I); + } + + if (CompTy->isFloatingPoint()) { + // (Non-trapping) compare and pop twice. + BuildMI (BB, X86::FUCOMPP, 0); + // Move fp status word (concodes) to ax. + BuildMI (BB, X86::FNSTSWr8, 1, X86::AX); + // Load real concodes from ax. + BuildMI (BB, X86::SAHF, 1).addReg(X86::AH); } + + // Emit setOp instruction (extract concode; clobbers ax), + // using the following mapping: + // LLVM -> X86 signed X86 unsigned + // ----- ----- ----- + // seteq -> sete sete + // setne -> setne setne + // setlt -> setl setb + // setgt -> setg seta + // setle -> setle setbe + // setge -> setge setae + + static const unsigned OpcodeTab[2][6] = { + {X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAr, X86::SETBEr, X86::SETAEr}, + {X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGr, X86::SETLEr, X86::SETGEr}, + }; + + BuildMI(BB, OpcodeTab[CompTy->isSigned()][OpNum], 0, X86::AL); + + // Put it in the result using a move. + BuildMI (BB, X86::MOVrr8, 1, getReg(I)).addReg(X86::AL); } +/// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide +/// operand, in the specified target register. +void +ISel::promote32 (const unsigned targetReg, Value *v) +{ + unsigned vReg = getReg (v); + unsigned Class = getClass (v->getType ()); + bool isUnsigned = v->getType ()->isUnsigned (); + assert (((Class == cByte) || (Class == cShort) || (Class == cInt)) + && "Unpromotable operand class in promote32"); + switch (Class) + { + case cByte: + // Extend value into target register (8->32) + if (isUnsigned) + BuildMI (BB, X86::MOVZXr32r8, 1, targetReg).addReg (vReg); + else + BuildMI (BB, X86::MOVSXr32r8, 1, targetReg).addReg (vReg); + break; + case cShort: + // Extend value into target register (16->32) + if (isUnsigned) + BuildMI (BB, X86::MOVZXr32r16, 1, targetReg).addReg (vReg); + else + BuildMI (BB, X86::MOVSXr32r16, 1, targetReg).addReg (vReg); + break; + case cInt: + // Move value into target register (32->32) + BuildMI (BB, X86::MOVrr32, 1, targetReg).addReg (vReg); + break; + } +} /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such, /// we have the following possibilities: @@ -129,47 +320,253 @@ void ISel::copyConstantToRegister(Constant *C, unsigned R) { /// ret short, ushort: Extend value into EAX and return /// ret int, uint : Move value into EAX and return /// ret pointer : Move value into EAX and return -/// ret long, ulong : Move value into EAX/EDX (?) and return -/// ret float/double : ? Top of FP stack? XMM0? +/// ret long, ulong : Move value into EAX/EDX and return +/// ret float/double : Top of FP stack +/// +void +ISel::visitReturnInst (ReturnInst &I) +{ + if (I.getNumOperands () == 0) + { + // Emit a 'ret' instruction + BuildMI (BB, X86::RET, 0); + return; + } + Value *rv = I.getOperand (0); + unsigned Class = getClass (rv->getType ()); + switch (Class) + { + // integral return values: extend or move into EAX and return. + case cByte: + case cShort: + case cInt: + promote32 (X86::EAX, rv); + break; + // ret float/double: top of FP stack + // FLD + case cFloat: // Floats + BuildMI (BB, X86::FLDr4, 1).addReg (getReg (rv)); + break; + case cDouble: // Doubles + BuildMI (BB, X86::FLDr8, 1).addReg (getReg (rv)); + break; + case cLong: + // ret long: use EAX(least significant 32 bits)/EDX (most + // significant 32)...uh, I think so Brain, but how do i call + // up the two parts of the value from inside this mouse + // cage? *zort* + default: + visitInstruction (I); + } + // Emit a 'ret' instruction + BuildMI (BB, X86::RET, 0); +} + +/// visitBranchInst - Handle conditional and unconditional branches here. Note +/// that since code layout is frozen at this point, that if we are trying to +/// jump to a block that is the immediate successor of the current block, we can +/// just make a fall-through. (but we don't currently). /// -void ISel::visitReturnInst(ReturnInst &I) { - if (I.getNumOperands() != 0) { // Not 'ret void'? - // Move result into a hard register... then emit a ret - visitInstruction(I); // abort +void +ISel::visitBranchInst (BranchInst & BI) +{ + if (BI.isConditional ()) + { + BasicBlock *ifTrue = BI.getSuccessor (0); + BasicBlock *ifFalse = BI.getSuccessor (1); // this is really unobvious + + // simplest thing I can think of: compare condition with zero, + // followed by jump-if-equal to ifFalse, and jump-if-nonequal to + // ifTrue + unsigned int condReg = getReg (BI.getCondition ()); + BuildMI (BB, X86::CMPri8, 2).addReg (condReg).addZImm (0); + BuildMI (BB, X86::JNE, 1).addPCDisp (BI.getSuccessor (0)); + BuildMI (BB, X86::JE, 1).addPCDisp (BI.getSuccessor (1)); + } + else // unconditional branch + { + BuildMI (BB, X86::JMP, 1).addPCDisp (BI.getSuccessor (0)); + } +} + +/// visitCallInst - Push args on stack and do a procedure call instruction. +void +ISel::visitCallInst (CallInst & CI) +{ + // keep a counter of how many bytes we pushed on the stack + unsigned bytesPushed = 0; + + // Push the arguments on the stack in reverse order, as specified by + // the ABI. + for (unsigned i = CI.getNumOperands()-1; i >= 1; --i) + { + Value *v = CI.getOperand (i); + switch (getClass (v->getType ())) + { + case cByte: + case cShort: + // Promote V to 32 bits wide, and move the result into EAX, + // then push EAX. + promote32 (X86::EAX, v); + BuildMI (BB, X86::PUSHr32, 1).addReg (X86::EAX); + bytesPushed += 4; + break; + case cInt: + case cFloat: { + unsigned Reg = getReg(v); + BuildMI (BB, X86::PUSHr32, 1).addReg(Reg); + bytesPushed += 4; + break; + } + default: + // FIXME: long/ulong/double args not handled. + visitInstruction (CI); + break; + } + } + // Emit a CALL instruction with PC-relative displacement. + BuildMI (BB, X86::CALLpcrel32, 1).addPCDisp (CI.getCalledValue ()); + + // Adjust the stack by `bytesPushed' amount if non-zero + if (bytesPushed > 0) + BuildMI (BB, X86::ADDri32, 2).addReg(X86::ESP).addZImm(bytesPushed); + + // If there is a return value, scavenge the result from the location the call + // leaves it in... + // + if (CI.getType() != Type::VoidTy) { + switch (getClass(CI.getType())) { + case cInt: + BuildMI(BB, X86::MOVrr32, 1, getReg(CI)).addReg(X86::EAX); + break; + + default: + std::cerr << "Cannot get return value for call of type '" + << *CI.getType() << "'\n"; + visitInstruction(CI); + } } +} + +/// visitSimpleBinary - Implement simple binary operators for integral types... +/// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, +/// 4 for Xor. +/// +void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) { + if (B.getType() == Type::BoolTy) // FIXME: Handle bools for logicals + visitInstruction(B); - // Emit a simple 'ret' instruction... appending it to the end of the basic - // block - BuildMI(BB, X86::RET, 0); + unsigned Class = getClass(B.getType()); + if (Class > 2) // FIXME: Handle longs + visitInstruction(B); + + static const unsigned OpcodeTab[][4] = { + // Arithmetic operators + { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, 0 }, // ADD + { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, 0 }, // SUB + + // Bitwise operators + { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND + { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR + { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR + }; + + unsigned Opcode = OpcodeTab[OperatorClass][Class]; + unsigned Op0r = getReg(B.getOperand(0)); + unsigned Op1r = getReg(B.getOperand(1)); + BuildMI(BB, Opcode, 2, getReg(B)).addReg(Op0r).addReg(Op1r); } -/// SimpleLog2 - Compute and return Log2 of the input, valid only for inputs 1, -/// 2, 4, & 8. Used to convert operand size into dense classes. +/// visitMul - Multiplies are not simple binary operators because they must deal +/// with the EAX register explicitly. /// -static inline unsigned SimpleLog2(unsigned N) { - switch (N) { - case 1: return 0; - case 2: return 1; - case 4: return 2; - case 8: return 3; - default: assert(0 && "Invalid operand to SimpleLog2!"); +void ISel::visitMul(BinaryOperator &I) { + unsigned Class = getClass(I.getType()); + if (Class > 2) // FIXME: Handle longs + visitInstruction(I); + + static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX }; + static const unsigned MulOpcode[]={ X86::MULrr8, X86::MULrr16, X86::MULrr32 }; + static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 }; + + unsigned Reg = Regs[Class]; + unsigned Op0Reg = getReg(I.getOperand(0)); + unsigned Op1Reg = getReg(I.getOperand(1)); + + // Put the first operand into one of the A registers... + BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg); + + // Emit the appropriate multiply instruction... + BuildMI(BB, MulOpcode[Class], 1).addReg(Op1Reg); + + // Put the result into the destination register... + BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(Reg); +} + + +/// visitDivRem - Handle division and remainder instructions... these +/// instruction both require the same instructions to be generated, they just +/// select the result from a different register. Note that both of these +/// instructions work differently for signed and unsigned operands. +/// +void ISel::visitDivRem(BinaryOperator &I) { + unsigned Class = getClass(I.getType()); + if (Class > 2) // FIXME: Handle longs + visitInstruction(I); + + static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX }; + static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 }; + static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CDQ }; + static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 }; + static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX }; + + static const unsigned DivOpcode[][4] = { + { X86::DIVrr8 , X86::DIVrr16 , X86::DIVrr32 , 0 }, // Unsigned division + { X86::IDIVrr8, X86::IDIVrr16, X86::IDIVrr32, 0 }, // Signed division + }; + + bool isSigned = I.getType()->isSigned(); + unsigned Reg = Regs[Class]; + unsigned ExtReg = ExtRegs[Class]; + unsigned Op0Reg = getReg(I.getOperand(0)); + unsigned Op1Reg = getReg(I.getOperand(1)); + + // Put the first operand into one of the A registers... + BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg); + + if (isSigned) { + // Emit a sign extension instruction... + BuildMI(BB, ExtOpcode[Class], 0); + } else { + // If unsigned, emit a zeroing instruction... (reg = xor reg, reg) + BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg); } - return 0; // not reached + + // Emit the appropriate divide or remainder instruction... + BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg); + + // Figure out which register we want to pick the result out of... + unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg; + + // Put the result into the destination register... + BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(DestReg); } + /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here /// for constant immediate shift values, and for constant immediate /// shift values equal to 1. Even the general case is sort of special, /// because the shift amount has to be in CL, not just any old register. /// -void -ISel::visitShiftInst (ShiftInst & I) -{ - unsigned Op0r = getReg (I.getOperand (0)); - unsigned DestReg = getReg (I); - bool isRightShift = (I.getOpcode () == Instruction::Shr); - bool isOperandUnsigned = I.getType ()->isUnsigned (); - unsigned OperandClass = SimpleLog2(I.getType()->getPrimitiveSize()); +void ISel::visitShiftInst (ShiftInst &I) { + unsigned Op0r = getReg (I.getOperand(0)); + unsigned DestReg = getReg(I); + bool isLeftShift = I.getOpcode() == Instruction::Shl; + bool isOperandSigned = I.getType()->isUnsigned(); + unsigned OperandClass = getClass(I.getType()); + + if (OperandClass > 2) + visitInstruction(I); // Can't handle longs yet! if (ConstantUInt *CUI = dyn_cast (I.getOperand (1))) { @@ -177,79 +574,18 @@ ISel::visitShiftInst (ShiftInst & I) assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?"); unsigned char shAmt = CUI->getValue(); + static const unsigned ConstantOperand[][4] = { + { X86::SHRir8, X86::SHRir16, X86::SHRir32, 0 }, // SHR + { X86::SARir8, X86::SARir16, X86::SARir32, 0 }, // SAR + { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SHL + { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SAL = SHL + }; + + const unsigned *OpTab = // Figure out the operand table to use + ConstantOperand[isLeftShift*2+isOperandSigned]; + // Emit: reg, shamt (shift-by-immediate opcode "ir" form.) - if (isRightShift) - { - if (isOperandUnsigned) - { - // This is a shift right logical (SHR). - switch (OperandClass) - { - case 0: - BuildMI (BB, X86::SHRir8, 2, - DestReg).addReg (Op0r).addZImm (shAmt); - break; - case 1: - BuildMI (BB, X86::SHRir16, 2, - DestReg).addReg (Op0r).addZImm (shAmt); - break; - case 2: - BuildMI (BB, X86::SHRir32, 2, - DestReg).addReg (Op0r).addZImm (shAmt); - break; - case 3: - default: - visitInstruction (I); - break; - } - } - else - { - // This is a shift right arithmetic (SAR). - switch (OperandClass) - { - case 0: - BuildMI (BB, X86::SARir8, 2, - DestReg).addReg (Op0r).addZImm (shAmt); - break; - case 1: - BuildMI (BB, X86::SARir16, 2, - DestReg).addReg (Op0r).addZImm (shAmt); - break; - case 2: - BuildMI (BB, X86::SARir32, 2, - DestReg).addReg (Op0r).addZImm (shAmt); - break; - case 3: - default: - visitInstruction (I); - break; - } - } - } - else - { - // This is a left shift (SHL). - switch (OperandClass) - { - case 0: - BuildMI (BB, X86::SHLir8, 2, - DestReg).addReg (Op0r).addZImm (shAmt); - break; - case 1: - BuildMI (BB, X86::SHLir16, 2, - DestReg).addReg (Op0r).addZImm (shAmt); - break; - case 2: - BuildMI (BB, X86::SHLir32, 2, - DestReg).addReg (Op0r).addZImm (shAmt); - break; - case 3: - default: - visitInstruction (I); - break; - } - } + BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addZImm(shAmt); } else { @@ -259,113 +595,145 @@ ISel::visitShiftInst (ShiftInst & I) // that amount is already in the CL register, so we have to put it // there first. // - // Get it from the register it's in. - unsigned Op1r = getReg (I.getOperand (1)); + // Emit: move cl, shiftAmount (put the shift amount in CL.) - BuildMI (BB, X86::MOVrr8, 2, X86::CL).addReg (Op1r); - // Emit: reg, cl (shift-by-CL opcode; "rr" form.) - if (isRightShift) - { - if (OperandClass) - { - // This is a shift right logical (SHR). - switch (OperandClass) - { - case 0: - BuildMI (BB, X86::SHRrr8, 2, - DestReg).addReg (Op0r).addReg (X86::CL); - break; - case 1: - BuildMI (BB, X86::SHRrr16, 2, - DestReg).addReg (Op0r).addReg (X86::CL); - break; - case 2: - BuildMI (BB, X86::SHRrr32, 2, - DestReg).addReg (Op0r).addReg (X86::CL); - break; - case 3: - default: - visitInstruction (I); - break; - } - } - else - { - // This is a shift right arithmetic (SAR). - switch (OperandClass) - { - case 0: - BuildMI (BB, X86::SARrr8, 2, - DestReg).addReg (Op0r).addReg (X86::CL); - break; - case 1: - BuildMI (BB, X86::SARrr16, 2, - DestReg).addReg (Op0r).addReg (X86::CL); - break; - case 2: - BuildMI (BB, X86::SARrr32, 2, - DestReg).addReg (Op0r).addReg (X86::CL); - break; - case 3: - default: - visitInstruction (I); - break; - } - } - } - else - { - // This is a left shift (SHL). - switch (OperandClass) - { - case 0: - BuildMI (BB, X86::SHLrr8, 2, - DestReg).addReg (Op0r).addReg (X86::CL); - break; - case 1: - BuildMI (BB, X86::SHLrr16, 2, - DestReg).addReg (Op0r).addReg (X86::CL); - break; - case 2: - BuildMI (BB, X86::SHLrr32, 2, - DestReg).addReg (Op0r).addReg (X86::CL); - break; - case 3: - default: - visitInstruction (I); - break; - } - } + BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(getReg(I.getOperand(1))); + + // This is a shift right (SHR). + static const unsigned NonConstantOperand[][4] = { + { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32, 0 }, // SHR + { X86::SARrr8, X86::SARrr16, X86::SARrr32, 0 }, // SAR + { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SHL + { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SAL = SHL + }; + + const unsigned *OpTab = // Figure out the operand table to use + NonConstantOperand[isLeftShift*2+isOperandSigned]; + + BuildMI(BB, OpTab[OperandClass], 1, DestReg).addReg(Op0r); } } -/// 'add' instruction - Simply turn this into an x86 reg,reg add instruction. -void ISel::visitAdd(BinaryOperator &B) { - unsigned Op0r = getReg(B.getOperand(0)), Op1r = getReg(B.getOperand(1)); - unsigned DestReg = getReg(B); +/// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov' +/// instruction. +/// +void ISel::visitLoadInst(LoadInst &I) { + unsigned Class = getClass(I.getType()); + if (Class > 2) // FIXME: Handle longs and others... + visitInstruction(I); - switch (B.getType()->getPrimitiveSize()) { - case 1: // UByte, SByte - BuildMI(BB, X86::ADDrr8, 2, DestReg).addReg(Op0r).addReg(Op1r); - break; - case 2: // UShort, Short - BuildMI(BB, X86::ADDrr16, 2, DestReg).addReg(Op0r).addReg(Op1r); - break; - case 4: // UInt, Int - BuildMI(BB, X86::ADDrr32, 2, DestReg).addReg(Op0r).addReg(Op1r); - break; - case 8: // ULong, Long - // Here we have a pair of operands each occupying a pair of registers. - // We need to do an ADDrr32 of the least-significant pair immediately - // followed by an ADCrr32 (Add with Carry) of the most-significant pair. - // I don't know how we are representing these multi-register arguments. - default: - visitInstruction(B); // abort - } + static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 }; + + unsigned AddressReg = getReg(I.getOperand(0)); + addDirectMem(BuildMI(BB, Opcode[Class], 4, getReg(I)), AddressReg); +} + + +/// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov' +/// instruction. +/// +void ISel::visitStoreInst(StoreInst &I) { + unsigned Class = getClass(I.getOperand(0)->getType()); + if (Class > 2) // FIXME: Handle longs and others... + visitInstruction(I); + + static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 }; + + unsigned ValReg = getReg(I.getOperand(0)); + unsigned AddressReg = getReg(I.getOperand(1)); + addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg); } +/// visitPHINode - Turn an LLVM PHI node into an X86 PHI node... +/// +void ISel::visitPHINode(PHINode &PN) { + MachineInstr *MI = BuildMI(BB, X86::PHI, PN.getNumOperands(), getReg(PN)); + + for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) { + // FIXME: This will put constants after the PHI nodes in the block, which + // is invalid. They should be put inline into the PHI node eventually. + // + MI->addRegOperand(getReg(PN.getIncomingValue(i))); + MI->addPCDispOperand(PN.getIncomingBlock(i)); + } +} + +/// visitCastInst - Here we have various kinds of copying with or without +/// sign extension going on. +void +ISel::visitCastInst (CastInst &CI) +{ + const Type *targetType = CI.getType (); + Value *operand = CI.getOperand (0); + unsigned int operandReg = getReg (operand); + const Type *sourceType = operand->getType (); + unsigned int destReg = getReg (CI); + // + // Currently we handle: + // + // 1) cast * to bool + // + // 2) cast {sbyte, ubyte} to {sbyte, ubyte} + // cast {short, ushort} to {ushort, short} + // cast {int, uint, ptr} to {int, uint, ptr} + // + // 3) cast {sbyte, ubyte} to {ushort, short} + // cast {sbyte, ubyte} to {int, uint, ptr} + // cast {short, ushort} to {int, uint, ptr} + // + // 4) cast {int, uint, ptr} to {short, ushort} + // cast {int, uint, ptr} to {sbyte, ubyte} + // cast {short, ushort} to {sbyte, ubyte} + // + // 1) Implement casts to bool by using compare on the operand followed + // by set if not zero on the result. + if (targetType == Type::BoolTy) + { + BuildMI (BB, X86::CMPri8, 2).addReg (operandReg).addZImm (0); + BuildMI (BB, X86::SETNEr, 1, destReg); + return; + } + // 2) Implement casts between values of the same type class (as determined + // by getClass) by using a register-to-register move. + unsigned int srcClass = getClass (sourceType); + unsigned int targClass = getClass (targetType); + static const unsigned regRegMove[] = { + X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 + }; + if ((srcClass < 3) && (targClass < 3) && (srcClass == targClass)) + { + BuildMI (BB, regRegMove[srcClass], 1, destReg).addReg (operandReg); + return; + } + // 3) Handle cast of SMALLER int to LARGER int using a move with sign + // extension or zero extension, depending on whether the source type + // was signed. + if ((srcClass < 3) && (targClass < 3) && (srcClass < targClass)) + { + static const unsigned ops[] = { + X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16, + X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16 + }; + unsigned srcSigned = sourceType->isSigned (); + BuildMI (BB, ops[3 * srcSigned + srcClass + targClass - 1], 1, + destReg).addReg (operandReg); + return; + } + // 4) Handle cast of LARGER int to SMALLER int using a move to EAX + // followed by a move out of AX or AL. + if ((srcClass < 3) && (targClass < 3) && (srcClass > targClass)) + { + static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX }; + BuildMI (BB, regRegMove[srcClass], 1, + AReg[srcClass]).addReg (operandReg); + BuildMI (BB, regRegMove[targClass], 1, destReg).addReg (AReg[srcClass]); + return; + } + // Anything we haven't handled already, we can't (yet) handle at all. + visitInstruction (CI); +} /// createSimpleX86InstructionSelector - This pass converts an LLVM function /// into a machine code representation is a very simple peep-hole fashion. The