X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FInstSelectSimple.cpp;h=217b219ba2a4ae47e6d7f5420d61147a06a5a9af;hb=d474e9cdce5aa061e9a340040246592737667cb5;hp=d174699a10e60a4a21b0a9d196ffa00f57776a31;hpb=05093a51b4b3bfaff33ee17b92ccab1711dc10ab;p=oota-llvm.git diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp index d174699a10e..217b219ba2a 100644 --- a/lib/Target/X86/InstSelectSimple.cpp +++ b/lib/Target/X86/InstSelectSimple.cpp @@ -44,6 +44,7 @@ namespace { F = &MachineFunction::construct(&Fn, TM); visit(Fn); RegMap.clear(); + CurReg = MRegisterInfo::FirstVirtualRegister; F = 0; return false; // We never modify the LLVM itself. } @@ -62,8 +63,11 @@ namespace { // Visitation methods for various instructions. These methods simply emit // fixed X86 code for each instruction. // + + // Control flow operators void visitReturnInst(ReturnInst &RI); void visitBranchInst(BranchInst &BI); + void visitCallInst(CallInst &I); // Arithmetic operators void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass); @@ -96,12 +100,14 @@ namespace { // Other operators void visitShiftInst(ShiftInst &I); void visitPHINode(PHINode &I); + void visitCastInst(CastInst &I); void visitInstruction(Instruction &I) { std::cerr << "Cannot instruction select: " << I; abort(); } + void promote32 (const unsigned targetReg, Value *v); /// copyConstantToRegister - Output the instructions required to put the /// specified constant into the specified register. @@ -127,8 +133,14 @@ namespace { // If this operand is a constant, emit the code to copy the constant into // the register here... // - if (Constant *C = dyn_cast(V)) + if (Constant *C = dyn_cast(V)) { copyConstantToRegister(C, Reg); + } else if (GlobalValue *GV = dyn_cast(V)) { + // Move the address of the global into the register + BuildMI(BB, X86::MOVir32, 1, Reg).addReg(GV); + } else if (Argument *A = dyn_cast(V)) { + std::cerr << "ERROR: Arguments not implemented in SimpleInstSel\n"; + } return Reg; } @@ -224,12 +236,12 @@ void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) { // FIXME: assuming var1, var2 are in memory, if not, spill to // stack first case cFloat: // Floats - BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg1); - BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg2); + BuildMI (BB, X86::FLDr4, 1).addReg (reg1); + BuildMI (BB, X86::FLDr4, 1).addReg (reg2); break; case cDouble: // Doubles - BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg1); - BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg2); + BuildMI (BB, X86::FLDr8, 1).addReg (reg1); + BuildMI (BB, X86::FLDr8, 1).addReg (reg2); break; case cLong: default: @@ -257,8 +269,8 @@ void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) { // setge -> setge setae static const unsigned OpcodeTab[2][6] = { - { X86::SETE, X86::SETNE, X86::SETB, X86::SETA, X86::SETBE, X86::SETAE }, - { X86::SETE, X86::SETNE, X86::SETL, X86::SETG, X86::SETLE, X86::SETGE }, + {X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAr, X86::SETBEr, X86::SETAEr}, + {X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGr, X86::SETLEr, X86::SETGEr}, }; BuildMI(BB, OpcodeTab[CompTy->isSigned()][OpNum], 0, X86::AL); @@ -267,6 +279,38 @@ void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) { BuildMI (BB, X86::MOVrr8, 1, getReg(I)).addReg(X86::AL); } +/// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide +/// operand, in the specified target register. +void +ISel::promote32 (const unsigned targetReg, Value *v) +{ + unsigned vReg = getReg (v); + unsigned Class = getClass (v->getType ()); + bool isUnsigned = v->getType ()->isUnsigned (); + assert (((Class == cByte) || (Class == cShort) || (Class == cInt)) + && "Unpromotable operand class in promote32"); + switch (Class) + { + case cByte: + // Extend value into target register (8->32) + if (isUnsigned) + BuildMI (BB, X86::MOVZXr32r8, 1, targetReg).addReg (vReg); + else + BuildMI (BB, X86::MOVSXr32r8, 1, targetReg).addReg (vReg); + break; + case cShort: + // Extend value into target register (16->32) + if (isUnsigned) + BuildMI (BB, X86::MOVZXr32r16, 1, targetReg).addReg (vReg); + else + BuildMI (BB, X86::MOVSXr32r16, 1, targetReg).addReg (vReg); + break; + case cInt: + // Move value into target register (32->32) + BuildMI (BB, X86::MOVrr32, 1, targetReg).addReg (vReg); + break; + } +} /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such, /// we have the following possibilities: @@ -279,56 +323,43 @@ void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) { /// ret long, ulong : Move value into EAX/EDX and return /// ret float/double : Top of FP stack /// -void ISel::visitReturnInst (ReturnInst &I) { - if (I.getNumOperands() == 0) { - // Emit a 'ret' instruction - BuildMI(BB, X86::RET, 0); - return; - } - - unsigned val = getReg(I.getOperand(0)); - unsigned Class = getClass(I.getOperand(0)->getType()); - bool isUnsigned = I.getOperand(0)->getType()->isUnsigned(); - switch (Class) { - case cByte: - // ret sbyte, ubyte: Extend value into EAX and return - if (isUnsigned) - BuildMI (BB, X86::MOVZXr32r8, 1, X86::EAX).addReg (val); - else - BuildMI (BB, X86::MOVSXr32r8, 1, X86::EAX).addReg (val); - break; - case cShort: - // ret short, ushort: Extend value into EAX and return - if (isUnsigned) - BuildMI (BB, X86::MOVZXr32r16, 1, X86::EAX).addReg (val); - else - BuildMI (BB, X86::MOVSXr32r16, 1, X86::EAX).addReg (val); - break; - case cInt: - // ret int, uint, ptr: Move value into EAX and return - // MOV EAX, - BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(val); - break; - - // ret float/double: top of FP stack - // FLD - case cFloat: // Floats - BuildMI(BB, X86::FLDr4, 1).addReg(val); - break; - case cDouble: // Doubles - BuildMI(BB, X86::FLDr8, 1).addReg(val); - break; - case cLong: - // ret long: use EAX(least significant 32 bits)/EDX (most - // significant 32)...uh, I think so Brain, but how do i call - // up the two parts of the value from inside this mouse - // cage? *zort* - default: - visitInstruction(I); - } - +void +ISel::visitReturnInst (ReturnInst &I) +{ + if (I.getNumOperands () == 0) + { + // Emit a 'ret' instruction + BuildMI (BB, X86::RET, 0); + return; + } + Value *rv = I.getOperand (0); + unsigned Class = getClass (rv->getType ()); + switch (Class) + { + // integral return values: extend or move into EAX and return. + case cByte: + case cShort: + case cInt: + promote32 (X86::EAX, rv); + break; + // ret float/double: top of FP stack + // FLD + case cFloat: // Floats + BuildMI (BB, X86::FLDr4, 1).addReg (getReg (rv)); + break; + case cDouble: // Doubles + BuildMI (BB, X86::FLDr8, 1).addReg (getReg (rv)); + break; + case cLong: + // ret long: use EAX(least significant 32 bits)/EDX (most + // significant 32)...uh, I think so Brain, but how do i call + // up the two parts of the value from inside this mouse + // cage? *zort* + default: + visitInstruction (I); + } // Emit a 'ret' instruction - BuildMI(BB, X86::RET, 0); + BuildMI (BB, X86::RET, 0); } /// visitBranchInst - Handle conditional and unconditional branches here. Note @@ -358,6 +389,64 @@ ISel::visitBranchInst (BranchInst & BI) } } +/// visitCallInst - Push args on stack and do a procedure call instruction. +void +ISel::visitCallInst (CallInst & CI) +{ + // keep a counter of how many bytes we pushed on the stack + unsigned bytesPushed = 0; + + // Push the arguments on the stack in reverse order, as specified by + // the ABI. + for (unsigned i = CI.getNumOperands()-1; i >= 1; --i) + { + Value *v = CI.getOperand (i); + switch (getClass (v->getType ())) + { + case cByte: + case cShort: + // Promote V to 32 bits wide, and move the result into EAX, + // then push EAX. + promote32 (X86::EAX, v); + BuildMI (BB, X86::PUSHr32, 1).addReg (X86::EAX); + bytesPushed += 4; + break; + case cInt: + case cFloat: { + unsigned Reg = getReg(v); + BuildMI (BB, X86::PUSHr32, 1).addReg(Reg); + bytesPushed += 4; + break; + } + default: + // FIXME: long/ulong/double args not handled. + visitInstruction (CI); + break; + } + } + // Emit a CALL instruction with PC-relative displacement. + BuildMI (BB, X86::CALLpcrel32, 1).addPCDisp (CI.getCalledValue ()); + + // Adjust the stack by `bytesPushed' amount if non-zero + if (bytesPushed > 0) + BuildMI (BB, X86::ADDri32, 2).addReg(X86::ESP).addZImm(bytesPushed); + + // If there is a return value, scavenge the result from the location the call + // leaves it in... + // + if (CI.getType() != Type::VoidTy) { + switch (getClass(CI.getType())) { + case cInt: + BuildMI(BB, X86::MOVrr32, 1, getReg(CI)).addReg(X86::EAX); + break; + + default: + std::cerr << "Cannot get return value for call of type '" + << *CI.getType() << "'\n"; + visitInstruction(CI); + } + } +} /// visitSimpleBinary - Implement simple binary operators for integral types... /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, @@ -397,12 +486,10 @@ void ISel::visitMul(BinaryOperator &I) { visitInstruction(I); static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX }; - static const unsigned Clobbers[] ={ X86::AH , X86::DX , X86::EDX }; static const unsigned MulOpcode[]={ X86::MULrr8, X86::MULrr16, X86::MULrr32 }; static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 }; unsigned Reg = Regs[Class]; - unsigned Clobber = Clobbers[Class]; unsigned Op0Reg = getReg(I.getOperand(0)); unsigned Op1Reg = getReg(I.getOperand(1)); @@ -410,8 +497,7 @@ void ISel::visitMul(BinaryOperator &I) { BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg); // Emit the appropriate multiply instruction... - BuildMI(BB, MulOpcode[Class], 3) - .addReg(Reg, UseAndDef).addReg(Op1Reg).addClobber(Clobber); + BuildMI(BB, MulOpcode[Class], 1).addReg(Op1Reg); // Put the result into the destination register... BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(Reg); @@ -450,15 +536,14 @@ void ISel::visitDivRem(BinaryOperator &I) { if (isSigned) { // Emit a sign extension instruction... - BuildMI(BB, ExtOpcode[Class], 1, ExtReg).addReg(Reg); + BuildMI(BB, ExtOpcode[Class], 0); } else { // If unsigned, emit a zeroing instruction... (reg = xor reg, reg) BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg); } // Emit the appropriate divide or remainder instruction... - BuildMI(BB, DivOpcode[isSigned][Class], 2) - .addReg(Reg, UseAndDef).addReg(ExtReg, UseAndDef).addReg(Op1Reg); + BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg); // Figure out which register we want to pick the result out of... unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg; @@ -525,7 +610,7 @@ void ISel::visitShiftInst (ShiftInst &I) { const unsigned *OpTab = // Figure out the operand table to use NonConstantOperand[isLeftShift*2+isOperandSigned]; - BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addReg(X86::CL); + BuildMI(BB, OpTab[OperandClass], 1, DestReg).addReg(Op0r); } } @@ -575,6 +660,80 @@ void ISel::visitPHINode(PHINode &PN) { } } +/// visitCastInst - Here we have various kinds of copying with or without +/// sign extension going on. +void +ISel::visitCastInst (CastInst &CI) +{ + const Type *targetType = CI.getType (); + Value *operand = CI.getOperand (0); + unsigned int operandReg = getReg (operand); + const Type *sourceType = operand->getType (); + unsigned int destReg = getReg (CI); + // + // Currently we handle: + // + // 1) cast * to bool + // + // 2) cast {sbyte, ubyte} to {sbyte, ubyte} + // cast {short, ushort} to {ushort, short} + // cast {int, uint, ptr} to {int, uint, ptr} + // + // 3) cast {sbyte, ubyte} to {ushort, short} + // cast {sbyte, ubyte} to {int, uint, ptr} + // cast {short, ushort} to {int, uint, ptr} + // + // 4) cast {int, uint, ptr} to {short, ushort} + // cast {int, uint, ptr} to {sbyte, ubyte} + // cast {short, ushort} to {sbyte, ubyte} + // + // 1) Implement casts to bool by using compare on the operand followed + // by set if not zero on the result. + if (targetType == Type::BoolTy) + { + BuildMI (BB, X86::CMPri8, 2).addReg (operandReg).addZImm (0); + BuildMI (BB, X86::SETNEr, 1, destReg); + return; + } + // 2) Implement casts between values of the same type class (as determined + // by getClass) by using a register-to-register move. + unsigned int srcClass = getClass (sourceType); + unsigned int targClass = getClass (targetType); + static const unsigned regRegMove[] = { + X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 + }; + if ((srcClass < 3) && (targClass < 3) && (srcClass == targClass)) + { + BuildMI (BB, regRegMove[srcClass], 1, destReg).addReg (operandReg); + return; + } + // 3) Handle cast of SMALLER int to LARGER int using a move with sign + // extension or zero extension, depending on whether the source type + // was signed. + if ((srcClass < 3) && (targClass < 3) && (srcClass < targClass)) + { + static const unsigned ops[] = { + X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16, + X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16 + }; + unsigned srcSigned = sourceType->isSigned (); + BuildMI (BB, ops[3 * srcSigned + srcClass + targClass - 1], 1, + destReg).addReg (operandReg); + return; + } + // 4) Handle cast of LARGER int to SMALLER int using a move to EAX + // followed by a move out of AX or AL. + if ((srcClass < 3) && (targClass < 3) && (srcClass > targClass)) + { + static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX }; + BuildMI (BB, regRegMove[srcClass], 1, + AReg[srcClass]).addReg (operandReg); + BuildMI (BB, regRegMove[targClass], 1, destReg).addReg (AReg[srcClass]); + return; + } + // Anything we haven't handled already, we can't (yet) handle at all. + visitInstruction (CI); +} /// createSimpleX86InstructionSelector - This pass converts an LLVM function /// into a machine code representation is a very simple peep-hole fashion. The