X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FInstSelectSimple.cpp;h=223fcb1c20cfbfbde787d431f3dd5962ffdb5ccf;hb=538607fe457a77d6125f60a29371e8838ea81167;hp=6712d94f32460b9bbbf14daea15f5ad6d73ad72b;hpb=36143fc4440ac1fc2a0fc95a4999bcadc3ec207d;p=oota-llvm.git diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp index 6712d94f324..223fcb1c20c 100644 --- a/lib/Target/X86/InstSelectSimple.cpp +++ b/lib/Target/X86/InstSelectSimple.cpp @@ -1,58 +1,49 @@ //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// // // This file defines a simple peephole instruction selector for the x86 target // //===----------------------------------------------------------------------===// #include "X86.h" -#include "X86InstrInfo.h" #include "X86InstrBuilder.h" +#include "X86InstrInfo.h" +#include "llvm/Constants.h" +#include "llvm/DerivedTypes.h" #include "llvm/Function.h" #include "llvm/Instructions.h" -#include "llvm/DerivedTypes.h" -#include "llvm/Constants.h" +#include "llvm/IntrinsicLowering.h" #include "llvm/Pass.h" -#include "llvm/Intrinsics.h" +#include "llvm/CodeGen/MachineConstantPool.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/SSARegMap.h" -#include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/MachineConstantPool.h" -#include "llvm/Target/TargetMachine.h" #include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Support/GetElementPtrTypeIterator.h" #include "llvm/Support/InstVisitor.h" +#include "llvm/Support/CFG.h" +#include "Support/Statistic.h" +using namespace llvm; -/// BMI - A special BuildMI variant that takes an iterator to insert the -/// instruction at as well as a basic block. This is the version for when you -/// have a destination register in mind. -inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB, - MachineBasicBlock::iterator &I, - int Opcode, unsigned NumOperands, - unsigned DestReg) { - assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!"); - MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true); - I = MBB->insert(I, MI)+1; - return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def); -} - -/// BMI - A special BuildMI variant that takes an iterator to insert the -/// instruction at as well as a basic block. -inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB, - MachineBasicBlock::iterator &I, - int Opcode, unsigned NumOperands) { - assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!"); - MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true); - I = MBB->insert(I, MI)+1; - return MachineInstrBuilder(MI); +namespace { + Statistic<> + NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added"); } - namespace { struct ISel : public FunctionPass, InstVisitor { TargetMachine &TM; MachineFunction *F; // The function we are compiling into MachineBasicBlock *BB; // The current MBB we are compiling int VarArgsFrameIndex; // FrameIndex for start of varargs area + int ReturnAddressIndex; // FrameIndex for the return address std::map RegMap; // Mapping between Val's and SSA Regs @@ -65,6 +56,10 @@ namespace { /// the entire function. /// bool runOnFunction(Function &Fn) { + // First pass over the function, lower any unknown intrinsic functions + // with the IntrinsicLowering class. + LowerUnknownIntrinsicFunctionCalls(Fn); + F = &MachineFunction::construct(&Fn, TM); // Create all of the machine basic blocks for the function... @@ -73,6 +68,10 @@ namespace { BB = &F->front(); + // Set up a frame object for the return address. This is used by the + // llvm.returnaddress & llvm.frameaddress intrinisics. + ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4); + // Copy incoming arguments off of the stack... LoadArgumentsToVirtualRegs(Fn); @@ -82,6 +81,9 @@ namespace { // Select the PHI nodes SelectPHINodes(); + // Insert the FP_REG_KILL instructions into blocks that need them. + InsertFPRegKills(); + RegMap.clear(); MBBMap.clear(); F = 0; @@ -102,6 +104,12 @@ namespace { BB = MBBMap[&LLVM_BB]; } + /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the + /// function, lowering any calls to unknown intrinsic functions into the + /// equivalent LLVM code. + /// + void LowerUnknownIntrinsicFunctionCalls(Function &F); + /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function /// from the stack into virtual registers. /// @@ -113,6 +121,12 @@ namespace { /// void SelectPHINodes(); + /// InsertFPRegKills - Insert FP_REG_KILL instructions into basic blocks + /// that need them. This only occurs due to the floating point stackifier + /// not being aggressive enough to handle arbitrary global stackification. + /// + void InsertFPRegKills(); + // Visitation methods for various instructions. These methods simply emit // fixed X86 code for each instruction. // @@ -129,19 +143,21 @@ namespace { ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {} }; void doCall(const ValueRecord &Ret, MachineInstr *CallMI, - const std::vector &Args); + const std::vector &Args); void visitCallInst(CallInst &I); - void visitInvokeInst(InvokeInst &II); - void visitUnwindInst(UnwindInst &UI); - void visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &I); + void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I); // Arithmetic operators void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass); void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); } void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); } - void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI, + void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, const Type *DestTy, - unsigned Op0Reg, unsigned Op1Reg); + unsigned Op0Reg, unsigned Op1Reg); + void doMultiplyConst(MachineBasicBlock *MBB, + MachineBasicBlock::iterator MBBI, + unsigned DestReg, const Type *DestTy, + unsigned Op0Reg, unsigned Op1Val); void visitMul(BinaryOperator &B); void visitDiv(BinaryOperator &B) { visitDivRem(B); } @@ -155,16 +171,12 @@ namespace { // Comparison operators... void visitSetCondInst(SetCondInst &I); - bool EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1, - MachineBasicBlock *MBB, - MachineBasicBlock::iterator &MBBI); - + unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1, + MachineBasicBlock *MBB, + MachineBasicBlock::iterator MBBI); + // Memory Instructions - MachineInstr *doFPLoad(MachineBasicBlock *MBB, - MachineBasicBlock::iterator &MBBI, - const Type *Ty, unsigned DestReg); void visitLoadInst(LoadInst &I); - void doFPStore(const Type *Ty, unsigned DestAddrReg, unsigned SrcReg); void visitStoreInst(StoreInst &I); void visitGetElementPtrInst(GetElementPtrInst &I); void visitAllocaInst(AllocaInst &I); @@ -175,7 +187,8 @@ namespace { void visitShiftInst(ShiftInst &I); void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass void visitCastInst(CastInst &I); - void visitVarArgInst(VarArgInst &I); + void visitVANextInst(VANextInst &I); + void visitVAArgInst(VAArgInst &I); void visitInstruction(Instruction &I) { std::cerr << "Cannot instruction select: " << I; @@ -186,42 +199,68 @@ namespace { /// void promote32(unsigned targetReg, const ValueRecord &VR); - /// EmitByteSwap - Byteswap SrcReg into DestReg. - /// - void EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class); - + // getGEPIndex - This is used to fold GEP instructions into X86 addressing + // expressions. + void getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP, + std::vector &GEPOps, + std::vector &GEPTypes, unsigned &BaseReg, + unsigned &Scale, unsigned &IndexReg, unsigned &Disp); + + /// isGEPFoldable - Return true if the specified GEP can be completely + /// folded into the addressing mode of a load/store or lea instruction. + bool isGEPFoldable(MachineBasicBlock *MBB, + Value *Src, User::op_iterator IdxBegin, + User::op_iterator IdxEnd, unsigned &BaseReg, + unsigned &Scale, unsigned &IndexReg, unsigned &Disp); + /// emitGEPOperation - Common code shared between visitGetElementPtrInst and /// constant expression GEP support. /// - void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator&IP, + void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP, Value *Src, User::op_iterator IdxBegin, User::op_iterator IdxEnd, unsigned TargetReg); /// emitCastOperation - Common code shared between visitCastInst and /// constant expression cast support. - void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator&IP, + /// + void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP, Value *Src, const Type *DestTy, unsigned TargetReg); /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary /// and constant expression support. + /// void emitSimpleBinaryOperation(MachineBasicBlock *BB, - MachineBasicBlock::iterator &IP, + MachineBasicBlock::iterator IP, Value *Op0, Value *Op1, unsigned OperatorClass, unsigned TargetReg); + void emitDivRemOperation(MachineBasicBlock *BB, + MachineBasicBlock::iterator IP, + unsigned Op0Reg, unsigned Op1Reg, bool isDiv, + const Type *Ty, unsigned TargetReg); + /// emitSetCCOperation - Common code shared between visitSetCondInst and /// constant expression support. + /// void emitSetCCOperation(MachineBasicBlock *BB, - MachineBasicBlock::iterator &IP, + MachineBasicBlock::iterator IP, Value *Op0, Value *Op1, unsigned Opcode, unsigned TargetReg); - + + /// emitShiftOperation - Common code shared between visitShiftInst and + /// constant expression support. + /// + void emitShiftOperation(MachineBasicBlock *MBB, + MachineBasicBlock::iterator IP, + Value *Op, Value *ShiftAmount, bool isLeftShift, + const Type *ResultTy, unsigned DestReg); + /// copyConstantToRegister - Output the instructions required to put the /// specified constant into the specified register. /// void copyConstantToRegister(MachineBasicBlock *MBB, - MachineBasicBlock::iterator &MBBI, + MachineBasicBlock::iterator MBBI, Constant *C, unsigned Reg); /// makeAnotherReg - This method returns the next register number we haven't @@ -238,11 +277,11 @@ namespace { const X86RegisterInfo *MRI = static_cast(TM.getRegisterInfo()); if (Ty == Type::LongTy || Ty == Type::ULongTy) { - const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy); - // Create the lower part - F->getSSARegMap()->createVirtualRegister(RC); - // Create the upper part. - return F->getSSARegMap()->createVirtualRegister(RC)-1; + const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy); + // Create the lower part + F->getSSARegMap()->createVirtualRegister(RC); + // Create the upper part. + return F->getSSARegMap()->createVirtualRegister(RC)-1; } // Add the mapping of regnumber => reg class to MachineFunction @@ -261,7 +300,7 @@ namespace { return getReg(V, BB, It); } unsigned getReg(Value *V, MachineBasicBlock *MBB, - MachineBasicBlock::iterator &IPt) { + MachineBasicBlock::iterator IPt) { unsigned &Reg = RegMap[V]; if (Reg == 0) { Reg = makeAnotherReg(V->getType()); @@ -276,7 +315,7 @@ namespace { RegMap.erase(V); // Assign a new name to this constant if ref'd again } else if (GlobalValue *GV = dyn_cast(V)) { // Move the address of the global into the register - BMI(MBB, IPt, X86::MOVir32, 1, Reg).addGlobalAddress(GV); + BuildMI(*MBB, IPt, X86::MOV32ri, 1, Reg).addGlobalAddress(GV); RegMap.erase(V); // Assign a new name to this address if ref'd again } @@ -327,7 +366,7 @@ static inline TypeClass getClassB(const Type *Ty) { /// specified constant into the specified register. /// void ISel::copyConstantToRegister(MachineBasicBlock *MBB, - MachineBasicBlock::iterator &IP, + MachineBasicBlock::iterator IP, Constant *C, unsigned R) { if (ConstantExpr *CE = dyn_cast(C)) { unsigned Class = 0; @@ -349,6 +388,22 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB, Class, R); return; + case Instruction::Mul: { + unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP); + unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP); + doMultiply(MBB, IP, R, CE->getType(), Op0Reg, Op1Reg); + return; + } + case Instruction::Div: + case Instruction::Rem: { + unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP); + unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP); + emitDivRemOperation(MBB, IP, Op0Reg, Op1Reg, + CE->getOpcode() == Instruction::Div, + CE->getType(), R); + return; + } + case Instruction::SetNE: case Instruction::SetEQ: case Instruction::SetLT: @@ -359,9 +414,15 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB, CE->getOpcode(), R); return; + case Instruction::Shl: + case Instruction::Shr: + emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1), + CE->getOpcode() == Instruction::Shl, CE->getType(), R); + return; + default: std::cerr << "Offending expr: " << C << "\n"; - assert(0 && "Constant expressions not yet handled!\n"); + assert(0 && "Constant expression not yet handled!\n"); } } @@ -371,42 +432,44 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB, if (Class == cLong) { // Copy the value into the register pair. uint64_t Val = cast(C)->getRawValue(); - BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(Val & 0xFFFFFFFF); - BMI(MBB, IP, X86::MOVir32, 1, R+1).addZImm(Val >> 32); + BuildMI(*MBB, IP, X86::MOV32ri, 1, R).addImm(Val & 0xFFFFFFFF); + BuildMI(*MBB, IP, X86::MOV32ri, 1, R+1).addImm(Val >> 32); return; } assert(Class <= cInt && "Type not handled yet!"); static const unsigned IntegralOpcodeTab[] = { - X86::MOVir8, X86::MOVir16, X86::MOVir32 + X86::MOV8ri, X86::MOV16ri, X86::MOV32ri }; if (C->getType() == Type::BoolTy) { - BMI(MBB, IP, X86::MOVir8, 1, R).addZImm(C == ConstantBool::True); + BuildMI(*MBB, IP, X86::MOV8ri, 1, R).addImm(C == ConstantBool::True); } else { ConstantInt *CI = cast(C); - BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CI->getRawValue()); + BuildMI(*MBB, IP, IntegralOpcodeTab[Class],1,R).addImm(CI->getRawValue()); } } else if (ConstantFP *CFP = dyn_cast(C)) { - double Value = CFP->getValue(); - if (Value == +0.0) - BMI(MBB, IP, X86::FLD0, 0, R); - else if (Value == +1.0) - BMI(MBB, IP, X86::FLD1, 0, R); + if (CFP->isExactlyValue(+0.0)) + BuildMI(*MBB, IP, X86::FLD0, 0, R); + else if (CFP->isExactlyValue(+1.0)) + BuildMI(*MBB, IP, X86::FLD1, 0, R); else { // Otherwise we need to spill the constant to memory... MachineConstantPool *CP = F->getConstantPool(); unsigned CPI = CP->getConstantPoolIndex(CFP); - addConstantPoolReference(doFPLoad(MBB, IP, CFP->getType(), R), CPI); + const Type *Ty = CFP->getType(); + + assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!"); + unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLD32m : X86::FLD64m; + addConstantPoolReference(BuildMI(*MBB, IP, LoadOpcode, 4, R), CPI); } } else if (isa(C)) { // Copy zero (null pointer) to the register. - BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(0); + BuildMI(*MBB, IP, X86::MOV32ri, 1, R).addImm(0); } else if (ConstantPointerRef *CPR = dyn_cast(C)) { - unsigned SrcReg = getReg(CPR->getValue(), MBB, IP); - BMI(MBB, IP, X86::MOVrr32, 1, R).addReg(SrcReg); + BuildMI(*MBB, IP, X86::MOV32ri, 1, R).addGlobalAddress(CPR->getValue()); } else { std::cerr << "Offending constant: " << C << "\n"; assert(0 && "Type not handled yet!"); @@ -435,31 +498,31 @@ void ISel::LoadArgumentsToVirtualRegs(Function &Fn) { switch (getClassB(I->getType())) { case cByte: FI = MFI->CreateFixedObject(1, ArgOffset); - addFrameReference(BuildMI(BB, X86::MOVmr8, 4, Reg), FI); + addFrameReference(BuildMI(BB, X86::MOV8rm, 4, Reg), FI); break; case cShort: FI = MFI->CreateFixedObject(2, ArgOffset); - addFrameReference(BuildMI(BB, X86::MOVmr16, 4, Reg), FI); + addFrameReference(BuildMI(BB, X86::MOV16rm, 4, Reg), FI); break; case cInt: FI = MFI->CreateFixedObject(4, ArgOffset); - addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI); + addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Reg), FI); break; case cLong: FI = MFI->CreateFixedObject(8, ArgOffset); - addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI); - addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg+1), FI, 4); + addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Reg), FI); + addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Reg+1), FI, 4); ArgOffset += 4; // longs require 4 additional bytes break; case cFP: unsigned Opcode; if (I->getType() == Type::FloatTy) { - Opcode = X86::FLDr32; - FI = MFI->CreateFixedObject(4, ArgOffset); + Opcode = X86::FLD32m; + FI = MFI->CreateFixedObject(4, ArgOffset); } else { - Opcode = X86::FLDr64; - FI = MFI->CreateFixedObject(8, ArgOffset); - ArgOffset += 4; // doubles require 4 additional bytes + Opcode = X86::FLD64m; + FI = MFI->CreateFixedObject(8, ArgOffset); + ArgOffset += 4; // doubles require 4 additional bytes } addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI); break; @@ -486,23 +549,22 @@ void ISel::SelectPHINodes() { const Function &LF = *F->getFunction(); // The LLVM function... for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) { const BasicBlock *BB = I; - MachineBasicBlock *MBB = MBBMap[I]; + MachineBasicBlock &MBB = *MBBMap[I]; // Loop over all of the PHI nodes in the LLVM basic block... - unsigned NumPHIs = 0; + MachineBasicBlock::iterator PHIInsertPoint = MBB.begin(); for (BasicBlock::const_iterator I = BB->begin(); - PHINode *PN = (PHINode*)dyn_cast(I); ++I) { + PHINode *PN = const_cast(dyn_cast(I)); ++I) { // Create a new machine instr PHI node, and insert it. unsigned PHIReg = getReg(*PN); - MachineInstr *PhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg); - MBB->insert(MBB->begin()+NumPHIs++, PhiMI); + MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint, + X86::PHI, PN->getNumOperands(), PHIReg); MachineInstr *LongPhiMI = 0; - if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy) { - LongPhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg+1); - MBB->insert(MBB->begin()+NumPHIs++, LongPhiMI); - } + if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy) + LongPhiMI = BuildMI(MBB, PHIInsertPoint, + X86::PHI, PN->getNumOperands(), PHIReg+1); // PHIValues - Map of blocks to incoming virtual registers. We use this // so that we only initialize one incoming value for a particular block, @@ -522,31 +584,139 @@ void ISel::SelectPHINodes() { ValReg = EntryIt->second; } else { - // Get the incoming value into a virtual register. If it is not - // already available in a virtual register, insert the computation - // code into PredMBB + // Get the incoming value into a virtual register. // - MachineBasicBlock::iterator PI = PredMBB->end(); - while (PI != PredMBB->begin() && - TII.isTerminatorInstr((*(PI-1))->getOpcode())) - --PI; - ValReg = getReg(PN->getIncomingValue(i), PredMBB, PI); + Value *Val = PN->getIncomingValue(i); + + // If this is a constant or GlobalValue, we may have to insert code + // into the basic block to compute it into a virtual register. + if (isa(Val) || isa(Val)) { + // Because we don't want to clobber any values which might be in + // physical registers with the computation of this constant (which + // might be arbitrarily complex if it is a constant expression), + // just insert the computation at the top of the basic block. + MachineBasicBlock::iterator PI = PredMBB->begin(); + + // Skip over any PHI nodes though! + while (PI != PredMBB->end() && PI->getOpcode() == X86::PHI) + ++PI; + + ValReg = getReg(Val, PredMBB, PI); + } else { + ValReg = getReg(Val); + } // Remember that we inserted a value for this PHI for this predecessor PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg)); } - PhiMI->addRegOperand(ValReg); + PhiMI->addRegOperand(ValReg); PhiMI->addMachineBasicBlockOperand(PredMBB); - if (LongPhiMI) { - LongPhiMI->addRegOperand(ValReg+1); - LongPhiMI->addMachineBasicBlockOperand(PredMBB); - } + if (LongPhiMI) { + LongPhiMI->addRegOperand(ValReg+1); + LongPhiMI->addMachineBasicBlockOperand(PredMBB); + } + } + + // Now that we emitted all of the incoming values for the PHI node, make + // sure to reposition the InsertPoint after the PHI that we just added. + // This is needed because we might have inserted a constant into this + // block, right after the PHI's which is before the old insert point! + PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI; + ++PHIInsertPoint; + } + } +} + +/// RequiresFPRegKill - The floating point stackifier pass cannot insert +/// compensation code on critical edges. As such, it requires that we kill all +/// FP registers on the exit from any blocks that either ARE critical edges, or +/// branch to a block that has incoming critical edges. +/// +/// Note that this kill instruction will eventually be eliminated when +/// restrictions in the stackifier are relaxed. +/// +static bool RequiresFPRegKill(const BasicBlock *BB) { +#if 0 + for (succ_const_iterator SI = succ_begin(BB), E = succ_end(BB); SI!=E; ++SI) { + const BasicBlock *Succ = *SI; + pred_const_iterator PI = pred_begin(Succ), PE = pred_end(Succ); + ++PI; // Block have at least one predecessory + if (PI != PE) { // If it has exactly one, this isn't crit edge + // If this block has more than one predecessor, check all of the + // predecessors to see if they have multiple successors. If so, then the + // block we are analyzing needs an FPRegKill. + for (PI = pred_begin(Succ); PI != PE; ++PI) { + const BasicBlock *Pred = *PI; + succ_const_iterator SI2 = succ_begin(Pred); + ++SI2; // There must be at least one successor of this block. + if (SI2 != succ_end(Pred)) + return true; // Yes, we must insert the kill on this edge. + } + } + } + // If we got this far, there is no need to insert the kill instruction. + return false; +#else + return true; +#endif +} + +// InsertFPRegKills - Insert FP_REG_KILL instructions into basic blocks that +// need them. This only occurs due to the floating point stackifier not being +// aggressive enough to handle arbitrary global stackification. +// +// Currently we insert an FP_REG_KILL instruction into each block that uses or +// defines a floating point virtual register. +// +// When the global register allocators (like linear scan) finally update live +// variable analysis, we can keep floating point values in registers across +// portions of the CFG that do not involve critical edges. This will be a big +// win, but we are waiting on the global allocators before we can do this. +// +// With a bit of work, the floating point stackifier pass can be enhanced to +// break critical edges as needed (to make a place to put compensation code), +// but this will require some infrastructure improvements as well. +// +void ISel::InsertFPRegKills() { + SSARegMap &RegMap = *F->getSSARegMap(); + + for (MachineFunction::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) { + for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I!=E; ++I) + for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { + MachineOperand& MO = I->getOperand(i); + if (MO.isRegister() && MO.getReg()) { + unsigned Reg = MO.getReg(); + if (MRegisterInfo::isVirtualRegister(Reg)) + if (RegMap.getRegClass(Reg)->getSize() == 10) + goto UsesFPReg; + } + } + // If we haven't found an FP register use or def in this basic block, check + // to see if any of our successors has an FP PHI node, which will cause a + // copy to be inserted into this block. + for (succ_const_iterator SI = succ_begin(BB->getBasicBlock()), + E = succ_end(BB->getBasicBlock()); SI != E; ++SI) { + MachineBasicBlock *SBB = MBBMap[*SI]; + for (MachineBasicBlock::iterator I = SBB->begin(); + I != SBB->end() && I->getOpcode() == X86::PHI; ++I) { + if (RegMap.getRegClass(I->getOperand(0).getReg())->getSize() == 10) + goto UsesFPReg; } } + continue; + UsesFPReg: + // Okay, this block uses an FP register. If the block has successors (ie, + // it's not an unwind/return), insert the FP_REG_KILL instruction. + if (BB->getBasicBlock()->getTerminator()->getNumSuccessors() && + RequiresFPRegKill(BB->getBasicBlock())) { + BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0); + ++NumFPKill; + } } } + // canFoldSetCCIntoBranch - Return the setcc instruction if we can fold it into // the conditional branch instruction which is the only user of the cc // instruction. This is the case if the conditional branch is the only user of @@ -556,7 +726,7 @@ void ISel::SelectPHINodes() { // static SetCondInst *canFoldSetCCIntoBranch(Value *V) { if (SetCondInst *SCI = dyn_cast(V)) - if (SCI->use_size() == 1 && isa(SCI->use_back()) && + if (SCI->hasOneUse() && isa(SCI->use_back()) && SCI->getParent() == cast(SCI->use_back())->getParent()) { const Type *Ty = SCI->getOperand(0)->getType(); if (Ty != Type::LongTy && Ty != Type::ULongTy) @@ -588,17 +758,23 @@ static unsigned getSetCCNumber(unsigned Opcode) { // setge -> setge setae // setgt -> setg seta // setle -> setle setbe -static const unsigned SetCCOpcodeTab[2][6] = { - {X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr}, - {X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr}, +// ---- +// sets // Used by comparison with 0 optimization +// setns +static const unsigned SetCCOpcodeTab[2][8] = { + { X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr, + 0, 0 }, + { X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr, + X86::SETSr, X86::SETNSr }, }; -bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1, - MachineBasicBlock *MBB, - MachineBasicBlock::iterator &IP) { +// EmitComparison - This function emits a comparison of the two operands, +// returning the extended setcc code to use. +unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1, + MachineBasicBlock *MBB, + MachineBasicBlock::iterator IP) { // The arguments are already supposed to be of the same type. const Type *CompTy = Op0->getType(); - bool isSigned = CompTy->isSigned(); unsigned Class = getClassB(CompTy); unsigned Op0r = getReg(Op0, MBB, IP); @@ -610,14 +786,35 @@ bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1, // Mask off any upper bits of the constant, if there are any... Op1v &= (1ULL << (8 << Class)) - 1; - switch (Class) { - case cByte: BMI(MBB,IP, X86::CMPri8, 2).addReg(Op0r).addZImm(Op1v);break; - case cShort: BMI(MBB,IP, X86::CMPri16,2).addReg(Op0r).addZImm(Op1v);break; - case cInt: BMI(MBB,IP, X86::CMPri32,2).addReg(Op0r).addZImm(Op1v);break; - default: - assert(0 && "Invalid class!"); + // If this is a comparison against zero, emit more efficient code. We + // can't handle unsigned comparisons against zero unless they are == or + // !=. These should have been strength reduced already anyway. + if (Op1v == 0 && (CompTy->isSigned() || OpNum < 2)) { + static const unsigned TESTTab[] = { + X86::TEST8rr, X86::TEST16rr, X86::TEST32rr + }; + BuildMI(*MBB, IP, TESTTab[Class], 2).addReg(Op0r).addReg(Op0r); + + if (OpNum == 2) return 6; // Map jl -> js + if (OpNum == 3) return 7; // Map jg -> jns + return OpNum; } - return isSigned; + + static const unsigned CMPTab[] = { + X86::CMP8ri, X86::CMP16ri, X86::CMP32ri + }; + + BuildMI(*MBB, IP, CMPTab[Class], 2).addReg(Op0r).addImm(Op1v); + return OpNum; + } + + // Special case handling of comparison against +/- 0.0 + if (ConstantFP *CFP = dyn_cast(Op1)) + if (CFP->isExactlyValue(+0.0) || CFP->isExactlyValue(-0.0)) { + BuildMI(*MBB, IP, X86::FTST, 1).addReg(Op0r); + BuildMI(*MBB, IP, X86::FNSTSW8r, 0); + BuildMI(*MBB, IP, X86::SAHF, 1); + return OpNum; } unsigned Op1r = getReg(Op1, MBB, IP); @@ -627,19 +824,18 @@ bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1, // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with // 32-bit. case cByte: - BMI(MBB, IP, X86::CMPrr8, 2).addReg(Op0r).addReg(Op1r); + BuildMI(*MBB, IP, X86::CMP8rr, 2).addReg(Op0r).addReg(Op1r); break; case cShort: - BMI(MBB, IP, X86::CMPrr16, 2).addReg(Op0r).addReg(Op1r); + BuildMI(*MBB, IP, X86::CMP16rr, 2).addReg(Op0r).addReg(Op1r); break; case cInt: - BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r); + BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r).addReg(Op1r); break; case cFP: - BMI(MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r); - BMI(MBB, IP, X86::FNSTSWr8, 0); - BMI(MBB, IP, X86::SAHF, 1); - isSigned = false; // Compare with unsigned operators + BuildMI(*MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r); + BuildMI(*MBB, IP, X86::FNSTSW8r, 0); + BuildMI(*MBB, IP, X86::SAHF, 1); break; case cLong: @@ -647,9 +843,9 @@ bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1, unsigned LoTmp = makeAnotherReg(Type::IntTy); unsigned HiTmp = makeAnotherReg(Type::IntTy); unsigned FinalTmp = makeAnotherReg(Type::IntTy); - BMI(MBB, IP, X86::XORrr32, 2, LoTmp).addReg(Op0r).addReg(Op1r); - BMI(MBB, IP, X86::XORrr32, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1); - BMI(MBB, IP, X86::ORrr32, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp); + BuildMI(*MBB, IP, X86::XOR32rr, 2, LoTmp).addReg(Op0r).addReg(Op1r); + BuildMI(*MBB, IP, X86::XOR32rr, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1); + BuildMI(*MBB, IP, X86::OR32rr, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp); break; // Allow the sete or setne to be generated from flags set by OR } else { // Emit a sequence of code which compares the high and low parts once @@ -665,19 +861,20 @@ bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1, // classes! Until then, hardcode registers so that we can deal with their // aliases (because we don't have conditional byte moves). // - BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r); - BMI(MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL); - BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r+1).addReg(Op1r+1); - BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, X86::BL); - BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH); - BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH); - BMI(MBB, IP, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX); + BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r).addReg(Op1r); + BuildMI(*MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL); + BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r+1).addReg(Op1r+1); + BuildMI(*MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0, X86::BL); + BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH); + BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH); + BuildMI(*MBB, IP, X86::CMOVE16rr, 2, X86::BX).addReg(X86::BX) + .addReg(X86::AX); // NOTE: visitSetCondInst knows that the value is dumped into the BL // register at this point for long values... - return isSigned; + return OpNum; } } - return isSigned; + return OpNum; } @@ -695,20 +892,25 @@ void ISel::visitSetCondInst(SetCondInst &I) { /// emitSetCCOperation - Common code shared between visitSetCondInst and /// constant expression support. +/// void ISel::emitSetCCOperation(MachineBasicBlock *MBB, - MachineBasicBlock::iterator &IP, + MachineBasicBlock::iterator IP, Value *Op0, Value *Op1, unsigned Opcode, unsigned TargetReg) { unsigned OpNum = getSetCCNumber(Opcode); - bool isSigned = EmitComparisonGetSignedness(OpNum, Op0, Op1, MBB, IP); + OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP); + + const Type *CompTy = Op0->getType(); + unsigned CompClass = getClassB(CompTy); + bool isSigned = CompTy->isSigned() && CompClass != cFP; - if (getClassB(Op0->getType()) != cLong || OpNum < 2) { + if (CompClass != cLong || OpNum < 2) { // Handle normal comparisons with a setcc instruction... - BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg); + BuildMI(*MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg); } else { // Handle long comparisons by copying the value which is already in BL into // the register we want... - BMI(MBB, IP, X86::MOVrr8, 1, TargetReg).addReg(X86::BL); + BuildMI(*MBB, IP, X86::MOV8rr, 1, TargetReg).addReg(X86::BL); } } @@ -717,6 +919,7 @@ void ISel::emitSetCCOperation(MachineBasicBlock *MBB, /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide /// operand, in the specified target register. +/// void ISel::promote32(unsigned targetReg, const ValueRecord &VR) { bool isUnsigned = VR.Ty->isUnsigned(); @@ -727,20 +930,20 @@ void ISel::promote32(unsigned targetReg, const ValueRecord &VR) { case cByte: // Extend value into target register (8->32) if (isUnsigned) - BuildMI(BB, X86::MOVZXr32r8, 1, targetReg).addReg(Reg); + BuildMI(BB, X86::MOVZX32rr8, 1, targetReg).addReg(Reg); else - BuildMI(BB, X86::MOVSXr32r8, 1, targetReg).addReg(Reg); + BuildMI(BB, X86::MOVSX32rr8, 1, targetReg).addReg(Reg); break; case cShort: // Extend value into target register (16->32) if (isUnsigned) - BuildMI(BB, X86::MOVZXr32r16, 1, targetReg).addReg(Reg); + BuildMI(BB, X86::MOVZX32rr16, 1, targetReg).addReg(Reg); else - BuildMI(BB, X86::MOVSXr32r16, 1, targetReg).addReg(Reg); + BuildMI(BB, X86::MOVSX32rr16, 1, targetReg).addReg(Reg); break; case cInt: // Move value into target register (32->32) - BuildMI(BB, X86::MOVrr32, 1, targetReg).addReg(Reg); + BuildMI(BB, X86::MOV32rr, 1, targetReg).addReg(Reg); break; default: assert(0 && "Unpromotable operand class in promote32"); @@ -780,10 +983,11 @@ void ISel::visitReturnInst(ReturnInst &I) { BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP); break; case cLong: - BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(RetReg); - BuildMI(BB, X86::MOVrr32, 1, X86::EDX).addReg(RetReg+1); + BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(RetReg); + BuildMI(BB, X86::MOV32rr, 1, X86::EDX).addReg(RetReg+1); // Declare that EAX & EDX are live on exit - BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX).addReg(X86::ESP); + BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX) + .addReg(X86::ESP); break; default: visitInstruction(I); @@ -819,7 +1023,7 @@ void ISel::visitBranchInst(BranchInst &BI) { // Nope, cannot fold setcc into this branch. Emit a branch on a condition // computed some other way... unsigned condReg = getReg(BI.getCondition()); - BuildMI(BB, X86::CMPri8, 2).addReg(condReg).addZImm(0); + BuildMI(BB, X86::CMP8ri, 2).addReg(condReg).addImm(0); if (BI.getSuccessor(1) == NextBB) { if (BI.getSuccessor(0) != NextBB) BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0)); @@ -834,9 +1038,12 @@ void ISel::visitBranchInst(BranchInst &BI) { unsigned OpNum = getSetCCNumber(SCI->getOpcode()); MachineBasicBlock::iterator MII = BB->end(); - bool isSigned = EmitComparisonGetSignedness(OpNum, SCI->getOperand(0), - SCI->getOperand(1), BB, MII); + OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII); + + const Type *CompTy = SCI->getOperand(0)->getType(); + bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP; + // LLVM -> X86 signed X86 unsigned // ----- ---------- ------------ // seteq -> je je @@ -845,9 +1052,14 @@ void ISel::visitBranchInst(BranchInst &BI) { // setge -> jge jae // setgt -> jg ja // setle -> jle jbe - static const unsigned OpcodeTab[2][6] = { - { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE }, - { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE }, + // ---- + // js // Used by comparison with 0 optimization + // jns + + static const unsigned OpcodeTab[2][8] = { + { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE, 0, 0 }, + { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE, + X86::JS, X86::JNS }, }; if (BI.getSuccessor(0) != NextBB) { @@ -869,7 +1081,7 @@ void ISel::visitBranchInst(BranchInst &BI) { /// it inserts the specified CallMI instruction into the stream. /// void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI, - const std::vector &Args) { + const std::vector &Args) { // Count how many bytes are to be pushed on the stack... unsigned NumBytes = 0; @@ -878,67 +1090,83 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI, for (unsigned i = 0, e = Args.size(); i != e; ++i) switch (getClassB(Args[i].Ty)) { case cByte: case cShort: case cInt: - NumBytes += 4; break; + NumBytes += 4; break; case cLong: - NumBytes += 8; break; + NumBytes += 8; break; case cFP: - NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8; - break; + NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8; + break; default: assert(0 && "Unknown class!"); } // Adjust the stack pointer for the new arguments... - BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(NumBytes); + BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addImm(NumBytes); // Arguments go on the stack in reverse order, as specified by the ABI. unsigned ArgOffset = 0; for (unsigned i = 0, e = Args.size(); i != e; ++i) { - unsigned ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg; + unsigned ArgReg; switch (getClassB(Args[i].Ty)) { case cByte: - case cShort: { - // Promote arg to 32 bits wide into a temporary register... - unsigned R = makeAnotherReg(Type::UIntTy); - promote32(R, Args[i]); - addRegOffset(BuildMI(BB, X86::MOVrm32, 5), - X86::ESP, ArgOffset).addReg(R); - break; - } + case cShort: + if (Args[i].Val && isa(Args[i].Val)) { + // Zero/Sign extend constant, then stuff into memory. + ConstantInt *Val = cast(Args[i].Val); + Val = cast(ConstantExpr::getCast(Val, Type::IntTy)); + addRegOffset(BuildMI(BB, X86::MOV32mi, 5), X86::ESP, ArgOffset) + .addImm(Val->getRawValue() & 0xFFFFFFFF); + } else { + // Promote arg to 32 bits wide into a temporary register... + ArgReg = makeAnotherReg(Type::UIntTy); + promote32(ArgReg, Args[i]); + addRegOffset(BuildMI(BB, X86::MOV32mr, 5), + X86::ESP, ArgOffset).addReg(ArgReg); + } + break; case cInt: - addRegOffset(BuildMI(BB, X86::MOVrm32, 5), - X86::ESP, ArgOffset).addReg(ArgReg); - break; + if (Args[i].Val && isa(Args[i].Val)) { + unsigned Val = cast(Args[i].Val)->getRawValue(); + addRegOffset(BuildMI(BB, X86::MOV32mi, 5), + X86::ESP, ArgOffset).addImm(Val); + } else { + ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg; + addRegOffset(BuildMI(BB, X86::MOV32mr, 5), + X86::ESP, ArgOffset).addReg(ArgReg); + } + break; case cLong: - addRegOffset(BuildMI(BB, X86::MOVrm32, 5), - X86::ESP, ArgOffset).addReg(ArgReg); - addRegOffset(BuildMI(BB, X86::MOVrm32, 5), - X86::ESP, ArgOffset+4).addReg(ArgReg+1); - ArgOffset += 4; // 8 byte entry, not 4. - break; - + ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg; + addRegOffset(BuildMI(BB, X86::MOV32mr, 5), + X86::ESP, ArgOffset).addReg(ArgReg); + addRegOffset(BuildMI(BB, X86::MOV32mr, 5), + X86::ESP, ArgOffset+4).addReg(ArgReg+1); + ArgOffset += 4; // 8 byte entry, not 4. + break; + case cFP: - if (Args[i].Ty == Type::FloatTy) { - addRegOffset(BuildMI(BB, X86::FSTr32, 5), - X86::ESP, ArgOffset).addReg(ArgReg); - } else { - assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!"); - addRegOffset(BuildMI(BB, X86::FSTr64, 5), - X86::ESP, ArgOffset).addReg(ArgReg); - ArgOffset += 4; // 8 byte entry, not 4. - } - break; + ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg; + if (Args[i].Ty == Type::FloatTy) { + addRegOffset(BuildMI(BB, X86::FST32m, 5), + X86::ESP, ArgOffset).addReg(ArgReg); + } else { + assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!"); + addRegOffset(BuildMI(BB, X86::FST64m, 5), + X86::ESP, ArgOffset).addReg(ArgReg); + ArgOffset += 4; // 8 byte entry, not 4. + } + break; default: assert(0 && "Unknown class!"); } ArgOffset += 4; } } else { - BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(0); + BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addImm(0); } BB->push_back(CallMI); - BuildMI(BB, X86::ADJCALLSTACKUP, 1).addZImm(NumBytes); + BuildMI(BB, X86::ADJCALLSTACKUP, 1).addImm(NumBytes); // If there is a return value, scavenge the result from the location the call // leaves it in... @@ -952,7 +1180,7 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI, // Integral results are in %eax, or the appropriate portion // thereof. static const unsigned regRegMove[] = { - X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 + X86::MOV8rr, X86::MOV16rr, X86::MOV32rr }; static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX }; BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]); @@ -962,8 +1190,8 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI, BuildMI(BB, X86::FpGETRESULT, 1, Ret.Reg); break; case cLong: // Long values are left in EDX:EAX - BuildMI(BB, X86::MOVrr32, 1, Ret.Reg).addReg(X86::EAX); - BuildMI(BB, X86::MOVrr32, 1, Ret.Reg+1).addReg(X86::EDX); + BuildMI(BB, X86::MOV32rr, 1, Ret.Reg).addReg(X86::EAX); + BuildMI(BB, X86::MOV32rr, 1, Ret.Reg+1).addReg(X86::EDX); break; default: assert(0 && "Unknown class!"); } @@ -976,7 +1204,7 @@ void ISel::visitCallInst(CallInst &CI) { MachineInstr *TheCall; if (Function *F = CI.getCalledFunction()) { // Is it an intrinsic function call? - if (LLVMIntrinsic::ID ID = (LLVMIntrinsic::ID)F->getIntrinsicID()) { + if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) { visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here return; } @@ -985,7 +1213,7 @@ void ISel::visitCallInst(CallInst &CI) { TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true); } else { // Emit an indirect call... unsigned Reg = getReg(CI.getCalledValue()); - TheCall = BuildMI(X86::CALLr32, 1).addReg(Reg); + TheCall = BuildMI(X86::CALL32r, 1).addReg(Reg); } std::vector Args; @@ -994,68 +1222,189 @@ void ISel::visitCallInst(CallInst &CI) { unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0; doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args); -} +} -// visitInvokeInst - For now, we don't support the llvm.unwind intrinsic, so -// invoke's are just calls with an unconditional branch after them! -void ISel::visitInvokeInst(InvokeInst &II) { - MachineInstr *TheCall; - if (Function *F = II.getCalledFunction()) { - // Emit a CALL instruction with PC-relative displacement. - TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true); - } else { // Emit an indirect call... - unsigned Reg = getReg(II.getCalledValue()); - TheCall = BuildMI(X86::CALLr32, 1).addReg(Reg); - } - - std::vector Args; - for (unsigned i = 3, e = II.getNumOperands(); i != e; ++i) - Args.push_back(ValueRecord(II.getOperand(i))); - - unsigned DestReg = II.getType() != Type::VoidTy ? getReg(II) : 0; - doCall(ValueRecord(DestReg, II.getType()), TheCall, Args); - - // If the normal destination is not the next basic block, emit a 'jmp'. - if (II.getNormalDest() != getBlockAfter(II.getParent())) - BuildMI(BB, X86::JMP, 1).addPCDisp(II.getNormalDest()); -} +/// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the +/// function, lowering any calls to unknown intrinsic functions into the +/// equivalent LLVM code. +/// +void ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) { + for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB) + for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ) + if (CallInst *CI = dyn_cast(I++)) + if (Function *F = CI->getCalledFunction()) + switch (F->getIntrinsicID()) { + case Intrinsic::not_intrinsic: + case Intrinsic::va_start: + case Intrinsic::va_copy: + case Intrinsic::va_end: + case Intrinsic::returnaddress: + case Intrinsic::frameaddress: + case Intrinsic::memcpy: + case Intrinsic::memset: + // We directly implement these intrinsics + break; + default: + // All other intrinsic calls we must lower. + Instruction *Before = CI->getPrev(); + TM.getIntrinsicLowering().LowerIntrinsicCall(CI); + if (Before) { // Move iterator to instruction after call + I = Before; ++I; + } else { + I = BB->begin(); + } + } -void ISel::visitUnwindInst(UnwindInst &UI) { - // unwind is not supported yet! Just abort when the unwind inst is executed! - BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("abort", true); } -void ISel::visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &CI) { +void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) { unsigned TmpReg1, TmpReg2; switch (ID) { - case LLVMIntrinsic::va_start: + case Intrinsic::va_start: // Get the address of the first vararg value... - TmpReg1 = makeAnotherReg(Type::UIntTy); - addFrameReference(BuildMI(BB, X86::LEAr32, 5, TmpReg1), VarArgsFrameIndex); - TmpReg2 = getReg(CI.getOperand(1)); - addDirectMem(BuildMI(BB, X86::MOVrm32, 5), TmpReg2).addReg(TmpReg1); + TmpReg1 = getReg(CI); + addFrameReference(BuildMI(BB, X86::LEA32r, 5, TmpReg1), VarArgsFrameIndex); return; - case LLVMIntrinsic::va_end: return; // Noop on X86 - case LLVMIntrinsic::va_copy: - TmpReg1 = getReg(CI.getOperand(2)); // Get existing va_list - TmpReg2 = getReg(CI.getOperand(1)); // Get va_list* to store into - addDirectMem(BuildMI(BB, X86::MOVrm32, 5), TmpReg2).addReg(TmpReg1); + case Intrinsic::va_copy: + TmpReg1 = getReg(CI); + TmpReg2 = getReg(CI.getOperand(1)); + BuildMI(BB, X86::MOV32rr, 1, TmpReg1).addReg(TmpReg2); + return; + case Intrinsic::va_end: return; // Noop on X86 + + case Intrinsic::returnaddress: + case Intrinsic::frameaddress: + TmpReg1 = getReg(CI); + if (cast(CI.getOperand(1))->isNullValue()) { + if (ID == Intrinsic::returnaddress) { + // Just load the return address + addFrameReference(BuildMI(BB, X86::MOV32rm, 4, TmpReg1), + ReturnAddressIndex); + } else { + addFrameReference(BuildMI(BB, X86::LEA32r, 4, TmpReg1), + ReturnAddressIndex, -4); + } + } else { + // Values other than zero are not implemented yet. + BuildMI(BB, X86::MOV32ri, 1, TmpReg1).addImm(0); + } return; - case LLVMIntrinsic::unwind: // llvm.unwind is not supported yet! - case LLVMIntrinsic::longjmp: - case LLVMIntrinsic::siglongjmp: - BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("abort", true); + case Intrinsic::memcpy: { + assert(CI.getNumOperands() == 5 && "Illegal llvm.memcpy call!"); + unsigned Align = 1; + if (ConstantInt *AlignC = dyn_cast(CI.getOperand(4))) { + Align = AlignC->getRawValue(); + if (Align == 0) Align = 1; + } + + // Turn the byte code into # iterations + unsigned CountReg; + unsigned Opcode; + switch (Align & 3) { + case 2: // WORD aligned + if (ConstantInt *I = dyn_cast(CI.getOperand(3))) { + CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2)); + } else { + CountReg = makeAnotherReg(Type::IntTy); + unsigned ByteReg = getReg(CI.getOperand(3)); + BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(1); + } + Opcode = X86::REP_MOVSW; + break; + case 0: // DWORD aligned + if (ConstantInt *I = dyn_cast(CI.getOperand(3))) { + CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4)); + } else { + CountReg = makeAnotherReg(Type::IntTy); + unsigned ByteReg = getReg(CI.getOperand(3)); + BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(2); + } + Opcode = X86::REP_MOVSD; + break; + default: // BYTE aligned + CountReg = getReg(CI.getOperand(3)); + Opcode = X86::REP_MOVSB; + break; + } + + // No matter what the alignment is, we put the source in ESI, the + // destination in EDI, and the count in ECX. + TmpReg1 = getReg(CI.getOperand(1)); + TmpReg2 = getReg(CI.getOperand(2)); + BuildMI(BB, X86::MOV32rr, 1, X86::ECX).addReg(CountReg); + BuildMI(BB, X86::MOV32rr, 1, X86::EDI).addReg(TmpReg1); + BuildMI(BB, X86::MOV32rr, 1, X86::ESI).addReg(TmpReg2); + BuildMI(BB, Opcode, 0); return; + } + case Intrinsic::memset: { + assert(CI.getNumOperands() == 5 && "Illegal llvm.memset call!"); + unsigned Align = 1; + if (ConstantInt *AlignC = dyn_cast(CI.getOperand(4))) { + Align = AlignC->getRawValue(); + if (Align == 0) Align = 1; + } - case LLVMIntrinsic::setjmp: - case LLVMIntrinsic::sigsetjmp: - // Setjmp always returns zero... - BuildMI(BB, X86::MOVir32, 1, getReg(CI)).addZImm(0); + // Turn the byte code into # iterations + unsigned CountReg; + unsigned Opcode; + if (ConstantInt *ValC = dyn_cast(CI.getOperand(2))) { + unsigned Val = ValC->getRawValue() & 255; + + // If the value is a constant, then we can potentially use larger copies. + switch (Align & 3) { + case 2: // WORD aligned + if (ConstantInt *I = dyn_cast(CI.getOperand(3))) { + CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2)); + } else { + CountReg = makeAnotherReg(Type::IntTy); + unsigned ByteReg = getReg(CI.getOperand(3)); + BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(1); + } + BuildMI(BB, X86::MOV16ri, 1, X86::AX).addImm((Val << 8) | Val); + Opcode = X86::REP_STOSW; + break; + case 0: // DWORD aligned + if (ConstantInt *I = dyn_cast(CI.getOperand(3))) { + CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4)); + } else { + CountReg = makeAnotherReg(Type::IntTy); + unsigned ByteReg = getReg(CI.getOperand(3)); + BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(2); + } + Val = (Val << 8) | Val; + BuildMI(BB, X86::MOV32ri, 1, X86::EAX).addImm((Val << 16) | Val); + Opcode = X86::REP_STOSD; + break; + default: // BYTE aligned + CountReg = getReg(CI.getOperand(3)); + BuildMI(BB, X86::MOV8ri, 1, X86::AL).addImm(Val); + Opcode = X86::REP_STOSB; + break; + } + } else { + // If it's not a constant value we are storing, just fall back. We could + // try to be clever to form 16 bit and 32 bit values, but we don't yet. + unsigned ValReg = getReg(CI.getOperand(2)); + BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(ValReg); + CountReg = getReg(CI.getOperand(3)); + Opcode = X86::REP_STOSB; + } + + // No matter what the alignment is, we put the source in ESI, the + // destination in EDI, and the count in ECX. + TmpReg1 = getReg(CI.getOperand(1)); + //TmpReg2 = getReg(CI.getOperand(2)); + BuildMI(BB, X86::MOV32rr, 1, X86::ECX).addReg(CountReg); + BuildMI(BB, X86::MOV32rr, 1, X86::EDI).addReg(TmpReg1); + BuildMI(BB, Opcode, 0); return; - default: assert(0 && "Unknown intrinsic for X86!"); + } + + default: assert(0 && "Error: unknown intrinsics should have been lowered!"); } } @@ -1063,6 +1412,7 @@ void ISel::visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &CI) { /// visitSimpleBinary - Implement simple binary operators for integral types... /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for /// Xor. +/// void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) { unsigned DestReg = getReg(B); MachineBasicBlock::iterator MI = BB->end(); @@ -1070,27 +1420,55 @@ void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) { OperatorClass, DestReg); } -/// visitSimpleBinary - Implement simple binary operators for integral types... -/// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, -/// 4 for Xor. +/// emitSimpleBinaryOperation - Implement simple binary operators for integral +/// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for +/// Or, 4 for Xor. /// /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary /// and constant expression support. -void ISel::emitSimpleBinaryOperation(MachineBasicBlock *BB, - MachineBasicBlock::iterator &IP, +/// +void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB, + MachineBasicBlock::iterator IP, Value *Op0, Value *Op1, - unsigned OperatorClass,unsigned TargetReg){ + unsigned OperatorClass, unsigned DestReg) { unsigned Class = getClassB(Op0->getType()); + + // sub 0, X -> neg X + if (OperatorClass == 1 && Class != cLong) + if (ConstantInt *CI = dyn_cast(Op0)) { + if (CI->isNullValue()) { + unsigned op1Reg = getReg(Op1, MBB, IP); + switch (Class) { + default: assert(0 && "Unknown class for this function!"); + case cByte: + BuildMI(*MBB, IP, X86::NEG8r, 1, DestReg).addReg(op1Reg); + return; + case cShort: + BuildMI(*MBB, IP, X86::NEG16r, 1, DestReg).addReg(op1Reg); + return; + case cInt: + BuildMI(*MBB, IP, X86::NEG32r, 1, DestReg).addReg(op1Reg); + return; + } + } + } else if (ConstantFP *CFP = dyn_cast(Op0)) + if (CFP->isExactlyValue(-0.0)) { + // -0.0 - X === -X + unsigned op1Reg = getReg(Op1, MBB, IP); + BuildMI(*MBB, IP, X86::FCHS, 1, DestReg).addReg(op1Reg); + return; + } + if (!isa(Op1) || Class == cLong) { static const unsigned OpcodeTab[][4] = { // Arithmetic operators - { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD }, // ADD - { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB }, // SUB + { X86::ADD8rr, X86::ADD16rr, X86::ADD32rr, X86::FpADD }, // ADD + { X86::SUB8rr, X86::SUB16rr, X86::SUB32rr, X86::FpSUB }, // SUB // Bitwise operators - { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND - { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR - { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR + { X86::AND8rr, X86::AND16rr, X86::AND32rr, 0 }, // AND + { X86:: OR8rr, X86:: OR16rr, X86:: OR32rr, 0 }, // OR + { X86::XOR8rr, X86::XOR16rr, X86::XOR32rr, 0 }, // XOR }; bool isLong = false; @@ -1101,107 +1479,193 @@ void ISel::emitSimpleBinaryOperation(MachineBasicBlock *BB, unsigned Opcode = OpcodeTab[OperatorClass][Class]; assert(Opcode && "Floating point arguments to logical inst?"); - unsigned Op0r = getReg(Op0, BB, IP); - unsigned Op1r = getReg(Op1, BB, IP); - BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addReg(Op1r); + unsigned Op0r = getReg(Op0, MBB, IP); + unsigned Op1r = getReg(Op1, MBB, IP); + BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r); if (isLong) { // Handle the upper 32 bits of long values... static const unsigned TopTab[] = { - X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32 + X86::ADC32rr, X86::SBB32rr, X86::AND32rr, X86::OR32rr, X86::XOR32rr }; - BMI(BB, IP, TopTab[OperatorClass], 2, - TargetReg+1).addReg(Op0r+1).addReg(Op1r+1); + BuildMI(*MBB, IP, TopTab[OperatorClass], 2, + DestReg+1).addReg(Op0r+1).addReg(Op1r+1); } - } else { - // Special case: op Reg, - ConstantInt *Op1C = cast(Op1); + return; + } - static const unsigned OpcodeTab[][3] = { - // Arithmetic operators - { X86::ADDri8, X86::ADDri16, X86::ADDri32 }, // ADD - { X86::SUBri8, X86::SUBri16, X86::SUBri32 }, // SUB - - // Bitwise operators - { X86::ANDri8, X86::ANDri16, X86::ANDri32 }, // AND - { X86:: ORri8, X86:: ORri16, X86:: ORri32 }, // OR - { X86::XORri8, X86::XORri16, X86::XORri32 }, // XOR - }; + // Special case: op Reg, + ConstantInt *Op1C = cast(Op1); + unsigned Op0r = getReg(Op0, MBB, IP); - assert(Class < 3 && "General code handles 64-bit integer types!"); - unsigned Opcode = OpcodeTab[OperatorClass][Class]; - unsigned Op0r = getReg(Op0, BB, IP); - uint64_t Op1v = cast(Op1C)->getRawValue(); + // xor X, -1 -> not X + if (OperatorClass == 4 && Op1C->isAllOnesValue()) { + static unsigned const NOTTab[] = { X86::NOT8r, X86::NOT16r, X86::NOT32r }; + BuildMI(*MBB, IP, NOTTab[Class], 1, DestReg).addReg(Op0r); + return; + } - // Mask off any upper bits of the constant, if there are any... - Op1v &= (1ULL << (8 << Class)) - 1; - BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addZImm(Op1v); + // add X, -1 -> dec X + if (OperatorClass == 0 && Op1C->isAllOnesValue()) { + static unsigned const DECTab[] = { X86::DEC8r, X86::DEC16r, X86::DEC32r }; + BuildMI(*MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r); + return; } + + // add X, 1 -> inc X + if (OperatorClass == 0 && Op1C->equalsInt(1)) { + static unsigned const DECTab[] = { X86::INC8r, X86::INC16r, X86::INC32r }; + BuildMI(*MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r); + return; + } + + static const unsigned OpcodeTab[][3] = { + // Arithmetic operators + { X86::ADD8ri, X86::ADD16ri, X86::ADD32ri }, // ADD + { X86::SUB8ri, X86::SUB16ri, X86::SUB32ri }, // SUB + + // Bitwise operators + { X86::AND8ri, X86::AND16ri, X86::AND32ri }, // AND + { X86:: OR8ri, X86:: OR16ri, X86:: OR32ri }, // OR + { X86::XOR8ri, X86::XOR16ri, X86::XOR32ri }, // XOR + }; + + assert(Class < 3 && "General code handles 64-bit integer types!"); + unsigned Opcode = OpcodeTab[OperatorClass][Class]; + uint64_t Op1v = cast(Op1C)->getRawValue(); + + // Mask off any upper bits of the constant, if there are any... + Op1v &= (1ULL << (8 << Class)) - 1; + BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1v); } /// doMultiply - Emit appropriate instructions to multiply together the /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the /// result should be given as DestTy. /// -void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI, +void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, const Type *DestTy, unsigned op0Reg, unsigned op1Reg) { unsigned Class = getClass(DestTy); switch (Class) { case cFP: // Floating point multiply - BMI(BB, MBBI, X86::FpMUL, 2, DestReg).addReg(op0Reg).addReg(op1Reg); + BuildMI(*MBB, MBBI, X86::FpMUL, 2, DestReg).addReg(op0Reg).addReg(op1Reg); return; case cInt: case cShort: - BMI(BB, MBBI, Class == cInt ? X86::IMULr32 : X86::IMULr16, 2, DestReg) + BuildMI(*MBB, MBBI, Class == cInt ? X86::IMUL32rr:X86::IMUL16rr, 2, DestReg) .addReg(op0Reg).addReg(op1Reg); return; case cByte: // Must use the MUL instruction, which forces use of AL... - BMI(MBB, MBBI, X86::MOVrr8, 1, X86::AL).addReg(op0Reg); - BMI(MBB, MBBI, X86::MULr8, 1).addReg(op1Reg); - BMI(MBB, MBBI, X86::MOVrr8, 1, DestReg).addReg(X86::AL); + BuildMI(*MBB, MBBI, X86::MOV8rr, 1, X86::AL).addReg(op0Reg); + BuildMI(*MBB, MBBI, X86::MUL8r, 1).addReg(op1Reg); + BuildMI(*MBB, MBBI, X86::MOV8rr, 1, DestReg).addReg(X86::AL); return; default: case cLong: assert(0 && "doMultiply cannot operate on LONG values!"); } } +// ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It +// returns zero when the input is not exactly a power of two. +static unsigned ExactLog2(unsigned Val) { + if (Val == 0) return 0; + unsigned Count = 0; + while (Val != 1) { + if (Val & 1) return 0; + Val >>= 1; + ++Count; + } + return Count+1; +} + +void ISel::doMultiplyConst(MachineBasicBlock *MBB, + MachineBasicBlock::iterator IP, + unsigned DestReg, const Type *DestTy, + unsigned op0Reg, unsigned ConstRHS) { + unsigned Class = getClass(DestTy); + + // If the element size is exactly a power of 2, use a shift to get it. + if (unsigned Shift = ExactLog2(ConstRHS)) { + switch (Class) { + default: assert(0 && "Unknown class for this function!"); + case cByte: + BuildMI(*MBB, IP, X86::SHL32ri,2, DestReg).addReg(op0Reg).addImm(Shift-1); + return; + case cShort: + BuildMI(*MBB, IP, X86::SHL32ri,2, DestReg).addReg(op0Reg).addImm(Shift-1); + return; + case cInt: + BuildMI(*MBB, IP, X86::SHL32ri,2, DestReg).addReg(op0Reg).addImm(Shift-1); + return; + } + } + + if (Class == cShort) { + BuildMI(*MBB, IP, X86::IMUL16rri,2,DestReg).addReg(op0Reg).addImm(ConstRHS); + return; + } else if (Class == cInt) { + BuildMI(*MBB, IP, X86::IMUL32rri,2,DestReg).addReg(op0Reg).addImm(ConstRHS); + return; + } + + // Most general case, emit a normal multiply... + static const unsigned MOVriTab[] = { + X86::MOV8ri, X86::MOV16ri, X86::MOV32ri + }; + + unsigned TmpReg = makeAnotherReg(DestTy); + BuildMI(*MBB, IP, MOVriTab[Class], 1, TmpReg).addImm(ConstRHS); + + // Emit a MUL to multiply the register holding the index by + // elementSize, putting the result in OffsetReg. + doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg); +} + /// visitMul - Multiplies are not simple binary operators because they must deal /// with the EAX register explicitly. /// void ISel::visitMul(BinaryOperator &I) { unsigned Op0Reg = getReg(I.getOperand(0)); - unsigned Op1Reg = getReg(I.getOperand(1)); unsigned DestReg = getReg(I); // Simple scalar multiply? if (I.getType() != Type::LongTy && I.getType() != Type::ULongTy) { - MachineBasicBlock::iterator MBBI = BB->end(); - doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg); + if (ConstantInt *CI = dyn_cast(I.getOperand(1))) { + unsigned Val = (unsigned)CI->getRawValue(); // Cannot be 64-bit constant + MachineBasicBlock::iterator MBBI = BB->end(); + doMultiplyConst(BB, MBBI, DestReg, I.getType(), Op0Reg, Val); + } else { + unsigned Op1Reg = getReg(I.getOperand(1)); + MachineBasicBlock::iterator MBBI = BB->end(); + doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg); + } } else { + unsigned Op1Reg = getReg(I.getOperand(1)); + // Long value. We have to do things the hard way... // Multiply the two low parts... capturing carry into EDX - BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(Op0Reg); - BuildMI(BB, X86::MULr32, 1).addReg(Op1Reg); // AL*BL + BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(Op0Reg); + BuildMI(BB, X86::MUL32r, 1).addReg(Op1Reg); // AL*BL unsigned OverflowReg = makeAnotherReg(Type::UIntTy); - BuildMI(BB, X86::MOVrr32, 1, DestReg).addReg(X86::EAX); // AL*BL - BuildMI(BB, X86::MOVrr32, 1, OverflowReg).addReg(X86::EDX); // AL*BL >> 32 + BuildMI(BB, X86::MOV32rr, 1, DestReg).addReg(X86::EAX); // AL*BL + BuildMI(BB, X86::MOV32rr, 1, OverflowReg).addReg(X86::EDX); // AL*BL >> 32 MachineBasicBlock::iterator MBBI = BB->end(); unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL - BMI(BB, MBBI, X86::IMULr32, 2, AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg); + BuildMI(*BB, MBBI, X86::IMUL32rr,2,AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg); unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy); - BuildMI(BB, X86::ADDrr32, 2, // AH*BL+(AL*BL >> 32) - AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg); + BuildMI(*BB, MBBI, X86::ADD32rr, 2, // AH*BL+(AL*BL >> 32) + AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg); MBBI = BB->end(); unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH - BMI(BB, MBBI, X86::IMULr32, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1); + BuildMI(*BB, MBBI, X86::IMUL32rr,2,ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1); - BuildMI(BB, X86::ADDrr32, 2, // AL*BH + AH*BL + (AL*BL >> 32) - DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg); + BuildMI(*BB, MBBI, X86::ADD32rr, 2, // AL*BH + AH*BL + (AL*BL >> 32) + DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg); } } @@ -1212,21 +1676,30 @@ void ISel::visitMul(BinaryOperator &I) { /// instructions work differently for signed and unsigned operands. /// void ISel::visitDivRem(BinaryOperator &I) { - unsigned Class = getClass(I.getType()); - unsigned Op0Reg, Op1Reg, ResultReg = getReg(I); + unsigned Op0Reg = getReg(I.getOperand(0)); + unsigned Op1Reg = getReg(I.getOperand(1)); + unsigned ResultReg = getReg(I); + MachineBasicBlock::iterator IP = BB->end(); + emitDivRemOperation(BB, IP, Op0Reg, Op1Reg, I.getOpcode() == Instruction::Div, + I.getType(), ResultReg); +} + +void ISel::emitDivRemOperation(MachineBasicBlock *BB, + MachineBasicBlock::iterator IP, + unsigned Op0Reg, unsigned Op1Reg, bool isDiv, + const Type *Ty, unsigned ResultReg) { + unsigned Class = getClass(Ty); switch (Class) { case cFP: // Floating point divide - if (I.getOpcode() == Instruction::Div) { - Op0Reg = getReg(I.getOperand(0)); - Op1Reg = getReg(I.getOperand(1)); - BuildMI(BB, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg); + if (isDiv) { + BuildMI(*BB, IP, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg); } else { // Floating point remainder... MachineInstr *TheCall = - BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true); + BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true); std::vector Args; - Args.push_back(ValueRecord(I.getOperand(0))); - Args.push_back(ValueRecord(I.getOperand(1))); + Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy)); + Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy)); doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args); } return; @@ -1234,60 +1707,57 @@ void ISel::visitDivRem(BinaryOperator &I) { static const char *FnName[] = { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" }; - unsigned NameIdx = I.getType()->isUnsigned()*2; - NameIdx += I.getOpcode() == Instruction::Div; + unsigned NameIdx = Ty->isUnsigned()*2 + isDiv; MachineInstr *TheCall = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true); std::vector Args; - Args.push_back(ValueRecord(I.getOperand(0))); - Args.push_back(ValueRecord(I.getOperand(1))); + Args.push_back(ValueRecord(Op0Reg, Type::LongTy)); + Args.push_back(ValueRecord(Op1Reg, Type::LongTy)); doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args); return; } case cByte: case cShort: case cInt: - break; // Small integerals, handled below... + break; // Small integrals, handled below... default: assert(0 && "Unknown class!"); } static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX }; - static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 }; - static const unsigned SarOpcode[]={ X86::SARir8, X86::SARir16, X86::SARir32 }; - static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 }; + static const unsigned MovOpcode[]={ X86::MOV8rr, X86::MOV16rr, X86::MOV32rr }; + static const unsigned SarOpcode[]={ X86::SAR8ri, X86::SAR16ri, X86::SAR32ri }; + static const unsigned ClrOpcode[]={ X86::MOV8ri, X86::MOV16ri, X86::MOV32ri }; static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX }; static const unsigned DivOpcode[][4] = { - { X86::DIVr8 , X86::DIVr16 , X86::DIVr32 , 0 }, // Unsigned division - { X86::IDIVr8, X86::IDIVr16, X86::IDIVr32, 0 }, // Signed division + { X86::DIV8r , X86::DIV16r , X86::DIV32r , 0 }, // Unsigned division + { X86::IDIV8r, X86::IDIV16r, X86::IDIV32r, 0 }, // Signed division }; - bool isSigned = I.getType()->isSigned(); + bool isSigned = Ty->isSigned(); unsigned Reg = Regs[Class]; unsigned ExtReg = ExtRegs[Class]; // Put the first operand into one of the A registers... - Op0Reg = getReg(I.getOperand(0)); - BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg); + BuildMI(*BB, IP, MovOpcode[Class], 1, Reg).addReg(Op0Reg); if (isSigned) { // Emit a sign extension instruction... - unsigned ShiftResult = makeAnotherReg(I.getType()); - BuildMI(BB, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31); - BuildMI(BB, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult); + unsigned ShiftResult = makeAnotherReg(Ty); + BuildMI(*BB, IP, SarOpcode[Class], 2,ShiftResult).addReg(Op0Reg).addImm(31); + BuildMI(*BB, IP, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult); } else { - // If unsigned, emit a zeroing instruction... (reg = xor reg, reg) - BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg); + // If unsigned, emit a zeroing instruction... (reg = 0) + BuildMI(*BB, IP, ClrOpcode[Class], 2, ExtReg).addImm(0); } // Emit the appropriate divide or remainder instruction... - Op1Reg = getReg(I.getOperand(1)); - BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg); + BuildMI(*BB, IP, DivOpcode[isSigned][Class], 1).addReg(Op1Reg); // Figure out which register we want to pick the result out of... - unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg; + unsigned DestReg = isDiv ? Reg : ExtReg; // Put the result into the destination register... - BuildMI(BB, MovOpcode[Class], 1, ResultReg).addReg(DestReg); + BuildMI(*BB, IP, MovOpcode[Class], 1, ResultReg).addReg(DestReg); } @@ -1297,24 +1767,34 @@ void ISel::visitDivRem(BinaryOperator &I) { /// because the shift amount has to be in CL, not just any old register. /// void ISel::visitShiftInst(ShiftInst &I) { - unsigned SrcReg = getReg(I.getOperand(0)); - unsigned DestReg = getReg(I); - bool isLeftShift = I.getOpcode() == Instruction::Shl; - bool isSigned = I.getType()->isSigned(); - unsigned Class = getClass(I.getType()); + MachineBasicBlock::iterator IP = BB->end (); + emitShiftOperation (BB, IP, I.getOperand (0), I.getOperand (1), + I.getOpcode () == Instruction::Shl, I.getType (), + getReg (I)); +} + +/// emitShiftOperation - Common code shared between visitShiftInst and +/// constant expression support. +void ISel::emitShiftOperation(MachineBasicBlock *MBB, + MachineBasicBlock::iterator IP, + Value *Op, Value *ShiftAmount, bool isLeftShift, + const Type *ResultTy, unsigned DestReg) { + unsigned SrcReg = getReg (Op, MBB, IP); + bool isSigned = ResultTy->isSigned (); + unsigned Class = getClass (ResultTy); static const unsigned ConstantOperand[][4] = { - { X86::SHRir8, X86::SHRir16, X86::SHRir32, X86::SHRDir32 }, // SHR - { X86::SARir8, X86::SARir16, X86::SARir32, X86::SHRDir32 }, // SAR - { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SHL - { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SAL = SHL + { X86::SHR8ri, X86::SHR16ri, X86::SHR32ri, X86::SHRD32rri8 }, // SHR + { X86::SAR8ri, X86::SAR16ri, X86::SAR32ri, X86::SHRD32rri8 }, // SAR + { X86::SHL8ri, X86::SHL16ri, X86::SHL32ri, X86::SHLD32rri8 }, // SHL + { X86::SHL8ri, X86::SHL16ri, X86::SHL32ri, X86::SHLD32rri8 }, // SAL = SHL }; static const unsigned NonConstantOperand[][4] = { - { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32 }, // SHR - { X86::SARrr8, X86::SARrr16, X86::SARrr32 }, // SAR - { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SHL - { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SAL = SHL + { X86::SHR8rCL, X86::SHR16rCL, X86::SHR32rCL }, // SHR + { X86::SAR8rCL, X86::SAR16rCL, X86::SAR32rCL }, // SAR + { X86::SHL8rCL, X86::SHL16rCL, X86::SHL32rCL }, // SHL + { X86::SHL8rCL, X86::SHL16rCL, X86::SHL32rCL }, // SAL = SHL }; // Longs, as usual, are handled specially... @@ -1322,29 +1802,31 @@ void ISel::visitShiftInst(ShiftInst &I) { // If we have a constant shift, we can generate much more efficient code // than otherwise... // - if (ConstantUInt *CUI = dyn_cast(I.getOperand(1))) { + if (ConstantUInt *CUI = dyn_cast(ShiftAmount)) { unsigned Amount = CUI->getValue(); if (Amount < 32) { - const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned]; - if (isLeftShift) { - BuildMI(BB, Opc[3], 3, - DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addZImm(Amount); - BuildMI(BB, Opc[2], 2, DestReg).addReg(SrcReg).addZImm(Amount); - } else { - BuildMI(BB, Opc[3], 3, - DestReg).addReg(SrcReg ).addReg(SrcReg+1).addZImm(Amount); - BuildMI(BB, Opc[2], 2, DestReg+1).addReg(SrcReg+1).addZImm(Amount); - } + const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned]; + if (isLeftShift) { + BuildMI(*MBB, IP, Opc[3], 3, + DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addImm(Amount); + BuildMI(*MBB, IP, Opc[2], 2, DestReg).addReg(SrcReg).addImm(Amount); + } else { + BuildMI(*MBB, IP, Opc[3], 3, + DestReg).addReg(SrcReg ).addReg(SrcReg+1).addImm(Amount); + BuildMI(*MBB, IP, Opc[2],2,DestReg+1).addReg(SrcReg+1).addImm(Amount); + } } else { // Shifting more than 32 bits - Amount -= 32; - if (isLeftShift) { - BuildMI(BB, X86::SHLir32, 2,DestReg+1).addReg(SrcReg).addZImm(Amount); - BuildMI(BB, X86::MOVir32, 1,DestReg ).addZImm(0); - } else { - unsigned Opcode = isSigned ? X86::SARir32 : X86::SHRir32; - BuildMI(BB, Opcode, 2, DestReg).addReg(SrcReg+1).addZImm(Amount); - BuildMI(BB, X86::MOVir32, 1, DestReg+1).addZImm(0); - } + Amount -= 32; + if (isLeftShift) { + BuildMI(*MBB, IP, X86::SHL32ri, 2, + DestReg + 1).addReg(SrcReg).addImm(Amount); + BuildMI(*MBB, IP, X86::MOV32ri, 1, + DestReg).addImm(0); + } else { + unsigned Opcode = isSigned ? X86::SAR32ri : X86::SHR32ri; + BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(SrcReg+1).addImm(Amount); + BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0); + } } } else { unsigned TmpReg = makeAnotherReg(Type::IntTy); @@ -1353,141 +1835,71 @@ void ISel::visitShiftInst(ShiftInst &I) { // If this is a SHR of a Long, then we need to do funny sign extension // stuff. TmpReg gets the value to use as the high-part if we are // shifting more than 32 bits. - BuildMI(BB, X86::SARir32, 2, TmpReg).addReg(SrcReg).addZImm(31); + BuildMI(*MBB, IP, X86::SAR32ri, 2, TmpReg).addReg(SrcReg).addImm(31); } else { // Other shifts use a fixed zero value if the shift is more than 32 // bits. - BuildMI(BB, X86::MOVir32, 1, TmpReg).addZImm(0); + BuildMI(*MBB, IP, X86::MOV32ri, 1, TmpReg).addImm(0); } // Initialize CL with the shift amount... - unsigned ShiftAmount = getReg(I.getOperand(1)); - BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(ShiftAmount); + unsigned ShiftAmountReg = getReg(ShiftAmount, MBB, IP); + BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::CL).addReg(ShiftAmountReg); unsigned TmpReg2 = makeAnotherReg(Type::IntTy); unsigned TmpReg3 = makeAnotherReg(Type::IntTy); if (isLeftShift) { // TmpReg2 = shld inHi, inLo - BuildMI(BB, X86::SHLDrr32, 2, TmpReg2).addReg(SrcReg+1).addReg(SrcReg); + BuildMI(*MBB, IP, X86::SHLD32rrCL,2,TmpReg2).addReg(SrcReg+1) + .addReg(SrcReg); // TmpReg3 = shl inLo, CL - BuildMI(BB, X86::SHLrr32, 1, TmpReg3).addReg(SrcReg); + BuildMI(*MBB, IP, X86::SHL32rCL, 1, TmpReg3).addReg(SrcReg); // Set the flags to indicate whether the shift was by more than 32 bits. - BuildMI(BB, X86::TESTri8, 2).addReg(X86::CL).addZImm(32); + BuildMI(*MBB, IP, X86::TEST8ri, 2).addReg(X86::CL).addImm(32); // DestHi = (>32) ? TmpReg3 : TmpReg2; - BuildMI(BB, X86::CMOVNErr32, 2, + BuildMI(*MBB, IP, X86::CMOVNE32rr, 2, DestReg+1).addReg(TmpReg2).addReg(TmpReg3); // DestLo = (>32) ? TmpReg : TmpReg3; - BuildMI(BB, X86::CMOVNErr32, 2, DestReg).addReg(TmpReg3).addReg(TmpReg); + BuildMI(*MBB, IP, X86::CMOVNE32rr, 2, + DestReg).addReg(TmpReg3).addReg(TmpReg); } else { // TmpReg2 = shrd inLo, inHi - BuildMI(BB, X86::SHRDrr32, 2, TmpReg2).addReg(SrcReg).addReg(SrcReg+1); + BuildMI(*MBB, IP, X86::SHRD32rrCL,2,TmpReg2).addReg(SrcReg) + .addReg(SrcReg+1); // TmpReg3 = s[ah]r inHi, CL - BuildMI(BB, isSigned ? X86::SARrr32 : X86::SHRrr32, 1, TmpReg3) + BuildMI(*MBB, IP, isSigned ? X86::SAR32rCL : X86::SHR32rCL, 1, TmpReg3) .addReg(SrcReg+1); // Set the flags to indicate whether the shift was by more than 32 bits. - BuildMI(BB, X86::TESTri8, 2).addReg(X86::CL).addZImm(32); + BuildMI(*MBB, IP, X86::TEST8ri, 2).addReg(X86::CL).addImm(32); // DestLo = (>32) ? TmpReg3 : TmpReg2; - BuildMI(BB, X86::CMOVNErr32, 2, + BuildMI(*MBB, IP, X86::CMOVNE32rr, 2, DestReg).addReg(TmpReg2).addReg(TmpReg3); // DestHi = (>32) ? TmpReg : TmpReg3; - BuildMI(BB, X86::CMOVNErr32, 2, + BuildMI(*MBB, IP, X86::CMOVNE32rr, 2, DestReg+1).addReg(TmpReg3).addReg(TmpReg); } } return; } - if (ConstantUInt *CUI = dyn_cast(I.getOperand(1))) { + if (ConstantUInt *CUI = dyn_cast(ShiftAmount)) { // The shift amount is constant, guaranteed to be a ubyte. Get its value. assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?"); const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned]; - BuildMI(BB, Opc[Class], 2, DestReg).addReg(SrcReg).addZImm(CUI->getValue()); + BuildMI(*MBB, IP, Opc[Class], 2, + DestReg).addReg(SrcReg).addImm(CUI->getValue()); } else { // The shift amount is non-constant. - BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(getReg(I.getOperand(1))); + unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP); + BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::CL).addReg(ShiftAmountReg); const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned]; - BuildMI(BB, Opc[Class], 1, DestReg).addReg(SrcReg); - } -} - - -/// doFPLoad - This method is used to load an FP value from memory using the -/// current endianness. NOTE: This method returns a partially constructed load -/// instruction which needs to have the memory source filled in still. -/// -MachineInstr *ISel::doFPLoad(MachineBasicBlock *MBB, - MachineBasicBlock::iterator &MBBI, - const Type *Ty, unsigned DestReg) { - assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!"); - unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLDr32 : X86::FLDr64; - - if (TM.getTargetData().isLittleEndian()) // fast path... - return BMI(MBB, MBBI, LoadOpcode, 4, DestReg); - - // If we are big-endian, start by creating an LEA instruction to represent the - // address of the memory location to load from... - // - unsigned SrcAddrReg = makeAnotherReg(Type::UIntTy); - MachineInstr *Result = BMI(MBB, MBBI, X86::LEAr32, 5, SrcAddrReg); - - // Allocate a temporary stack slot to transform the value into... - int FrameIdx = F->getFrameInfo()->CreateStackObject(Ty, TM.getTargetData()); - - // Perform the bswaps 32 bits at a time... - unsigned TmpReg1 = makeAnotherReg(Type::UIntTy); - unsigned TmpReg2 = makeAnotherReg(Type::UIntTy); - addDirectMem(BMI(MBB, MBBI, X86::MOVmr32, 4, TmpReg1), SrcAddrReg); - BMI(MBB, MBBI, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1); - unsigned Offset = (Ty == Type::DoubleTy) << 2; - addFrameReference(BMI(MBB, MBBI, X86::MOVrm32, 5), - FrameIdx, Offset).addReg(TmpReg2); - - if (Ty == Type::DoubleTy) { // Swap the other 32 bits of a double value... - TmpReg1 = makeAnotherReg(Type::UIntTy); - TmpReg2 = makeAnotherReg(Type::UIntTy); - - addRegOffset(BMI(MBB, MBBI, X86::MOVmr32, 4, TmpReg1), SrcAddrReg, 4); - BMI(MBB, MBBI, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1); - unsigned Offset = (Ty == Type::DoubleTy) << 2; - addFrameReference(BMI(MBB, MBBI, X86::MOVrm32,5), FrameIdx).addReg(TmpReg2); - } - - // Now we can reload the final byteswapped result into the final destination. - addFrameReference(BMI(MBB, MBBI, LoadOpcode, 4, DestReg), FrameIdx); - return Result; -} - -/// EmitByteSwap - Byteswap SrcReg into DestReg. -/// -void ISel::EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class) { - // Emit the byte swap instruction... - switch (Class) { - case cByte: - // No byteswap necessary for 8 bit value... - BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(SrcReg); - break; - case cInt: - // Use the 32 bit bswap instruction to do a 32 bit swap... - BuildMI(BB, X86::BSWAPr32, 1, DestReg).addReg(SrcReg); - break; - - case cShort: - // For 16 bit we have to use an xchg instruction, because there is no - // 16-bit bswap. XCHG is necessarily not in SSA form, so we force things - // into AX to do the xchg. - // - BuildMI(BB, X86::MOVrr16, 1, X86::AX).addReg(SrcReg); - BuildMI(BB, X86::XCHGrr8, 2).addReg(X86::AL, MOTy::UseAndDef) - .addReg(X86::AH, MOTy::UseAndDef); - BuildMI(BB, X86::MOVrr16, 1, DestReg).addReg(X86::AX); - break; - default: assert(0 && "Cannot byteswap this class!"); + BuildMI(*MBB, IP, Opc[Class], 1, DestReg).addReg(SrcReg); } } @@ -1497,155 +1909,112 @@ void ISel::EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class) { /// need to worry about the memory layout of the target machine. /// void ISel::visitLoadInst(LoadInst &I) { - bool isLittleEndian = TM.getTargetData().isLittleEndian(); - bool hasLongPointers = TM.getTargetData().getPointerSize() == 8; - unsigned SrcAddrReg = getReg(I.getOperand(0)); unsigned DestReg = getReg(I); - - unsigned Class = getClassB(I.getType()); - switch (Class) { - case cFP: { - MachineBasicBlock::iterator MBBI = BB->end(); - addDirectMem(doFPLoad(BB, MBBI, I.getType(), DestReg), SrcAddrReg); - return; - } - case cLong: case cInt: case cShort: case cByte: - break; // Integers of various sizes handled below - default: assert(0 && "Unknown memory class!"); + unsigned BaseReg = 0, Scale = 1, IndexReg = 0, Disp = 0; + Value *Addr = I.getOperand(0); + if (GetElementPtrInst *GEP = dyn_cast(Addr)) { + if (isGEPFoldable(BB, GEP->getOperand(0), GEP->op_begin()+1, GEP->op_end(), + BaseReg, Scale, IndexReg, Disp)) + Addr = 0; // Address is consumed! + } else if (ConstantExpr *CE = dyn_cast(Addr)) { + if (CE->getOpcode() == Instruction::GetElementPtr) + if (isGEPFoldable(BB, CE->getOperand(0), CE->op_begin()+1, CE->op_end(), + BaseReg, Scale, IndexReg, Disp)) + Addr = 0; } - // We need to adjust the input pointer if we are emulating a big-endian - // long-pointer target. On these systems, the pointer that we are interested - // in is in the upper part of the eight byte memory image of the pointer. It - // also happens to be byte-swapped, but this will be handled later. - // - if (!isLittleEndian && hasLongPointers && isa(I.getType())) { - unsigned R = makeAnotherReg(Type::UIntTy); - BuildMI(BB, X86::ADDri32, 2, R).addReg(SrcAddrReg).addZImm(4); - SrcAddrReg = R; + if (Addr) { + // If it's not foldable, reset addr mode. + BaseReg = getReg(Addr); + Scale = 1; IndexReg = 0; Disp = 0; } - unsigned IReg = DestReg; - if (!isLittleEndian) // If big endian we need an intermediate stage - DestReg = makeAnotherReg(Class != cLong ? I.getType() : Type::UIntTy); - - static const unsigned Opcode[] = { - X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, 0, X86::MOVmr32 - }; - addDirectMem(BuildMI(BB, Opcode[Class], 4, DestReg), SrcAddrReg); - - // Handle long values now... + unsigned Class = getClassB(I.getType()); if (Class == cLong) { - if (isLittleEndian) { - addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), SrcAddrReg, 4); - } else { - EmitByteSwap(IReg+1, DestReg, cInt); - unsigned TempReg = makeAnotherReg(Type::IntTy); - addRegOffset(BuildMI(BB, X86::MOVmr32, 4, TempReg), SrcAddrReg, 4); - EmitByteSwap(IReg, TempReg, cInt); - } - return; - } - - if (!isLittleEndian) - EmitByteSwap(IReg, DestReg, Class); -} - - -/// doFPStore - This method is used to store an FP value to memory using the -/// current endianness. -/// -void ISel::doFPStore(const Type *Ty, unsigned DestAddrReg, unsigned SrcReg) { - assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!"); - unsigned StoreOpcode = Ty == Type::FloatTy ? X86::FSTr32 : X86::FSTr64; - - if (TM.getTargetData().isLittleEndian()) { // fast path... - addDirectMem(BuildMI(BB, StoreOpcode,5), DestAddrReg).addReg(SrcReg); + addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg), + BaseReg, Scale, IndexReg, Disp); + addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg+1), + BaseReg, Scale, IndexReg, Disp+4); return; } - // Allocate a temporary stack slot to transform the value into... - int FrameIdx = F->getFrameInfo()->CreateStackObject(Ty, TM.getTargetData()); - unsigned SrcAddrReg = makeAnotherReg(Type::UIntTy); - addFrameReference(BuildMI(BB, X86::LEAr32, 5, SrcAddrReg), FrameIdx); - - // Store the value into a temporary stack slot... - addDirectMem(BuildMI(BB, StoreOpcode, 5), SrcAddrReg).addReg(SrcReg); - - // Perform the bswaps 32 bits at a time... - unsigned TmpReg1 = makeAnotherReg(Type::UIntTy); - unsigned TmpReg2 = makeAnotherReg(Type::UIntTy); - addDirectMem(BuildMI(BB, X86::MOVmr32, 4, TmpReg1), SrcAddrReg); - BuildMI(BB, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1); - unsigned Offset = (Ty == Type::DoubleTy) << 2; - addRegOffset(BuildMI(BB, X86::MOVrm32, 5), - DestAddrReg, Offset).addReg(TmpReg2); - - if (Ty == Type::DoubleTy) { // Swap the other 32 bits of a double value... - TmpReg1 = makeAnotherReg(Type::UIntTy); - TmpReg2 = makeAnotherReg(Type::UIntTy); - - addRegOffset(BuildMI(BB, X86::MOVmr32, 4, TmpReg1), SrcAddrReg, 4); - BuildMI(BB, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1); - unsigned Offset = (Ty == Type::DoubleTy) << 2; - addDirectMem(BuildMI(BB, X86::MOVrm32, 5), DestAddrReg).addReg(TmpReg2); - } + static const unsigned Opcodes[] = { + X86::MOV8rm, X86::MOV16rm, X86::MOV32rm, X86::FLD32m + }; + unsigned Opcode = Opcodes[Class]; + if (I.getType() == Type::DoubleTy) Opcode = X86::FLD64m; + addFullAddress(BuildMI(BB, Opcode, 4, DestReg), + BaseReg, Scale, IndexReg, Disp); } - /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov' /// instruction. /// void ISel::visitStoreInst(StoreInst &I) { - bool isLittleEndian = TM.getTargetData().isLittleEndian(); - bool hasLongPointers = TM.getTargetData().getPointerSize() == 8; - unsigned ValReg = getReg(I.getOperand(0)); - unsigned AddressReg = getReg(I.getOperand(1)); - - unsigned Class = getClassB(I.getOperand(0)->getType()); - switch (Class) { - case cLong: - if (isLittleEndian) { - addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(ValReg); - addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4), - AddressReg, 4).addReg(ValReg+1); - } else { - unsigned T1 = makeAnotherReg(Type::IntTy); - unsigned T2 = makeAnotherReg(Type::IntTy); - EmitByteSwap(T1, ValReg , cInt); - EmitByteSwap(T2, ValReg+1, cInt); - addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(T2); - addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg, 4).addReg(T1); - } - return; - case cFP: - doFPStore(I.getOperand(0)->getType(), AddressReg, ValReg); - return; - case cInt: case cShort: case cByte: - break; // Integers of various sizes handled below - default: assert(0 && "Unknown memory class!"); + unsigned BaseReg = 0, Scale = 1, IndexReg = 0, Disp = 0; + Value *Addr = I.getOperand(1); + if (GetElementPtrInst *GEP = dyn_cast(Addr)) { + if (isGEPFoldable(BB, GEP->getOperand(0), GEP->op_begin()+1, GEP->op_end(), + BaseReg, Scale, IndexReg, Disp)) + Addr = 0; // Address is consumed! + } else if (ConstantExpr *CE = dyn_cast(Addr)) { + if (CE->getOpcode() == Instruction::GetElementPtr) + if (isGEPFoldable(BB, CE->getOperand(0), CE->op_begin()+1, CE->op_end(), + BaseReg, Scale, IndexReg, Disp)) + Addr = 0; } - if (!isLittleEndian && hasLongPointers && - isa(I.getOperand(0)->getType())) { - unsigned R = makeAnotherReg(Type::UIntTy); - BuildMI(BB, X86::ADDri32, 2, R).addReg(AddressReg).addZImm(4); - AddressReg = R; + if (Addr) { + // If it's not foldable, reset addr mode. + BaseReg = getReg(Addr); + Scale = 1; IndexReg = 0; Disp = 0; } - if (!isLittleEndian && Class != cByte) { - unsigned R = makeAnotherReg(I.getOperand(0)->getType()); - EmitByteSwap(R, ValReg, Class); - ValReg = R; - } + const Type *ValTy = I.getOperand(0)->getType(); + unsigned Class = getClassB(ValTy); - static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 }; - addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg); + if (ConstantInt *CI = dyn_cast(I.getOperand(0))) { + uint64_t Val = CI->getRawValue(); + if (Class == cLong) { + addFullAddress(BuildMI(BB, X86::MOV32mi, 5), + BaseReg, Scale, IndexReg, Disp).addImm(Val & ~0U); + addFullAddress(BuildMI(BB, X86::MOV32mi, 5), + BaseReg, Scale, IndexReg, Disp+4).addImm(Val>>32); + } else { + static const unsigned Opcodes[] = { + X86::MOV8mi, X86::MOV16mi, X86::MOV32mi + }; + unsigned Opcode = Opcodes[Class]; + addFullAddress(BuildMI(BB, Opcode, 5), + BaseReg, Scale, IndexReg, Disp).addImm(Val); + } + } else if (ConstantBool *CB = dyn_cast(I.getOperand(0))) { + addFullAddress(BuildMI(BB, X86::MOV8mi, 5), + BaseReg, Scale, IndexReg, Disp).addImm(CB->getValue()); + } else { + if (Class == cLong) { + unsigned ValReg = getReg(I.getOperand(0)); + addFullAddress(BuildMI(BB, X86::MOV32mr, 5), + BaseReg, Scale, IndexReg, Disp).addReg(ValReg); + addFullAddress(BuildMI(BB, X86::MOV32mr, 5), + BaseReg, Scale, IndexReg, Disp+4).addReg(ValReg+1); + } else { + unsigned ValReg = getReg(I.getOperand(0)); + static const unsigned Opcodes[] = { + X86::MOV8mr, X86::MOV16mr, X86::MOV32mr, X86::FST32m + }; + unsigned Opcode = Opcodes[Class]; + if (ValTy == Type::DoubleTy) Opcode = X86::FST64m; + addFullAddress(BuildMI(BB, Opcode, 1+4), + BaseReg, Scale, IndexReg, Disp).addReg(ValReg); + } + } } -/// visitCastInst - Here we have various kinds of copying with or without -/// sign extension going on. +/// visitCastInst - Here we have various kinds of copying with or without sign +/// extension going on. +/// void ISel::visitCastInst(CastInst &CI) { Value *Op = CI.getOperand(0); // If this is a cast from a 32-bit integer to a Long type, and the only uses @@ -1669,10 +2038,11 @@ void ISel::visitCastInst(CastInst &CI) { emitCastOperation(BB, MI, Op, CI.getType(), DestReg); } -/// emitCastOperation - Common code shared between visitCastInst and -/// constant expression cast support. +/// emitCastOperation - Common code shared between visitCastInst and constant +/// expression cast support. +/// void ISel::emitCastOperation(MachineBasicBlock *BB, - MachineBasicBlock::iterator &IP, + MachineBasicBlock::iterator IP, Value *Src, const Type *DestTy, unsigned DestReg) { unsigned SrcReg = getReg(Src, BB, IP); @@ -1685,56 +2055,58 @@ void ISel::emitCastOperation(MachineBasicBlock *BB, if (DestTy == Type::BoolTy) { switch (SrcClass) { case cByte: - BMI(BB, IP, X86::TESTrr8, 2).addReg(SrcReg).addReg(SrcReg); + BuildMI(*BB, IP, X86::TEST8rr, 2).addReg(SrcReg).addReg(SrcReg); break; case cShort: - BMI(BB, IP, X86::TESTrr16, 2).addReg(SrcReg).addReg(SrcReg); + BuildMI(*BB, IP, X86::TEST16rr, 2).addReg(SrcReg).addReg(SrcReg); break; case cInt: - BMI(BB, IP, X86::TESTrr32, 2).addReg(SrcReg).addReg(SrcReg); + BuildMI(*BB, IP, X86::TEST32rr, 2).addReg(SrcReg).addReg(SrcReg); break; case cLong: { unsigned TmpReg = makeAnotherReg(Type::IntTy); - BMI(BB, IP, X86::ORrr32, 2, TmpReg).addReg(SrcReg).addReg(SrcReg+1); + BuildMI(*BB, IP, X86::OR32rr, 2, TmpReg).addReg(SrcReg).addReg(SrcReg+1); break; } case cFP: - assert(0 && "FIXME: implement cast FP to bool"); - abort(); + BuildMI(*BB, IP, X86::FTST, 1).addReg(SrcReg); + BuildMI(*BB, IP, X86::FNSTSW8r, 0); + BuildMI(*BB, IP, X86::SAHF, 1); + break; } // If the zero flag is not set, then the value is true, set the byte to // true. - BMI(BB, IP, X86::SETNEr, 1, DestReg); + BuildMI(*BB, IP, X86::SETNEr, 1, DestReg); return; } static const unsigned RegRegMove[] = { - X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV, X86::MOVrr32 + X86::MOV8rr, X86::MOV16rr, X86::MOV32rr, X86::FpMOV, X86::MOV32rr }; // Implement casts between values of the same type class (as determined by // getClass) by using a register-to-register move. if (SrcClass == DestClass) { if (SrcClass <= cInt || (SrcClass == cFP && SrcTy == DestTy)) { - BMI(BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg); + BuildMI(*BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg); } else if (SrcClass == cFP) { if (SrcTy == Type::FloatTy) { // double -> float - assert(DestTy == Type::DoubleTy && "Unknown cFP member!"); - BMI(BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg); + assert(DestTy == Type::DoubleTy && "Unknown cFP member!"); + BuildMI(*BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg); } else { // float -> double - assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy && - "Unknown cFP member!"); - // Truncate from double to float by storing to memory as short, then - // reading it back. - unsigned FltAlign = TM.getTargetData().getFloatAlignment(); + assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy && + "Unknown cFP member!"); + // Truncate from double to float by storing to memory as short, then + // reading it back. + unsigned FltAlign = TM.getTargetData().getFloatAlignment(); int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign); - addFrameReference(BMI(BB, IP, X86::FSTr32, 5), FrameIdx).addReg(SrcReg); - addFrameReference(BMI(BB, IP, X86::FLDr32, 5, DestReg), FrameIdx); + addFrameReference(BuildMI(*BB, IP, X86::FST32m, 5), FrameIdx).addReg(SrcReg); + addFrameReference(BuildMI(*BB, IP, X86::FLD32m, 5, DestReg), FrameIdx); } } else if (SrcClass == cLong) { - BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg); - BMI(BB, IP, X86::MOVrr32, 1, DestReg+1).addReg(SrcReg+1); + BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg); + BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg+1).addReg(SrcReg+1); } else { assert(0 && "Cannot handle this type of cast instruction!"); abort(); @@ -1750,26 +2122,26 @@ void ISel::emitCastOperation(MachineBasicBlock *BB, if (isLong) DestClass = cInt; static const unsigned Opc[][4] = { - { X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16, X86::MOVrr32 }, // s - { X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16, X86::MOVrr32 } // u + { X86::MOVSX16rr8, X86::MOVSX32rr8, X86::MOVSX32rr16, X86::MOV32rr }, // s + { X86::MOVZX16rr8, X86::MOVZX32rr8, X86::MOVZX32rr16, X86::MOV32rr } // u }; bool isUnsigned = SrcTy->isUnsigned(); - BMI(BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1, + BuildMI(*BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1, DestReg).addReg(SrcReg); if (isLong) { // Handle upper 32 bits as appropriate... if (isUnsigned) // Zero out top bits... - BMI(BB, IP, X86::MOVir32, 1, DestReg+1).addZImm(0); + BuildMI(*BB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0); else // Sign extend bottom half... - BMI(BB, IP, X86::SARir32, 2, DestReg+1).addReg(DestReg).addZImm(31); + BuildMI(*BB, IP, X86::SAR32ri, 2, DestReg+1).addReg(DestReg).addImm(31); } return; } // Special case long -> int ... if (SrcClass == cLong && DestClass == cInt) { - BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg); + BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg); return; } @@ -1778,8 +2150,8 @@ void ISel::emitCastOperation(MachineBasicBlock *BB, if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt && SrcClass > DestClass) { static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX, 0, X86::EAX }; - BMI(BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg); - BMI(BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]); + BuildMI(*BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg); + BuildMI(*BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]); return; } @@ -1791,42 +2163,45 @@ void ISel::emitCastOperation(MachineBasicBlock *BB, // const Type *PromoteType = 0; unsigned PromoteOpcode; + unsigned RealDestReg = DestReg; switch (SrcTy->getPrimitiveID()) { case Type::BoolTyID: case Type::SByteTyID: // We don't have the facilities for directly loading byte sized data from // memory (even signed). Promote it to 16 bits. PromoteType = Type::ShortTy; - PromoteOpcode = X86::MOVSXr16r8; + PromoteOpcode = X86::MOVSX16rr8; break; case Type::UByteTyID: PromoteType = Type::ShortTy; - PromoteOpcode = X86::MOVZXr16r8; + PromoteOpcode = X86::MOVZX16rr8; break; case Type::UShortTyID: PromoteType = Type::IntTy; - PromoteOpcode = X86::MOVZXr32r16; + PromoteOpcode = X86::MOVZX32rr16; break; case Type::UIntTyID: { // Make a 64 bit temporary... and zero out the top of it... unsigned TmpReg = makeAnotherReg(Type::LongTy); - BMI(BB, IP, X86::MOVrr32, 1, TmpReg).addReg(SrcReg); - BMI(BB, IP, X86::MOVir32, 1, TmpReg+1).addZImm(0); + BuildMI(*BB, IP, X86::MOV32rr, 1, TmpReg).addReg(SrcReg); + BuildMI(*BB, IP, X86::MOV32ri, 1, TmpReg+1).addImm(0); SrcTy = Type::LongTy; SrcClass = cLong; SrcReg = TmpReg; break; } case Type::ULongTyID: - assert("FIXME: not implemented: cast ulong X to fp type!"); + // Don't fild into the read destination. + DestReg = makeAnotherReg(Type::DoubleTy); + break; default: // No promotion needed... break; } if (PromoteType) { unsigned TmpReg = makeAnotherReg(PromoteType); - BMI(BB, IP, SrcTy->isSigned() ? X86::MOVSXr16r8 : X86::MOVZXr16r8, - 1, TmpReg).addReg(SrcReg); + unsigned Opc = SrcTy->isSigned() ? X86::MOVSX16rr8 : X86::MOVZX16rr8; + BuildMI(*BB, IP, Opc, 1, TmpReg).addReg(SrcReg); SrcTy = PromoteType; SrcClass = getClass(PromoteType); SrcReg = TmpReg; @@ -1837,17 +2212,51 @@ void ISel::emitCastOperation(MachineBasicBlock *BB, F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData()); if (SrcClass == cLong) { - addFrameReference(BMI(BB, IP, X86::MOVrm32, 5), FrameIdx).addReg(SrcReg); - addFrameReference(BMI(BB, IP, X86::MOVrm32, 5), - FrameIdx, 4).addReg(SrcReg+1); + addFrameReference(BuildMI(*BB, IP, X86::MOV32mr, 5), + FrameIdx).addReg(SrcReg); + addFrameReference(BuildMI(*BB, IP, X86::MOV32mr, 5), + FrameIdx, 4).addReg(SrcReg+1); } else { - static const unsigned Op1[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 }; - addFrameReference(BMI(BB, IP, Op1[SrcClass], 5), FrameIdx).addReg(SrcReg); + static const unsigned Op1[] = { X86::MOV8mr, X86::MOV16mr, X86::MOV32mr }; + addFrameReference(BuildMI(*BB, IP, Op1[SrcClass], 5), + FrameIdx).addReg(SrcReg); } static const unsigned Op2[] = - { 0/*byte*/, X86::FILDr16, X86::FILDr32, 0/*FP*/, X86::FILDr64 }; - addFrameReference(BMI(BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx); + { 0/*byte*/, X86::FILD16m, X86::FILD32m, 0/*FP*/, X86::FILD64m }; + addFrameReference(BuildMI(*BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx); + + // We need special handling for unsigned 64-bit integer sources. If the + // input number has the "sign bit" set, then we loaded it incorrectly as a + // negative 64-bit number. In this case, add an offset value. + if (SrcTy == Type::ULongTy) { + // Emit a test instruction to see if the dynamic input value was signed. + BuildMI(*BB, IP, X86::TEST32rr, 2).addReg(SrcReg+1).addReg(SrcReg+1); + + // If the sign bit is set, get a pointer to an offset, otherwise get a + // pointer to a zero. + MachineConstantPool *CP = F->getConstantPool(); + unsigned Zero = makeAnotherReg(Type::IntTy); + Constant *Null = Constant::getNullValue(Type::UIntTy); + addConstantPoolReference(BuildMI(*BB, IP, X86::LEA32r, 5, Zero), + CP->getConstantPoolIndex(Null)); + unsigned Offset = makeAnotherReg(Type::IntTy); + Constant *OffsetCst = ConstantUInt::get(Type::UIntTy, 0x5f800000); + + addConstantPoolReference(BuildMI(*BB, IP, X86::LEA32r, 5, Offset), + CP->getConstantPoolIndex(OffsetCst)); + unsigned Addr = makeAnotherReg(Type::IntTy); + BuildMI(*BB, IP, X86::CMOVS32rr, 2, Addr).addReg(Zero).addReg(Offset); + + // Load the constant for an add. FIXME: this could make an 'fadd' that + // reads directly from memory, but we don't support these yet. + unsigned ConstReg = makeAnotherReg(Type::DoubleTy); + addDirectMem(BuildMI(*BB, IP, X86::FLD32m, 4, ConstReg), Addr); + + BuildMI(*BB, IP, X86::FpADD, 2, RealDestReg) + .addReg(ConstReg).addReg(DestReg); + } + return; } @@ -1857,21 +2266,23 @@ void ISel::emitCastOperation(MachineBasicBlock *BB, // mode when truncating to an integer value. // int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2); - addFrameReference(BMI(BB, IP, X86::FNSTCWm16, 4), CWFrameIdx); + addFrameReference(BuildMI(*BB, IP, X86::FNSTCW16m, 4), CWFrameIdx); // Load the old value of the high byte of the control word... unsigned HighPartOfCW = makeAnotherReg(Type::UByteTy); - addFrameReference(BMI(BB, IP, X86::MOVmr8, 4, HighPartOfCW), CWFrameIdx, 1); + addFrameReference(BuildMI(*BB, IP, X86::MOV8rm, 4, HighPartOfCW), + CWFrameIdx, 1); // Set the high part to be round to zero... - addFrameReference(BMI(BB, IP, X86::MOVim8, 5), CWFrameIdx, 1).addZImm(12); + addFrameReference(BuildMI(*BB, IP, X86::MOV8mi, 5), + CWFrameIdx, 1).addImm(12); // Reload the modified control word now... - addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx); + addFrameReference(BuildMI(*BB, IP, X86::FLDCW16m, 4), CWFrameIdx); // Restore the memory image of control word to original value - addFrameReference(BMI(BB, IP, X86::MOVrm8, 5), - CWFrameIdx, 1).addReg(HighPartOfCW); + addFrameReference(BuildMI(*BB, IP, X86::MOV8mr, 5), + CWFrameIdx, 1).addReg(HighPartOfCW); // We don't have the facilities for directly storing byte sized data to // memory. Promote it to 16 bits. We also must promote unsigned values to @@ -1895,19 +2306,21 @@ void ISel::emitCastOperation(MachineBasicBlock *BB, F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData()); static const unsigned Op1[] = - { 0, X86::FISTr16, X86::FISTr32, 0, X86::FISTPr64 }; - addFrameReference(BMI(BB, IP, Op1[StoreClass], 5), FrameIdx).addReg(SrcReg); + { 0, X86::FIST16m, X86::FIST32m, 0, X86::FISTP64m }; + addFrameReference(BuildMI(*BB, IP, Op1[StoreClass], 5), + FrameIdx).addReg(SrcReg); if (DestClass == cLong) { - addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg), FrameIdx); - addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg+1), FrameIdx, 4); + addFrameReference(BuildMI(*BB, IP, X86::MOV32rm, 4, DestReg), FrameIdx); + addFrameReference(BuildMI(*BB, IP, X86::MOV32rm, 4, DestReg+1), + FrameIdx, 4); } else { - static const unsigned Op2[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 }; - addFrameReference(BMI(BB, IP, Op2[DestClass], 4, DestReg), FrameIdx); + static const unsigned Op2[] = { X86::MOV8rm, X86::MOV16rm, X86::MOV32rm }; + addFrameReference(BuildMI(*BB, IP, Op2[DestClass], 4, DestReg), FrameIdx); } // Reload the original control word now... - addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx); + addFrameReference(BuildMI(*BB, IP, X86::FLDCW16m, 4), CWFrameIdx); return; } @@ -1916,106 +2329,261 @@ void ISel::emitCastOperation(MachineBasicBlock *BB, abort(); } -/// visitVarArgInst - Implement the va_arg instruction... +/// visitVANextInst - Implement the va_next instruction... /// -void ISel::visitVarArgInst(VarArgInst &I) { - unsigned SrcReg = getReg(I.getOperand(0)); +void ISel::visitVANextInst(VANextInst &I) { + unsigned VAList = getReg(I.getOperand(0)); unsigned DestReg = getReg(I); - // Load the va_list into a register... - unsigned VAList = makeAnotherReg(Type::UIntTy); - addDirectMem(BuildMI(BB, X86::MOVmr32, 4, VAList), SrcReg); - unsigned Size; - switch (I.getType()->getPrimitiveID()) { + switch (I.getArgType()->getPrimitiveID()) { default: std::cerr << I; - assert(0 && "Error: bad type for va_arg instruction!"); + assert(0 && "Error: bad type for va_next instruction!"); return; case Type::PointerTyID: case Type::UIntTyID: case Type::IntTyID: Size = 4; - addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList); break; case Type::ULongTyID: case Type::LongTyID: - Size = 8; - addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList); - addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), VAList, 4); - break; case Type::DoubleTyID: Size = 8; - addDirectMem(BuildMI(BB, X86::FLDr64, 4, DestReg), VAList); break; } // Increment the VAList pointer... - unsigned NextVAList = makeAnotherReg(Type::UIntTy); - BuildMI(BB, X86::ADDri32, 2, NextVAList).addReg(VAList).addZImm(Size); - - // Update the VAList in memory... - addDirectMem(BuildMI(BB, X86::MOVrm32, 5), SrcReg).addReg(NextVAList); + BuildMI(BB, X86::ADD32ri, 2, DestReg).addReg(VAList).addImm(Size); } +void ISel::visitVAArgInst(VAArgInst &I) { + unsigned VAList = getReg(I.getOperand(0)); + unsigned DestReg = getReg(I); -// ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It -// returns zero when the input is not exactly a power of two. -static unsigned ExactLog2(unsigned Val) { - if (Val == 0) return 0; - unsigned Count = 0; - while (Val != 1) { - if (Val & 1) return 0; - Val >>= 1; - ++Count; + switch (I.getType()->getPrimitiveID()) { + default: + std::cerr << I; + assert(0 && "Error: bad type for va_next instruction!"); + return; + case Type::PointerTyID: + case Type::UIntTyID: + case Type::IntTyID: + addDirectMem(BuildMI(BB, X86::MOV32rm, 4, DestReg), VAList); + break; + case Type::ULongTyID: + case Type::LongTyID: + addDirectMem(BuildMI(BB, X86::MOV32rm, 4, DestReg), VAList); + addRegOffset(BuildMI(BB, X86::MOV32rm, 4, DestReg+1), VAList, 4); + break; + case Type::DoubleTyID: + addDirectMem(BuildMI(BB, X86::FLD64m, 4, DestReg), VAList); + break; } - return Count+1; } +/// visitGetElementPtrInst - instruction-select GEP instructions +/// void ISel::visitGetElementPtrInst(GetElementPtrInst &I) { + // If this GEP instruction will be folded into all of its users, we don't need + // to explicitly calculate it! + unsigned A, B, C, D; + if (isGEPFoldable(0, I.getOperand(0), I.op_begin()+1, I.op_end(), A,B,C,D)) { + // Check all of the users of the instruction to see if they are loads and + // stores. + bool AllWillFold = true; + for (Value::use_iterator UI = I.use_begin(), E = I.use_end(); UI != E; ++UI) + if (cast(*UI)->getOpcode() != Instruction::Load) + if (cast(*UI)->getOpcode() != Instruction::Store || + cast(*UI)->getOperand(0) == &I) { + AllWillFold = false; + break; + } + + // If the instruction is foldable, and will be folded into all users, don't + // emit it! + if (AllWillFold) return; + } + unsigned outputReg = getReg(I); - MachineBasicBlock::iterator MI = BB->end(); - emitGEPOperation(BB, MI, I.getOperand(0), + emitGEPOperation(BB, BB->end(), I.getOperand(0), I.op_begin()+1, I.op_end(), outputReg); } +/// getGEPIndex - Inspect the getelementptr operands specified with GEPOps and +/// GEPTypes (the derived types being stepped through at each level). On return +/// from this function, if some indexes of the instruction are representable as +/// an X86 lea instruction, the machine operands are put into the Ops +/// instruction and the consumed indexes are poped from the GEPOps/GEPTypes +/// lists. Otherwise, GEPOps.size() is returned. If this returns a an +/// addressing mode that only partially consumes the input, the BaseReg input of +/// the addressing mode must be left free. +/// +/// Note that there is one fewer entry in GEPTypes than there is in GEPOps. +/// +void ISel::getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP, + std::vector &GEPOps, + std::vector &GEPTypes, unsigned &BaseReg, + unsigned &Scale, unsigned &IndexReg, unsigned &Disp) { + const TargetData &TD = TM.getTargetData(); + + // Clear out the state we are working with... + BaseReg = 0; // No base register + Scale = 1; // Unit scale + IndexReg = 0; // No index register + Disp = 0; // No displacement + + // While there are GEP indexes that can be folded into the current address, + // keep processing them. + while (!GEPTypes.empty()) { + if (const StructType *StTy = dyn_cast(GEPTypes.back())) { + // It's a struct access. CUI is the index into the structure, + // which names the field. This index must have unsigned type. + const ConstantUInt *CUI = cast(GEPOps.back()); + + // Use the TargetData structure to pick out what the layout of the + // structure is in memory. Since the structure index must be constant, we + // can get its value and use it to find the right byte offset from the + // StructLayout class's list of structure member offsets. + Disp += TD.getStructLayout(StTy)->MemberOffsets[CUI->getValue()]; + GEPOps.pop_back(); // Consume a GEP operand + GEPTypes.pop_back(); + } else { + // It's an array or pointer access: [ArraySize x ElementType]. + const SequentialType *SqTy = cast(GEPTypes.back()); + Value *idx = GEPOps.back(); + + // idx is the index into the array. Unlike with structure + // indices, we may not know its actual value at code-generation + // time. + assert(idx->getType() == Type::LongTy && "Bad GEP array index!"); + + // If idx is a constant, fold it into the offset. + unsigned TypeSize = TD.getTypeSize(SqTy->getElementType()); + if (ConstantSInt *CSI = dyn_cast(idx)) { + Disp += TypeSize*CSI->getValue(); + } else { + // If the index reg is already taken, we can't handle this index. + if (IndexReg) return; + + // If this is a size that we can handle, then add the index as + switch (TypeSize) { + case 1: case 2: case 4: case 8: + // These are all acceptable scales on X86. + Scale = TypeSize; + break; + default: + // Otherwise, we can't handle this scale + return; + } + + if (CastInst *CI = dyn_cast(idx)) + if (CI->getOperand(0)->getType() == Type::IntTy || + CI->getOperand(0)->getType() == Type::UIntTy) + idx = CI->getOperand(0); + + IndexReg = MBB ? getReg(idx, MBB, IP) : 1; + } + + GEPOps.pop_back(); // Consume a GEP operand + GEPTypes.pop_back(); + } + } + + // GEPTypes is empty, which means we have a single operand left. See if we + // can set it as the base register. + // + // FIXME: When addressing modes are more powerful/correct, we could load + // global addresses directly as 32-bit immediates. + assert(BaseReg == 0); + BaseReg = MBB ? getReg(GEPOps[0], MBB, IP) : 1; + GEPOps.pop_back(); // Consume the last GEP operand +} + + +/// isGEPFoldable - Return true if the specified GEP can be completely +/// folded into the addressing mode of a load/store or lea instruction. +bool ISel::isGEPFoldable(MachineBasicBlock *MBB, + Value *Src, User::op_iterator IdxBegin, + User::op_iterator IdxEnd, unsigned &BaseReg, + unsigned &Scale, unsigned &IndexReg, unsigned &Disp) { + if (ConstantPointerRef *CPR = dyn_cast(Src)) + Src = CPR->getValue(); + + std::vector GEPOps; + GEPOps.resize(IdxEnd-IdxBegin+1); + GEPOps[0] = Src; + std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1); + + std::vector GEPTypes; + GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd), + gep_type_end(Src->getType(), IdxBegin, IdxEnd)); + + MachineBasicBlock::iterator IP; + if (MBB) IP = MBB->end(); + getGEPIndex(MBB, IP, GEPOps, GEPTypes, BaseReg, Scale, IndexReg, Disp); + + // We can fold it away iff the getGEPIndex call eliminated all operands. + return GEPOps.empty(); +} + void ISel::emitGEPOperation(MachineBasicBlock *MBB, - MachineBasicBlock::iterator &IP, + MachineBasicBlock::iterator IP, Value *Src, User::op_iterator IdxBegin, User::op_iterator IdxEnd, unsigned TargetReg) { const TargetData &TD = TM.getTargetData(); - const Type *Ty = Src->getType(); - unsigned BaseReg = getReg(Src, MBB, IP); - - // GEPs have zero or more indices; we must perform a struct access - // or array access for each one. - for (GetElementPtrInst::op_iterator oi = IdxBegin, - oe = IdxEnd; oi != oe; ++oi) { - Value *idx = *oi; - unsigned NextReg = BaseReg; - if (const StructType *StTy = dyn_cast(Ty)) { - // It's a struct access. idx is the index into the structure, - // which names the field. This index must have ubyte type. - const ConstantUInt *CUI = cast(idx); - assert(CUI->getType() == Type::UByteTy - && "Funny-looking structure index in GEP"); - // Use the TargetData structure to pick out what the layout of - // the structure is in memory. Since the structure index must - // be constant, we can get its value and use it to find the - // right byte offset from the StructLayout class's list of - // structure member offsets. - unsigned idxValue = CUI->getValue(); - unsigned FieldOff = TD.getStructLayout(StTy)->MemberOffsets[idxValue]; - if (FieldOff) { - NextReg = makeAnotherReg(Type::UIntTy); - // Emit an ADD to add FieldOff to the basePtr. - BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(FieldOff); + if (ConstantPointerRef *CPR = dyn_cast(Src)) + Src = CPR->getValue(); + + std::vector GEPOps; + GEPOps.resize(IdxEnd-IdxBegin+1); + GEPOps[0] = Src; + std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1); + + std::vector GEPTypes; + GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd), + gep_type_end(Src->getType(), IdxBegin, IdxEnd)); + + // Keep emitting instructions until we consume the entire GEP instruction. + while (!GEPOps.empty()) { + unsigned OldSize = GEPOps.size(); + unsigned BaseReg, Scale, IndexReg, Disp; + getGEPIndex(MBB, IP, GEPOps, GEPTypes, BaseReg, Scale, IndexReg, Disp); + + if (GEPOps.size() != OldSize) { + // getGEPIndex consumed some of the input. Build an LEA instruction here. + unsigned NextTarget = 0; + if (!GEPOps.empty()) { + assert(BaseReg == 0 && + "getGEPIndex should have left the base register open for chaining!"); + NextTarget = BaseReg = makeAnotherReg(Type::UIntTy); } - // The next type is the member of the structure selected by the - // index. - Ty = StTy->getElementTypes()[idxValue]; - } else if (const SequentialType *SqTy = cast(Ty)) { + + if (IndexReg == 0 && Disp == 0) + BuildMI(*MBB, IP, X86::MOV32rr, 1, TargetReg).addReg(BaseReg); + else + addFullAddress(BuildMI(*MBB, IP, X86::LEA32r, 5, TargetReg), + BaseReg, Scale, IndexReg, Disp); + --IP; + TargetReg = NextTarget; + } else if (GEPTypes.empty()) { + // The getGEPIndex operation didn't want to build an LEA. Check to see if + // all operands are consumed but the base pointer. If so, just load it + // into the register. + if (GlobalValue *GV = dyn_cast(GEPOps[0])) { + BuildMI(*MBB, IP, X86::MOV32ri, 1, TargetReg).addGlobalAddress(GV); + } else { + unsigned BaseReg = getReg(GEPOps[0], MBB, IP); + BuildMI(*MBB, IP, X86::MOV32rr, 1, TargetReg).addReg(BaseReg); + } + break; // we are now done + + } else { // It's an array or pointer access: [ArraySize x ElementType]. + const SequentialType *SqTy = cast(GEPTypes.back()); + Value *idx = GEPOps.back(); + GEPOps.pop_back(); // Consume a GEP operand + GEPTypes.pop_back(); // idx is the index into the array. Unlike with structure // indices, we may not know its actual value at code-generation @@ -2032,51 +2600,54 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB, // We want to add BaseReg to(idxReg * sizeof ElementType). First, we // must find the size of the pointed-to type (Not coincidentally, the next // type is the type of the elements in the array). - Ty = SqTy->getElementType(); - unsigned elementSize = TD.getTypeSize(Ty); + const Type *ElTy = SqTy->getElementType(); + unsigned elementSize = TD.getTypeSize(ElTy); // If idxReg is a constant, we don't need to perform the multiply! if (ConstantSInt *CSI = dyn_cast(idx)) { if (!CSI->isNullValue()) { unsigned Offset = elementSize*CSI->getValue(); - NextReg = makeAnotherReg(Type::UIntTy); - BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(Offset); + unsigned Reg = makeAnotherReg(Type::UIntTy); + BuildMI(*MBB, IP, X86::ADD32ri, 2, TargetReg) + .addReg(Reg).addImm(Offset); + --IP; // Insert the next instruction before this one. + TargetReg = Reg; // Codegen the rest of the GEP into this } } else if (elementSize == 1) { // If the element size is 1, we don't have to multiply, just add unsigned idxReg = getReg(idx, MBB, IP); - NextReg = makeAnotherReg(Type::UIntTy); - BMI(MBB, IP, X86::ADDrr32, 2, NextReg).addReg(BaseReg).addReg(idxReg); + unsigned Reg = makeAnotherReg(Type::UIntTy); + BuildMI(*MBB, IP, X86::ADD32rr, 2,TargetReg).addReg(Reg).addReg(idxReg); + --IP; // Insert the next instruction before this one. + TargetReg = Reg; // Codegen the rest of the GEP into this } else { unsigned idxReg = getReg(idx, MBB, IP); unsigned OffsetReg = makeAnotherReg(Type::UIntTy); - if (unsigned Shift = ExactLog2(elementSize)) { - // If the element size is exactly a power of 2, use a shift to get it. - BMI(MBB, IP, X86::SHLir32, 2, - OffsetReg).addReg(idxReg).addZImm(Shift-1); - } else { - // Most general case, emit a multiply... - unsigned elementSizeReg = makeAnotherReg(Type::LongTy); - BMI(MBB, IP, X86::MOVir32, 1, elementSizeReg).addZImm(elementSize); - - // Emit a MUL to multiply the register holding the index by - // elementSize, putting the result in OffsetReg. - doMultiply(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSizeReg); - } + + // Make sure we can back the iterator up to point to the first + // instruction emitted. + MachineBasicBlock::iterator BeforeIt = IP; + if (IP == MBB->begin()) + BeforeIt = MBB->end(); + else + --BeforeIt; + doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize); + // Emit an ADD to add OffsetReg to the basePtr. - NextReg = makeAnotherReg(Type::UIntTy); - BMI(MBB, IP, X86::ADDrr32, 2,NextReg).addReg(BaseReg).addReg(OffsetReg); + unsigned Reg = makeAnotherReg(Type::UIntTy); + BuildMI(*MBB, IP, X86::ADD32rr, 2, TargetReg) + .addReg(Reg).addReg(OffsetReg); + + // Step to the first instruction of the multiply. + if (BeforeIt == MBB->end()) + IP = MBB->begin(); + else + IP = ++BeforeIt; + + TargetReg = Reg; // Codegen the rest of the GEP into this } } - // Now that we are here, further indices refer to subtypes of this - // one, so we don't need to worry about BaseReg itself, anymore. - BaseReg = NextReg; } - // After we have processed all the indices, the result is left in - // BaseReg. Move it to the register where we were expected to - // put the answer. A 32-bit move should do it, because we are in - // ILP32 land. - BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg(BaseReg); } @@ -2098,7 +2669,7 @@ void ISel::visitAllocaInst(AllocaInst &I) { // Create a new stack object using the frame manager... int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment); - addFrameReference(BuildMI(BB, X86::LEAr32, 5, getReg(I)), FrameIdx); + addFrameReference(BuildMI(BB, X86::LEA32r, 5, getReg(I)), FrameIdx); return; } } @@ -2107,27 +2678,25 @@ void ISel::visitAllocaInst(AllocaInst &I) { // constant by the variable amount. unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy); unsigned SrcReg1 = getReg(I.getArraySize()); - unsigned SizeReg = makeAnotherReg(Type::UIntTy); - BuildMI(BB, X86::MOVir32, 1, SizeReg).addZImm(TySize); // TotalSizeReg = mul , MachineBasicBlock::iterator MBBI = BB->end(); - doMultiply(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, SizeReg); + doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize); // AddedSize = add , 15 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy); - BuildMI(BB, X86::ADDri32, 2, AddedSizeReg).addReg(TotalSizeReg).addZImm(15); + BuildMI(BB, X86::ADD32ri, 2, AddedSizeReg).addReg(TotalSizeReg).addImm(15); // AlignedSize = and , ~15 unsigned AlignedSize = makeAnotherReg(Type::UIntTy); - BuildMI(BB, X86::ANDri32, 2, AlignedSize).addReg(AddedSizeReg).addZImm(~15); + BuildMI(BB, X86::AND32ri, 2, AlignedSize).addReg(AddedSizeReg).addImm(~15); // Subtract size from stack pointer, thereby allocating some space. - BuildMI(BB, X86::SUBrr32, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize); + BuildMI(BB, X86::SUB32rr, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize); // Put a pointer to the space into the result register, by copying // the stack pointer. - BuildMI(BB, X86::MOVrr32, 1, getReg(I)).addReg(X86::ESP); + BuildMI(BB, X86::MOV32rr, 1, getReg(I)).addReg(X86::ESP); // Inform the Frame Information that we have just allocated a variable-sized // object. @@ -2145,16 +2714,15 @@ void ISel::visitMallocInst(MallocInst &I) { Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize)); } else { Arg = makeAnotherReg(Type::UIntTy); - unsigned Op0Reg = getReg(ConstantUInt::get(Type::UIntTy, AllocSize)); - unsigned Op1Reg = getReg(I.getOperand(0)); + unsigned Op0Reg = getReg(I.getOperand(0)); MachineBasicBlock::iterator MBBI = BB->end(); - doMultiply(BB, MBBI, Arg, Type::UIntTy, Op0Reg, Op1Reg); + doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize); } std::vector Args; Args.push_back(ValueRecord(Arg, Type::UIntTy)); MachineInstr *TheCall = BuildMI(X86::CALLpcrel32, - 1).addExternalSymbol("malloc", true); + 1).addExternalSymbol("malloc", true); doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args); } @@ -2166,15 +2734,14 @@ void ISel::visitFreeInst(FreeInst &I) { std::vector Args; Args.push_back(ValueRecord(I.getOperand(0))); MachineInstr *TheCall = BuildMI(X86::CALLpcrel32, - 1).addExternalSymbol("free", true); + 1).addExternalSymbol("free", true); doCall(ValueRecord(0, Type::VoidTy), TheCall, Args); } - /// createX86SimpleInstructionSelector - This pass converts an LLVM function /// into a machine code representation is a very simple peep-hole fashion. The /// generated code sucks but the implementation is nice and simple. /// -FunctionPass *createX86SimpleInstructionSelector(TargetMachine &TM) { +FunctionPass *llvm::createX86SimpleInstructionSelector(TargetMachine &TM) { return new ISel(TM); }