X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FMakefile;h=e518fecf044fd68ec576c26f8acabeaa63f0bebe;hb=9ec9305f0679d052d7311691291e184cde92353c;hp=896feae08dd55f3f3f03f93cf1d9ebf23f79e0e9;hpb=0a8fd30c1bb4f324a9bca9b7b7c0efb0fa341112;p=oota-llvm.git

diff --git a/lib/Target/X86/Makefile b/lib/Target/X86/Makefile
index 896feae08dd..e518fecf044 100644
--- a/lib/Target/X86/Makefile
+++ b/lib/Target/X86/Makefile
@@ -1,56 +1,23 @@
 ##===- lib/Target/X86/Makefile -----------------------------*- Makefile -*-===##
-# 
+#
 #                     The LLVM Compiler Infrastructure
 #
-# This file was developed by the LLVM research group and is distributed under
-# the University of Illinois Open Source License. See LICENSE.TXT for details.
-# 
+# This file is distributed under the University of Illinois Open Source
+# License. See LICENSE.TXT for details.
+#
 ##===----------------------------------------------------------------------===##
+
 LEVEL = ../../..
-LIBRARYNAME = x86
-include $(LEVEL)/Makefile.common
+LIBRARYNAME = LLVMX86CodeGen
+TARGET = X86
 
 # Make sure that tblgen is run, first thing.
-$(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
-                 X86GenRegisterInfo.inc X86GenInstrNames.inc \
-                 X86GenInstrInfo.inc X86GenSimpInstrSelector.inc \
-		 X86GenInstrSelector.inc
-
-X86GenRegisterNames.inc::  $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \
-                           $(SourceDir)/../Target.td $(TBLGEN)
-	@echo "Building X86.td register names with tblgen"
-	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
-
-X86GenRegisterInfo.h.inc:: $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \
-                           $(SourceDir)/../Target.td $(TBLGEN)
-	@echo "Building X86.td register information header with tblgen"
-	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
-
-X86GenRegisterInfo.inc:: $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \
-                         $(SourceDir)/../Target.td $(TBLGEN)
-	@echo "Building X86.td register information implementation with tblgen"
-	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
+BUILT_SOURCES = X86GenRegisterInfo.inc X86GenInstrInfo.inc \
+		X86GenAsmWriter.inc X86GenAsmMatcher.inc \
+                X86GenAsmWriter1.inc X86GenDAGISel.inc  \
+                X86GenDisassemblerTables.inc X86GenFastISel.inc \
+                X86GenCallingConv.inc X86GenSubtargetInfo.inc
 
-X86GenInstrNames.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \
-                       $(SourceDir)/../Target.td $(TBLGEN)
-	@echo "Building X86.td instruction names with tblgen"
-	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
+DIRS = InstPrinter AsmParser Disassembler TargetInfo MCTargetDesc Utils
 
-X86GenInstrInfo.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \
-                      $(SourceDir)/../Target.td $(TBLGEN)
-	@echo "Building X86.td instruction information with tblgen"
-	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
-
-X86GenSimpInstrSelector.inc:: $(SourceDir)/X86InstrSel.td $(TBLGEN)
-	@echo "Building X86.td simple instruction selector with tblgen"
-	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-simp-instr-sel -o $@
-
-X86GenInstrSelector.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \
-                          $(SourceDir)/../Target.td $(TBLGEN)
-	@echo "Building X86.td instruction selector with tblgen"
-	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
-
-
-
-clean::
-	$(VERB) rm -f *.inc
+include $(LEVEL)/Makefile.common