X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FPrinter.cpp;h=95e8642a0d276ab1284cda3badb2b8c0a93e5717;hb=98938f83d52e01b10e34f9fc6db55e4787fa3dad;hp=a80e7d26642186632f6f0dd5afd9bf745d14157c;hpb=3faae2dbc2196c60d27eb64e8d5797e826879f95;p=oota-llvm.git diff --git a/lib/Target/X86/Printer.cpp b/lib/Target/X86/Printer.cpp index a80e7d26642..95e8642a0d2 100644 --- a/lib/Target/X86/Printer.cpp +++ b/lib/Target/X86/Printer.cpp @@ -7,21 +7,26 @@ #include "X86.h" #include "X86InstrInfo.h" -#include "llvm/Pass.h" #include "llvm/Function.h" +#include "llvm/Constant.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineInstr.h" #include "Support/Statistic.h" namespace { - struct Printer : public FunctionPass { - TargetMachine &TM; + struct Printer : public MachineFunctionPass { std::ostream &O; + unsigned ConstIdx; + Printer(std::ostream &o) : O(o), ConstIdx(0) {} - Printer(TargetMachine &tm, std::ostream &o) : TM(tm), O(o) {} + virtual const char *getPassName() const { + return "X86 Assembly Printer"; + } - bool runOnFunction(Function &F); + void printConstantPool(MachineConstantPool *MCP, const TargetData &TD); + bool runOnMachineFunction(MachineFunction &F); }; } @@ -29,67 +34,72 @@ namespace { /// the specified stream. This function should work regardless of whether or /// not the function is in SSA form or not. /// -Pass *createX86CodePrinterPass(TargetMachine &TM, std::ostream &O) { - return new Printer(TM, O); +Pass *createX86CodePrinterPass(std::ostream &O) { + return new Printer(O); } +// printConstantPool - Print out any constants which have been spilled to +// memory... +void Printer::printConstantPool(MachineConstantPool *MCP, const TargetData &TD){ + const std::vector &CP = MCP->getConstants(); + if (CP.empty()) return; + + for (unsigned i = 0, e = CP.size(); i != e; ++i) { + O << "\t.section .rodata\n"; + O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType()) << "\n"; + O << ".CPI" << i+ConstIdx << ":\t\t\t\t\t;" << *CP[i] << "\n"; + O << "\t*Constant output not implemented yet!*\n\n"; + } + ConstIdx += CP.size(); // Don't recycle constant pool index numbers +} + /// runOnFunction - This uses the X86InstructionInfo::print method /// to print assembly for each instruction. -bool Printer::runOnFunction (Function & F) -{ - static unsigned bbnumber = 0; - MachineFunction & MF = MachineFunction::get (&F); - const MachineInstrInfo & MII = TM.getInstrInfo (); +bool Printer::runOnMachineFunction(MachineFunction &MF) { + static unsigned BBNumber = 0; + const TargetMachine &TM = MF.getTarget(); + const TargetInstrInfo &TII = TM.getInstrInfo(); + + // Print out constants referenced by the function + printConstantPool(MF.getConstantPool(), TM.getTargetData()); // Print out labels for the function. - O << "\t.globl\t" << F.getName () << "\n"; - O << "\t.type\t" << F.getName () << ", @function\n"; - O << F.getName () << ":\n"; + O << "\t.text\n"; + O << "\t.align 16\n"; + O << "\t.globl\t" << MF.getFunction()->getName() << "\n"; + O << "\t.type\t" << MF.getFunction()->getName() << ", @function\n"; + O << MF.getFunction()->getName() << ":\n"; // Print out code for the function. - for (MachineFunction::const_iterator bb_i = MF.begin (), bb_e = MF.end (); - bb_i != bb_e; ++bb_i) - { - // Print a label for the basic block. - O << ".BB" << bbnumber++ << ":\n"; - for (MachineBasicBlock::const_iterator i_i = bb_i->begin (), i_e = - bb_i->end (); i_i != i_e; ++i_i) - { - // Print the assembly for the instruction. - O << "\t"; - MII.print(*i_i, O, TM); - } + for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); + I != E; ++I) { + // Print a label for the basic block. + O << ".BB" << BBNumber++ << ":\n"; + for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end(); + II != E; ++II) { + // Print the assembly for the instruction. + O << "\t"; + TII.print(*II, O, TM); } + } // We didn't modify anything. return false; } -static bool isReg(const MachineOperand &MO) { - return MO.getType() == MachineOperand::MO_VirtualRegister || - MO.getType() == MachineOperand::MO_MachineRegister; -} - -static bool isImmediate(const MachineOperand &MO) { - return MO.getType() == MachineOperand::MO_SignExtendedImmed || - MO.getType() == MachineOperand::MO_UnextendedImmed; -} - -static bool isPCRelativeDisp(const MachineOperand &MO) { - return MO.getType() == MachineOperand::MO_PCRelativeDisp; -} - static bool isScale(const MachineOperand &MO) { - return isImmediate(MO) && + return MO.isImmediate() && (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 || MO.getImmedValue() == 4 || MO.getImmedValue() == 8); } static bool isMem(const MachineInstr *MI, unsigned Op) { + if (MI->getOperand(Op).isFrameIndex()) return true; + if (MI->getOperand(Op).isConstantPoolIndex()) return true; return Op+4 <= MI->getNumOperands() && - isReg(MI->getOperand(Op )) && isScale(MI->getOperand(Op+1)) && - isReg(MI->getOperand(Op+2)) && isImmediate(MI->getOperand(Op+3)); + MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) && + MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate(); } static void printOp(std::ostream &O, const MachineOperand &MO, @@ -100,6 +110,7 @@ static void printOp(std::ostream &O, const MachineOperand &MO, O << "<" << V->getName() << ">"; return; } + // FALLTHROUGH case MachineOperand::MO_MachineRegister: if (MO.getReg() < MRegisterInfo::FirstVirtualRegister) O << RI.get(MO.getReg()).Name; @@ -114,30 +125,52 @@ static void printOp(std::ostream &O, const MachineOperand &MO, case MachineOperand::MO_PCRelativeDisp: O << "<" << MO.getVRegValue()->getName() << ">"; return; + case MachineOperand::MO_GlobalAddress: + O << "<" << MO.getGlobal()->getName() << ">"; + return; + case MachineOperand::MO_ExternalSymbol: + O << "<" << MO.getSymbolName() << ">"; + return; default: O << ""; return; } } -static const std::string sizePtr (const MachineInstrDescriptor &Desc) { +static const std::string sizePtr(const TargetInstrDescriptor &Desc) { switch (Desc.TSFlags & X86II::ArgMask) { + default: assert(0 && "Unknown arg size!"); case X86II::Arg8: return "BYTE PTR"; case X86II::Arg16: return "WORD PTR"; case X86II::Arg32: return "DWORD PTR"; case X86II::Arg64: return "QWORD PTR"; - case X86II::Arg80: return "XWORD PTR"; - case X86II::Arg128: return "128BIT PTR"; // dunno what the real one is - default: return " PTR"; // crack being smoked + case X86II::ArgF32: return "DWORD PTR"; + case X86II::ArgF64: return "QWORD PTR"; + case X86II::ArgF80: return "XWORD PTR"; } } static void printMemReference(std::ostream &O, const MachineInstr *MI, unsigned Op, const MRegisterInfo &RI) { assert(isMem(MI, Op) && "Invalid memory reference!"); + + if (MI->getOperand(Op).isFrameIndex()) { + O << "[frame slot #" << MI->getOperand(Op).getFrameIndex(); + if (MI->getOperand(Op+3).getImmedValue()) + O << " + " << MI->getOperand(Op+3).getImmedValue(); + O << "]"; + return; + } else if (MI->getOperand(Op).isConstantPoolIndex()) { + O << "[.CPI" << MI->getOperand(Op).getConstantPoolIndex(); + if (MI->getOperand(Op+3).getImmedValue()) + O << " + " << MI->getOperand(Op+3).getImmedValue(); + O << "]"; + return; + } + const MachineOperand &BaseReg = MI->getOperand(Op); - const MachineOperand &Scale = MI->getOperand(Op+1); + int ScaleVal = MI->getOperand(Op+1).getImmedValue(); const MachineOperand &IndexReg = MI->getOperand(Op+2); - const MachineOperand &Disp = MI->getOperand(Op+3); + int DispVal = MI->getOperand(Op+3).getImmedValue(); O << "["; bool NeedPlus = false; @@ -148,15 +181,21 @@ static void printMemReference(std::ostream &O, const MachineInstr *MI, if (IndexReg.getReg()) { if (NeedPlus) O << " + "; - if (Scale.getImmedValue() != 1) - O << Scale.getImmedValue() << "*"; + if (ScaleVal != 1) + O << ScaleVal << "*"; printOp(O, IndexReg, RI); NeedPlus = true; } - if (Disp.getImmedValue()) { - if (NeedPlus) O << " + "; - printOp(O, Disp, RI); + if (DispVal) { + if (NeedPlus) + if (DispVal > 0) + O << " + "; + else { + O << " - "; + DispVal = -DispVal; + } + O << DispVal; } O << "]"; } @@ -165,34 +204,53 @@ static void printMemReference(std::ostream &O, const MachineInstr *MI, void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, const TargetMachine &TM) const { unsigned Opcode = MI->getOpcode(); - const MachineInstrDescriptor &Desc = get(Opcode); + const TargetInstrDescriptor &Desc = get(Opcode); - if (Opcode == X86::PHI) { - printOp(O, MI->getOperand(0), RI); - O << " = phi "; - for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) { - if (i != 1) O << ", "; - O << "["; - printOp(O, MI->getOperand(i), RI); - O << ", "; - printOp(O, MI->getOperand(i+1), RI); - O << "]"; + switch (Desc.TSFlags & X86II::FormMask) { + case X86II::Pseudo: + if (Opcode == X86::PHI) { + printOp(O, MI->getOperand(0), RI); + O << " = phi "; + for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) { + if (i != 1) O << ", "; + O << "["; + printOp(O, MI->getOperand(i), RI); + O << ", "; + printOp(O, MI->getOperand(i+1), RI); + O << "]"; + } + } else { + unsigned i = 0; + if (MI->getNumOperands() && MI->getOperand(0).opIsDef()) { + printOp(O, MI->getOperand(0), RI); + O << " = "; + ++i; + } + O << getName(MI->getOpcode()); + + for (unsigned e = MI->getNumOperands(); i != e; ++i) { + O << " "; + if (MI->getOperand(i).opIsDef()) O << "*"; + printOp(O, MI->getOperand(i), RI); + if (MI->getOperand(i).opIsDef()) O << "*"; + } } O << "\n"; return; - } - - switch (Desc.TSFlags & X86II::FormMask) { case X86II::RawFrm: // The accepted forms of Raw instructions are: // 1. nop - No operand required // 2. jmp foo - PC relative displacement operand + // 3. call bar - GlobalAddress Operand or External Symbol Operand // assert(MI->getNumOperands() == 0 || - (MI->getNumOperands() == 1 && isPCRelativeDisp(MI->getOperand(0))) && + (MI->getNumOperands() == 1 && + (MI->getOperand(0).isPCRelativeDisp() || + MI->getOperand(0).isGlobalAddress() || + MI->getOperand(0).isExternalSymbol())) && "Illegal raw instruction!"); - O << getName(MI->getOpCode()) << " "; + O << getName(MI->getOpcode()) << " "; if (MI->getNumOperands() == 1) { printOp(O, MI->getOperand(0), RI); @@ -206,20 +264,28 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, // or it takes a register and an immediate of the same size as the register // (move immediate f.e.). Note that this immediate value might be stored as // an LLVM value, to represent, for example, loading the address of a global - // into a register. + // into a register. The initial register might be duplicated if this is a + // M_2_ADDR_REG instruction // - assert(isReg(MI->getOperand(0)) && + assert(MI->getOperand(0).isRegister() && (MI->getNumOperands() == 1 || (MI->getNumOperands() == 2 && (MI->getOperand(1).getVRegValueOrNull() || - isImmediate(MI->getOperand(1))))) && + MI->getOperand(1).isImmediate() || + MI->getOperand(1).isRegister() || + MI->getOperand(1).isGlobalAddress() || + MI->getOperand(1).isExternalSymbol()))) && "Illegal form for AddRegFrm instruction!"); unsigned Reg = MI->getOperand(0).getReg(); O << getName(MI->getOpCode()) << " "; printOp(O, MI->getOperand(0), RI); - if (MI->getNumOperands() == 2) { + if (MI->getNumOperands() == 2 && + (!MI->getOperand(1).isRegister() || + MI->getOperand(1).getVRegValueOrNull() || + MI->getOperand(1).isGlobalAddress() || + MI->getOperand(1).isExternalSymbol())) { O << ", "; printOp(O, MI->getOperand(1), RI); } @@ -227,29 +293,36 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, return; } case X86II::MRMDestReg: { - // There are two acceptable forms of MRMDestReg instructions, those with 3 - // and 2 operands: + // There are two acceptable forms of MRMDestReg instructions, those with 2, + // 3 and 4 operands: + // + // 2 Operands: this is for things like mov that do not read a second input // // 3 Operands: in this form, the first two registers (the destination, and // the first operand) should be the same, post register allocation. The 3rd // operand is an additional input. This should be for things like add // instructions. // - // 2 Operands: this is for things like mov that do not read a second input + // 4 Operands: This form is for instructions which are 3 operands forms, but + // have a constant argument as well. // - assert(isReg(MI->getOperand(0)) && - (MI->getNumOperands() == 2 || - (MI->getNumOperands() == 3 && isReg(MI->getOperand(1)))) && - isReg(MI->getOperand(MI->getNumOperands()-1)) + bool isTwoAddr = isTwoAddrInstr(Opcode); + assert(MI->getOperand(0).isRegister() && + (MI->getNumOperands() == 2 || + (isTwoAddr && MI->getOperand(1).isRegister() && + MI->getOperand(0).getReg() == MI->getOperand(1).getReg() && + (MI->getNumOperands() == 3 || + (MI->getNumOperands() == 4 && MI->getOperand(3).isImmediate())))) && "Bad format for MRMDestReg!"); - if (MI->getNumOperands() == 3 && - MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) - O << "**"; O << getName(MI->getOpCode()) << " "; printOp(O, MI->getOperand(0), RI); O << ", "; - printOp(O, MI->getOperand(MI->getNumOperands()-1), RI); + printOp(O, MI->getOperand(1+isTwoAddr), RI); + if (MI->getNumOperands() == 4) { + O << ", "; + printOp(O, MI->getOperand(3), RI); + } O << "\n"; return; } @@ -259,9 +332,9 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, // register reference for the mod/rm field, it's a memory reference. // assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 && - isReg(MI->getOperand(4)) && "Bad format for MRMDestMem!"); + MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!"); - O << getName(MI->getOpCode()) << " " << sizePtr (Desc) << " "; + O << getName(MI->getOpCode()) << " " << sizePtr(Desc) << " "; printMemReference(O, MI, 0, RI); O << ", "; printOp(O, MI->getOperand(4), RI); @@ -279,11 +352,11 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, // // 2 Operands: this is for things like mov that do not read a second input // - assert(isReg(MI->getOperand(0)) && - isReg(MI->getOperand(1)) && + assert(MI->getOperand(0).isRegister() && + MI->getOperand(1).isRegister() && (MI->getNumOperands() == 2 || - (MI->getNumOperands() == 3 && isReg(MI->getOperand(2)))) - && "Bad format for MRMDestReg!"); + (MI->getNumOperands() == 3 && MI->getOperand(2).isRegister())) + && "Bad format for MRMSrcReg!"); if (MI->getNumOperands() == 3 && MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) O << "**"; @@ -300,9 +373,9 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, // These instructions are the same as MRMSrcReg, but instead of having a // register reference for the mod/rm field, it's a memory reference. // - assert(isReg(MI->getOperand(0)) && + assert(MI->getOperand(0).isRegister() && (MI->getNumOperands() == 1+4 && isMem(MI, 1)) || - (MI->getNumOperands() == 2+4 && isReg(MI->getOperand(1)) && + (MI->getNumOperands() == 2+4 && MI->getOperand(1).isRegister() && isMem(MI, 2)) && "Bad format for MRMDestReg!"); if (MI->getNumOperands() == 2+4 && @@ -311,7 +384,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, O << getName(MI->getOpCode()) << " "; printOp(O, MI->getOperand(0), RI); - O << ", " << sizePtr (Desc) << " "; + O << ", " << sizePtr(Desc) << " "; printMemReference(O, MI, MI->getNumOperands()-4, RI); O << "\n"; return; @@ -328,21 +401,21 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, // 3. sbb rdest, rinput, immediate [rdest = rinput] // assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 && - isReg(MI->getOperand(0)) && "Bad MRMSxR format!"); + MI->getOperand(0).isRegister() && "Bad MRMSxR format!"); assert((MI->getNumOperands() != 2 || - isReg(MI->getOperand(1)) || isImmediate(MI->getOperand(1))) && + MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&& "Bad MRMSxR format!"); assert((MI->getNumOperands() < 3 || - (isReg(MI->getOperand(1)) && isImmediate(MI->getOperand(2)))) && + (MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) && "Bad MRMSxR format!"); - if (MI->getNumOperands() > 1 && isReg(MI->getOperand(1)) && + if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() && MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) O << "**"; O << getName(MI->getOpCode()) << " "; printOp(O, MI->getOperand(0), RI); - if (isImmediate(MI->getOperand(MI->getNumOperands()-1))) { + if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) { O << ", "; printOp(O, MI->getOperand(MI->getNumOperands()-1), RI); } @@ -351,7 +424,33 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, return; } + case X86II::MRMS0m: case X86II::MRMS1m: + case X86II::MRMS2m: case X86II::MRMS3m: + case X86II::MRMS4m: case X86II::MRMS5m: + case X86II::MRMS6m: case X86II::MRMS7m: { + // In this form, the following are valid formats: + // 1. sete [m] + // 2. cmp [m], immediate + // 2. shl [m], rinput + // 3. sbb [m], immediate + // + assert(MI->getNumOperands() >= 4 && MI->getNumOperands() <= 5 && + isMem(MI, 0) && "Bad MRMSxM format!"); + assert((MI->getNumOperands() != 5 || MI->getOperand(4).isImmediate()) && + "Bad MRMSxM format!"); + + O << getName(MI->getOpCode()) << " "; + O << sizePtr(Desc) << " "; + printMemReference(O, MI, 0, RI); + if (MI->getNumOperands() == 5) { + O << ", "; + printOp(O, MI->getOperand(4), RI); + } + O << "\n"; + return; + } + default: - O << "\t\t\t-"; MI->print(O, TM); break; + O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, TM); break; } }