X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FPrinter.cpp;h=bfaa4bd1acd30c287178a2092f8f87bdaddc95d3;hb=2adb3959f629bdacab0e47b29e52139595523236;hp=8bf9968c0620a7f97d1034a899df8f971fa8d35f;hpb=e1f0d8113adc8687658af524a01385f606ee36b3;p=oota-llvm.git diff --git a/lib/Target/X86/Printer.cpp b/lib/Target/X86/Printer.cpp index 8bf9968c062..bfaa4bd1acd 100644 --- a/lib/Target/X86/Printer.cpp +++ b/lib/Target/X86/Printer.cpp @@ -12,6 +12,7 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstr.h" +#include "Support/Statistic.h" namespace { struct Printer : public FunctionPass { @@ -41,8 +42,6 @@ bool Printer::runOnFunction (Function & F) MachineFunction & MF = MachineFunction::get (&F); const MachineInstrInfo & MII = TM.getInstrInfo (); - O << "; x86 printing only sorta implemented so far!\n"; - // Print out labels for the function. O << "\t.globl\t" << F.getName () << "\n"; O << "\t.type\t" << F.getName () << ", @function\n"; @@ -67,35 +66,88 @@ bool Printer::runOnFunction (Function & F) return false; } +static bool isReg(const MachineOperand &MO) { + return MO.getType() == MachineOperand::MO_VirtualRegister || + MO.getType() == MachineOperand::MO_MachineRegister; +} + +static bool isImmediate(const MachineOperand &MO) { + return MO.getType() == MachineOperand::MO_SignExtendedImmed || + MO.getType() == MachineOperand::MO_UnextendedImmed; +} + +static bool isPCRelativeDisp(const MachineOperand &MO) { + return MO.getType() == MachineOperand::MO_PCRelativeDisp; +} + +static bool isScale(const MachineOperand &MO) { + return isImmediate(MO) && + (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 || + MO.getImmedValue() == 4 || MO.getImmedValue() == 8); +} + +static bool isMem(const MachineInstr *MI, unsigned Op) { + return Op+4 <= MI->getNumOperands() && + isReg(MI->getOperand(Op )) && isScale(MI->getOperand(Op+1)) && + isReg(MI->getOperand(Op+2)) && isImmediate(MI->getOperand(Op+3)); +} + static void printOp(std::ostream &O, const MachineOperand &MO, const MRegisterInfo &RI) { switch (MO.getType()) { case MachineOperand::MO_VirtualRegister: + if (Value *V = MO.getVRegValueOrNull()) { + O << "<" << V->getName() << ">"; + return; + } case MachineOperand::MO_MachineRegister: if (MO.getReg() < MRegisterInfo::FirstVirtualRegister) O << RI.get(MO.getReg()).Name; else O << "%reg" << MO.getReg(); return; - + + case MachineOperand::MO_SignExtendedImmed: + case MachineOperand::MO_UnextendedImmed: + O << (int)MO.getImmedValue(); + return; + case MachineOperand::MO_PCRelativeDisp: + O << "<" << MO.getVRegValue()->getName() << ">"; + return; default: O << ""; return; } } -static inline void toHexDigit(std::ostream &O, unsigned char V) { - if (V >= 10) - O << (char)('A'+V-10); - else - O << (char)('0'+V); -} +static void printMemReference(std::ostream &O, const MachineInstr *MI, + unsigned Op, const MRegisterInfo &RI) { + assert(isMem(MI, Op) && "Invalid memory reference!"); + const MachineOperand &BaseReg = MI->getOperand(Op); + const MachineOperand &Scale = MI->getOperand(Op+1); + const MachineOperand &IndexReg = MI->getOperand(Op+2); + const MachineOperand &Disp = MI->getOperand(Op+3); -static std::ostream &toHex(std::ostream &O, unsigned char V) { - toHexDigit(O, V >> 4); - toHexDigit(O, V & 0xF); - return O; -} + O << "["; + bool NeedPlus = false; + if (BaseReg.getReg()) { + printOp(O, BaseReg, RI); + NeedPlus = true; + } + + if (IndexReg.getReg()) { + if (NeedPlus) O << " + "; + if (IndexReg.getImmedValue() != 1) + O << IndexReg.getImmedValue() << "*"; + printOp(O, IndexReg, RI); + NeedPlus = true; + } + if (Disp.getImmedValue()) { + if (NeedPlus) O << " + "; + printOp(O, Disp, RI); + } + O << "]"; +} // print - Print out an x86 instruction in intel syntax void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, @@ -103,30 +155,50 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, unsigned Opcode = MI->getOpcode(); const MachineInstrDescriptor &Desc = get(Opcode); - if (Desc.TSFlags & X86II::TB) - O << "0F "; - switch (Desc.TSFlags & X86II::FormMask) { - case X86II::OtherFrm: - O << "\t"; - O << "-"; MI->print(O, TM); - break; case X86II::RawFrm: - toHex(O, getBaseOpcodeFor(Opcode)) << "\t"; + // The accepted forms of Raw instructions are: + // 1. nop - No operand required + // 2. jmp foo - PC relative displacement operand + // + assert(MI->getNumOperands() == 0 || + (MI->getNumOperands() == 1 && isPCRelativeDisp(MI->getOperand(0))) && + "Illegal raw instruction!"); O << getName(MI->getOpCode()) << " "; - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - if (i) O << ", "; - printOp(O, MI->getOperand(i), RI); + if (MI->getNumOperands() == 1) { + printOp(O, MI->getOperand(0), RI); } O << "\n"; return; + case X86II::AddRegFrm: { + // There are currently two forms of acceptable AddRegFrm instructions. + // Either the instruction JUST takes a single register (like inc, dec, etc), + // or it takes a register and an immediate of the same size as the register + // (move immediate f.e.). Note that this immediate value might be stored as + // an LLVM value, to represent, for example, loading the address of a global + // into a register. + // + assert(isReg(MI->getOperand(0)) && + (MI->getNumOperands() == 1 || + (MI->getNumOperands() == 2 && + (MI->getOperand(1).getVRegValueOrNull() || + isImmediate(MI->getOperand(1))))) && + "Illegal form for AddRegFrm instruction!"); - case X86II::AddRegFrm: - O << "\t-"; MI->print(O, TM); break; - - case X86II::MRMDestReg: + unsigned Reg = MI->getOperand(0).getReg(); + + O << getName(MI->getOpCode()) << " "; + printOp(O, MI->getOperand(0), RI); + if (MI->getNumOperands() == 2) { + O << ", "; + printOp(O, MI->getOperand(1), RI); + } + O << "\n"; + return; + } + case X86II::MRMDestReg: { // There are two acceptable forms of MRMDestReg instructions, those with 3 // and 2 operands: // @@ -137,36 +209,121 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, // // 2 Operands: this is for things like mov that do not read a second input // - assert(((MI->getNumOperands() == 3 && - (MI->getOperand(0).getType()==MachineOperand::MO_VirtualRegister|| - MI->getOperand(0).getType()==MachineOperand::MO_MachineRegister) - && - (MI->getOperand(1).getType()==MachineOperand::MO_VirtualRegister|| - MI->getOperand(1).getType()==MachineOperand::MO_MachineRegister)) - || - (MI->getNumOperands() == 2 && - (MI->getOperand(0).getType()==MachineOperand::MO_VirtualRegister|| - MI->getOperand(0).getType()==MachineOperand::MO_MachineRegister) - && (MI->getOperand(MI->getNumOperands()-1).getType() == - MachineOperand::MO_VirtualRegister|| - MI->getOperand(MI->getNumOperands()-1).getType() == - MachineOperand::MO_MachineRegister))) + assert(isReg(MI->getOperand(0)) && + (MI->getNumOperands() == 2 || + (MI->getNumOperands() == 3 && isReg(MI->getOperand(1)))) && + isReg(MI->getOperand(MI->getNumOperands()-1)) && "Bad format for MRMDestReg!"); if (MI->getNumOperands() == 3 && MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) O << "**"; - O << "\t"; O << getName(MI->getOpCode()) << " "; printOp(O, MI->getOperand(0), RI); O << ", "; printOp(O, MI->getOperand(MI->getNumOperands()-1), RI); O << "\n"; return; - case X86II::MRMDestMem: - case X86II::MRMSrcReg: - case X86II::MRMSrcMem: + } + + case X86II::MRMDestMem: { + // These instructions are the same as MRMDestReg, but instead of having a + // register reference for the mod/rm field, it's a memory reference. + // + assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 && + isReg(MI->getOperand(4)) && "Bad format for MRMDestMem!"); + + O << getName(MI->getOpCode()) << " PTR "; + printMemReference(O, MI, 0, RI); + O << ", "; + printOp(O, MI->getOperand(4), RI); + O << "\n"; + return; + } + + case X86II::MRMSrcReg: { + // There is a two forms that are acceptable for MRMSrcReg instructions, + // those with 3 and 2 operands: + // + // 3 Operands: in this form, the last register (the second input) is the + // ModR/M input. The first two operands should be the same, post register + // allocation. This is for things like: add r32, r/m32 + // + // 2 Operands: this is for things like mov that do not read a second input + // + assert(isReg(MI->getOperand(0)) && + isReg(MI->getOperand(1)) && + (MI->getNumOperands() == 2 || + (MI->getNumOperands() == 3 && isReg(MI->getOperand(2)))) + && "Bad format for MRMDestReg!"); + if (MI->getNumOperands() == 3 && + MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) + O << "**"; + + O << getName(MI->getOpCode()) << " "; + printOp(O, MI->getOperand(0), RI); + O << ", "; + printOp(O, MI->getOperand(MI->getNumOperands()-1), RI); + O << "\n"; + return; + } + + case X86II::MRMSrcMem: { + // These instructions are the same as MRMSrcReg, but instead of having a + // register reference for the mod/rm field, it's a memory reference. + // + assert(isReg(MI->getOperand(0)) && + (MI->getNumOperands() == 1+4 && isMem(MI, 1)) || + (MI->getNumOperands() == 2+4 && isReg(MI->getOperand(1)) && + isMem(MI, 2)) + && "Bad format for MRMDestReg!"); + if (MI->getNumOperands() == 2+4 && + MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) + O << "**"; + + O << getName(MI->getOpCode()) << " "; + printOp(O, MI->getOperand(0), RI); + O << ", PTR "; + printMemReference(O, MI, MI->getNumOperands()-4, RI); + O << "\n"; + return; + } + + case X86II::MRMS0r: case X86II::MRMS1r: + case X86II::MRMS2r: case X86II::MRMS3r: + case X86II::MRMS4r: case X86II::MRMS5r: + case X86II::MRMS6r: case X86II::MRMS7r: { + // In this form, the following are valid formats: + // 1. sete r + // 2. cmp reg, immediate + // 2. shl rdest, rinput + // 3. sbb rdest, rinput, immediate [rdest = rinput] + // + assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 && + isReg(MI->getOperand(0)) && "Bad MRMSxR format!"); + assert((MI->getNumOperands() != 2 || + isReg(MI->getOperand(1)) || isImmediate(MI->getOperand(1))) && + "Bad MRMSxR format!"); + assert((MI->getNumOperands() < 3 || + (isReg(MI->getOperand(1)) && isImmediate(MI->getOperand(2)))) && + "Bad MRMSxR format!"); + + if (MI->getNumOperands() > 1 && isReg(MI->getOperand(1)) && + MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) + O << "**"; + + O << getName(MI->getOpCode()) << " "; + printOp(O, MI->getOperand(0), RI); + if (isImmediate(MI->getOperand(MI->getNumOperands()-1))) { + O << ", "; + printOp(O, MI->getOperand(MI->getNumOperands()-1), RI); + } + O << "\n"; + + return; + } + default: - O << "\t-"; MI->print(O, TM); break; + O << "\t\t\t-"; MI->print(O, TM); break; } }