X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86AsmPrinter.cpp;h=88dc554957e12d8e775b1bec3b2a22f1285db3c5;hb=439b76730d40e8a8a95f2231bce95ff211a95ead;hp=bfaa4bd1acd30c287178a2092f8f87bdaddc95d3;hpb=ac573f61b4cc095f9b5c7b48728e4d3e85087c2f;p=oota-llvm.git diff --git a/lib/Target/X86/X86AsmPrinter.cpp b/lib/Target/X86/X86AsmPrinter.cpp index bfaa4bd1acd..88dc554957e 100644 --- a/lib/Target/X86/X86AsmPrinter.cpp +++ b/lib/Target/X86/X86AsmPrinter.cpp @@ -66,30 +66,16 @@ bool Printer::runOnFunction (Function & F) return false; } -static bool isReg(const MachineOperand &MO) { - return MO.getType() == MachineOperand::MO_VirtualRegister || - MO.getType() == MachineOperand::MO_MachineRegister; -} - -static bool isImmediate(const MachineOperand &MO) { - return MO.getType() == MachineOperand::MO_SignExtendedImmed || - MO.getType() == MachineOperand::MO_UnextendedImmed; -} - -static bool isPCRelativeDisp(const MachineOperand &MO) { - return MO.getType() == MachineOperand::MO_PCRelativeDisp; -} - static bool isScale(const MachineOperand &MO) { - return isImmediate(MO) && + return MO.isImmediate() && (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 || MO.getImmedValue() == 4 || MO.getImmedValue() == 8); } static bool isMem(const MachineInstr *MI, unsigned Op) { return Op+4 <= MI->getNumOperands() && - isReg(MI->getOperand(Op )) && isScale(MI->getOperand(Op+1)) && - isReg(MI->getOperand(Op+2)) && isImmediate(MI->getOperand(Op+3)); + MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) && + MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate(); } static void printOp(std::ostream &O, const MachineOperand &MO, @@ -119,6 +105,18 @@ static void printOp(std::ostream &O, const MachineOperand &MO, } } +static const std::string sizePtr (const MachineInstrDescriptor &Desc) { + switch (Desc.TSFlags & X86II::ArgMask) { + case X86II::Arg8: return "BYTE PTR"; + case X86II::Arg16: return "WORD PTR"; + case X86II::Arg32: return "DWORD PTR"; + case X86II::Arg64: return "QWORD PTR"; + case X86II::Arg80: return "XWORD PTR"; + case X86II::Arg128: return "128BIT PTR"; // dunno what the real one is + default: return " PTR"; // crack being smoked + } +} + static void printMemReference(std::ostream &O, const MachineInstr *MI, unsigned Op, const MRegisterInfo &RI) { assert(isMem(MI, Op) && "Invalid memory reference!"); @@ -136,8 +134,8 @@ static void printMemReference(std::ostream &O, const MachineInstr *MI, if (IndexReg.getReg()) { if (NeedPlus) O << " + "; - if (IndexReg.getImmedValue() != 1) - O << IndexReg.getImmedValue() << "*"; + if (Scale.getImmedValue() != 1) + O << Scale.getImmedValue() << "*"; printOp(O, IndexReg, RI); NeedPlus = true; } @@ -155,6 +153,22 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, unsigned Opcode = MI->getOpcode(); const MachineInstrDescriptor &Desc = get(Opcode); + if (Opcode == X86::PHI) { + printOp(O, MI->getOperand(0), RI); + O << " = phi "; + for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) { + if (i != 1) O << ", "; + O << "["; + printOp(O, MI->getOperand(i), RI); + O << ", "; + printOp(O, MI->getOperand(i+1), RI); + O << "]"; + } + O << "\n"; + return; + } + + switch (Desc.TSFlags & X86II::FormMask) { case X86II::RawFrm: // The accepted forms of Raw instructions are: @@ -162,7 +176,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, // 2. jmp foo - PC relative displacement operand // assert(MI->getNumOperands() == 0 || - (MI->getNumOperands() == 1 && isPCRelativeDisp(MI->getOperand(0))) && + (MI->getNumOperands() == 1 && MI->getOperand(0).isPCRelativeDisp())&& "Illegal raw instruction!"); O << getName(MI->getOpCode()) << " "; @@ -180,11 +194,11 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, // an LLVM value, to represent, for example, loading the address of a global // into a register. // - assert(isReg(MI->getOperand(0)) && + assert(MI->getOperand(0).isRegister() && (MI->getNumOperands() == 1 || (MI->getNumOperands() == 2 && (MI->getOperand(1).getVRegValueOrNull() || - isImmediate(MI->getOperand(1))))) && + MI->getOperand(1).isImmediate()))) && "Illegal form for AddRegFrm instruction!"); unsigned Reg = MI->getOperand(0).getReg(); @@ -209,10 +223,10 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, // // 2 Operands: this is for things like mov that do not read a second input // - assert(isReg(MI->getOperand(0)) && + assert(MI->getOperand(0).isRegister() && (MI->getNumOperands() == 2 || - (MI->getNumOperands() == 3 && isReg(MI->getOperand(1)))) && - isReg(MI->getOperand(MI->getNumOperands()-1)) + (MI->getNumOperands() == 3 && MI->getOperand(1).isRegister())) && + MI->getOperand(MI->getNumOperands()-1).isRegister() && "Bad format for MRMDestReg!"); if (MI->getNumOperands() == 3 && MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) @@ -231,9 +245,9 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, // register reference for the mod/rm field, it's a memory reference. // assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 && - isReg(MI->getOperand(4)) && "Bad format for MRMDestMem!"); + MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!"); - O << getName(MI->getOpCode()) << " PTR "; + O << getName(MI->getOpCode()) << " " << sizePtr (Desc) << " "; printMemReference(O, MI, 0, RI); O << ", "; printOp(O, MI->getOperand(4), RI); @@ -251,10 +265,10 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, // // 2 Operands: this is for things like mov that do not read a second input // - assert(isReg(MI->getOperand(0)) && - isReg(MI->getOperand(1)) && + assert(MI->getOperand(0).isRegister() && + MI->getOperand(1).isRegister() && (MI->getNumOperands() == 2 || - (MI->getNumOperands() == 3 && isReg(MI->getOperand(2)))) + (MI->getNumOperands() == 3 && MI->getOperand(2).isRegister())) && "Bad format for MRMDestReg!"); if (MI->getNumOperands() == 3 && MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) @@ -272,9 +286,9 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, // These instructions are the same as MRMSrcReg, but instead of having a // register reference for the mod/rm field, it's a memory reference. // - assert(isReg(MI->getOperand(0)) && + assert(MI->getOperand(0).isRegister() && (MI->getNumOperands() == 1+4 && isMem(MI, 1)) || - (MI->getNumOperands() == 2+4 && isReg(MI->getOperand(1)) && + (MI->getNumOperands() == 2+4 && MI->getOperand(1).isRegister() && isMem(MI, 2)) && "Bad format for MRMDestReg!"); if (MI->getNumOperands() == 2+4 && @@ -283,7 +297,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, O << getName(MI->getOpCode()) << " "; printOp(O, MI->getOperand(0), RI); - O << ", PTR "; + O << ", " << sizePtr (Desc) << " "; printMemReference(O, MI, MI->getNumOperands()-4, RI); O << "\n"; return; @@ -300,21 +314,21 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, // 3. sbb rdest, rinput, immediate [rdest = rinput] // assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 && - isReg(MI->getOperand(0)) && "Bad MRMSxR format!"); + MI->getOperand(0).isRegister() && "Bad MRMSxR format!"); assert((MI->getNumOperands() != 2 || - isReg(MI->getOperand(1)) || isImmediate(MI->getOperand(1))) && + MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&& "Bad MRMSxR format!"); assert((MI->getNumOperands() < 3 || - (isReg(MI->getOperand(1)) && isImmediate(MI->getOperand(2)))) && + (MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) && "Bad MRMSxR format!"); - if (MI->getNumOperands() > 1 && isReg(MI->getOperand(1)) && + if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() && MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) O << "**"; O << getName(MI->getOpCode()) << " "; printOp(O, MI->getOperand(0), RI); - if (isImmediate(MI->getOperand(MI->getNumOperands()-1))) { + if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) { O << ", "; printOp(O, MI->getOperand(MI->getNumOperands()-1), RI); }