X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86CodeEmitter.cpp;h=1dc6e7692506822f8531b8ea630c1836ebf18888;hb=15a380a03567deba90c074a2cd5a45b81ae0958b;hp=db80d9f892eb20f4891602844d073225e3622e9e;hpb=794fd75c67a2cdc128d67342c6d88a504d186896;p=oota-llvm.git diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index db80d9f892e..1dc6e769250 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -14,39 +14,50 @@ #define DEBUG_TYPE "x86-emitter" #include "X86InstrInfo.h" +#include "X86JITInfo.h" #include "X86Subtarget.h" #include "X86TargetMachine.h" #include "X86Relocations.h" #include "X86.h" #include "llvm/PassManager.h" #include "llvm/CodeGen/MachineCodeEmitter.h" +#include "llvm/CodeGen/JITCodeEmitter.h" +#include "llvm/CodeGen/ObjectCodeEmitter.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/Function.h" #include "llvm/ADT/Statistic.h" #include "llvm/Support/Compiler.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetOptions.h" using namespace llvm; STATISTIC(NumEmitted, "Number of machine instructions emitted"); namespace { +template class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass { const X86InstrInfo *II; const TargetData *TD; - TargetMachine &TM; - MachineCodeEmitter &MCE; + X86TargetMachine &TM; + CodeEmitter &MCE; + intptr_t PICBaseOffset; bool Is64BitMode; + bool IsPIC; public: - static const int ID; - explicit Emitter(TargetMachine &tm, MachineCodeEmitter &mce) - : MachineFunctionPass((intptr_t)&ID), II(0), TD(0), TM(tm), - MCE(mce), Is64BitMode(false) {} - Emitter(TargetMachine &tm, MachineCodeEmitter &mce, + static char ID; + explicit Emitter(X86TargetMachine &tm, CodeEmitter &mce) + : MachineFunctionPass(&ID), II(0), TD(0), TM(tm), + MCE(mce), PICBaseOffset(0), Is64BitMode(false), + IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} + Emitter(X86TargetMachine &tm, CodeEmitter &mce, const X86InstrInfo &ii, const TargetData &td, bool is64) - : MachineFunctionPass((intptr_t)&ID), II(&ii), TD(&td), TM(tm), - MCE(mce), Is64BitMode(is64) {} + : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm), + MCE(mce), PICBaseOffset(0), Is64BitMode(is64), + IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} bool runOnMachineFunction(MachineFunction &MF); @@ -54,78 +65,99 @@ namespace { return "X86 Machine Code Emitter"; } - void emitInstruction(const MachineInstr &MI); + void emitInstruction(const MachineInstr &MI, + const TargetInstrDesc *Desc); + + void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired(); + MachineFunctionPass::getAnalysisUsage(AU); + } private: void emitPCRelativeBlockAddress(MachineBasicBlock *MBB); - void emitPCRelativeValue(intptr_t Address); - void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub); - void emitGlobalAddressForPtr(GlobalValue *GV, unsigned Reloc, - int Disp = 0, unsigned PCAdj = 0); + void emitGlobalAddress(GlobalValue *GV, unsigned Reloc, + intptr_t Disp = 0, intptr_t PCAdj = 0, + bool NeedStub = false, bool Indirect = false); void emitExternalSymbolAddress(const char *ES, unsigned Reloc); - void emitConstPoolAddress(unsigned CPI, unsigned Reloc, int Disp = 0, - unsigned PCAdj = 0); - void emitJumpTableAddress(unsigned JTI, unsigned Reloc, unsigned PCAdj = 0); + void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0, + intptr_t PCAdj = 0); + void emitJumpTableAddress(unsigned JTI, unsigned Reloc, + intptr_t PCAdj = 0); void emitDisplacementField(const MachineOperand *RelocOp, int DispVal, - unsigned PCAdj = 0); + intptr_t PCAdj = 0); void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField); + void emitRegModRMByte(unsigned RegOpcodeField); void emitSIBByte(unsigned SS, unsigned Index, unsigned Base); void emitConstant(uint64_t Val, unsigned Size); void emitMemModRMByte(const MachineInstr &MI, unsigned Op, unsigned RegOpcodeField, - unsigned PCAdj = 0); + intptr_t PCAdj = 0); - unsigned getX86RegNum(unsigned RegNo); - bool isX86_64ExtendedReg(const MachineOperand &MO); - unsigned determineREX(const MachineInstr &MI); + unsigned getX86RegNum(unsigned RegNo) const; + + bool gvNeedsNonLazyPtr(const GlobalValue *GV); }; - const int Emitter::ID = 0; + +template + char Emitter::ID = 0; } /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code -/// to the specified MCE object. +/// to the specified templated MachineCodeEmitter object. + FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM, MachineCodeEmitter &MCE) { - return new Emitter(TM, MCE); + return new Emitter(TM, MCE); +} +FunctionPass *llvm::createX86JITCodeEmitterPass(X86TargetMachine &TM, + JITCodeEmitter &JCE) { + return new Emitter(TM, JCE); +} +FunctionPass *llvm::createX86ObjectCodeEmitterPass(X86TargetMachine &TM, + ObjectCodeEmitter &OCE) { + return new Emitter(TM, OCE); } -bool Emitter::runOnMachineFunction(MachineFunction &MF) { - assert((MF.getTarget().getRelocationModel() != Reloc::Default || - MF.getTarget().getRelocationModel() != Reloc::Static) && - "JIT relocation model must be set to static or default!"); - II = ((X86TargetMachine&)MF.getTarget()).getInstrInfo(); - TD = ((X86TargetMachine&)MF.getTarget()).getTargetData(); - Is64BitMode = - ((X86TargetMachine&)MF.getTarget()).getSubtarget().is64Bit(); - +template +bool Emitter::runOnMachineFunction(MachineFunction &MF) { + + MCE.setModuleInfo(&getAnalysis()); + + II = TM.getInstrInfo(); + TD = TM.getTargetData(); + Is64BitMode = TM.getSubtarget().is64Bit(); + IsPIC = TM.getRelocationModel() == Reloc::PIC_; + do { + DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n"; MCE.startFunction(MF); for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); MBB != E; ++MBB) { MCE.StartMachineBasicBlock(MBB); for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end(); - I != E; ++I) - emitInstruction(*I); + I != E; ++I) { + const TargetInstrDesc &Desc = I->getDesc(); + emitInstruction(*I, &Desc); + // MOVPC32r is basically a call plus a pop instruction. + if (Desc.getOpcode() == X86::MOVPC32r) + emitInstruction(*I, &II->get(X86::POP32r)); + NumEmitted++; // Keep track of the # of mi's emitted + } } } while (MCE.finishFunction(MF)); return false; } -/// emitPCRelativeValue - Emit a PC relative address. -/// -void Emitter::emitPCRelativeValue(intptr_t Address) { - MCE.emitWordLE(Address-MCE.getCurrentPCValue()-4); -} - /// emitPCRelativeBlockAddress - This method keeps track of the information /// necessary to resolve the address of this block later and emits a dummy /// value. /// -void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) { +template +void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) { // Remember where this reference was and where it is to so we can // deal with it later. MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), @@ -133,127 +165,92 @@ void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) { MCE.emitWordLE(0); } -/// emitGlobalAddressForCall - Emit the specified address to the code stream -/// assuming this is part of a function call, which is PC relative. -/// -void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub) { - MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), - X86::reloc_pcrel_word, GV, 0, - DoesntNeedStub)); - MCE.emitWordLE(0); -} - /// emitGlobalAddress - Emit the specified address to the code stream assuming /// this is part of a "take the address of a global" instruction. /// -void Emitter::emitGlobalAddressForPtr(GlobalValue *GV, unsigned Reloc, - int Disp /* = 0 */, - unsigned PCAdj /* = 0 */) { - MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, - GV, PCAdj)); +template +void Emitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc, + intptr_t Disp /* = 0 */, + intptr_t PCAdj /* = 0 */, + bool NeedStub /* = false */, + bool Indirect /* = false */) { + intptr_t RelocCST = 0; + if (Reloc == X86::reloc_picrel_word) + RelocCST = PICBaseOffset; + else if (Reloc == X86::reloc_pcrel_word) + RelocCST = PCAdj; + MachineRelocation MR = Indirect + ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc, + GV, RelocCST, NeedStub) + : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, + GV, RelocCST, NeedStub); + MCE.addRelocation(MR); + // The relocated value will be added to the displacement if (Reloc == X86::reloc_absolute_dword) - MCE.emitWordLE(0); - MCE.emitWordLE(Disp); // The relocated value will be added to the displacement + MCE.emitDWordLE(Disp); + else + MCE.emitWordLE((int32_t)Disp); } /// emitExternalSymbolAddress - Arrange for the address of an external symbol to /// be emitted to the current location in the function, and allow it to be PC /// relative. -void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) { +template +void Emitter::emitExternalSymbolAddress(const char *ES, + unsigned Reloc) { + intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0; MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), - Reloc, ES)); + Reloc, ES, RelocCST)); if (Reloc == X86::reloc_absolute_dword) + MCE.emitDWordLE(0); + else MCE.emitWordLE(0); - MCE.emitWordLE(0); } /// emitConstPoolAddress - Arrange for the address of an constant pool /// to be emitted to the current location in the function, and allow it to be PC /// relative. -void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc, - int Disp /* = 0 */, - unsigned PCAdj /* = 0 */) { +template +void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc, + intptr_t Disp /* = 0 */, + intptr_t PCAdj /* = 0 */) { + intptr_t RelocCST = 0; + if (Reloc == X86::reloc_picrel_word) + RelocCST = PICBaseOffset; + else if (Reloc == X86::reloc_pcrel_word) + RelocCST = PCAdj; MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), - Reloc, CPI, PCAdj)); + Reloc, CPI, RelocCST)); + // The relocated value will be added to the displacement if (Reloc == X86::reloc_absolute_dword) - MCE.emitWordLE(0); - MCE.emitWordLE(Disp); // The relocated value will be added to the displacement + MCE.emitDWordLE(Disp); + else + MCE.emitWordLE((int32_t)Disp); } /// emitJumpTableAddress - Arrange for the address of a jump table to /// be emitted to the current location in the function, and allow it to be PC /// relative. -void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc, - unsigned PCAdj /* = 0 */) { +template +void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc, + intptr_t PCAdj /* = 0 */) { + intptr_t RelocCST = 0; + if (Reloc == X86::reloc_picrel_word) + RelocCST = PICBaseOffset; + else if (Reloc == X86::reloc_pcrel_word) + RelocCST = PCAdj; MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), - Reloc, JTI, PCAdj)); + Reloc, JTI, RelocCST)); + // The relocated value will be added to the displacement if (Reloc == X86::reloc_absolute_dword) + MCE.emitDWordLE(0); + else MCE.emitWordLE(0); - MCE.emitWordLE(0); // The relocated value will be added to the displacement } -/// N86 namespace - Native X86 Register numbers... used by X86 backend. -/// -namespace N86 { - enum { - EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 - }; -} - -// getX86RegNum - This function maps LLVM register identifiers to their X86 -// specific numbering, which is used in various places encoding instructions. -// -unsigned Emitter::getX86RegNum(unsigned RegNo) { - switch(RegNo) { - case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX; - case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX; - case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX; - case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX; - case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH: - return N86::ESP; - case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH: - return N86::EBP; - case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH: - return N86::ESI; - case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH: - return N86::EDI; - - case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: - return N86::EAX; - case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B: - return N86::ECX; - case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: - return N86::EDX; - case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B: - return N86::EBX; - case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B: - return N86::ESP; - case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B: - return N86::EBP; - case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B: - return N86::ESI; - case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B: - return N86::EDI; - - case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3: - case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7: - return RegNo-X86::ST0; - - case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3: - case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: - return II->getRegisterInfo().getDwarfRegNum(RegNo) - - II->getRegisterInfo().getDwarfRegNum(X86::XMM0); - case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: - case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: - return II->getRegisterInfo().getDwarfRegNum(RegNo) - - II->getRegisterInfo().getDwarfRegNum(X86::XMM8); - - default: - assert(MRegisterInfo::isVirtualRegister(RegNo) && - "Unknown physical register!"); - assert(0 && "Register allocator hasn't allocated reg correctly yet!"); - return 0; - } +template +unsigned Emitter::getX86RegNum(unsigned RegNo) const { + return II->getRegisterInfo().getX86RegNum(RegNo); } inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode, @@ -262,16 +259,27 @@ inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode, return RM | (RegOpcode << 3) | (Mod << 6); } -void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){ +template +void Emitter::emitRegModRMByte(unsigned ModRMReg, + unsigned RegOpcodeFld){ MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg))); } -void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) { +template +void Emitter::emitRegModRMByte(unsigned RegOpcodeFld) { + MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0)); +} + +template +void Emitter::emitSIBByte(unsigned SS, + unsigned Index, + unsigned Base) { // SIB byte is in the same format as the ModRMByte... MCE.emitByte(ModRMByte(SS, Index, Base)); } -void Emitter::emitConstant(uint64_t Val, unsigned Size) { +template +void Emitter::emitConstant(uint64_t Val, unsigned Size) { // Output the constant in little endian byte order... for (unsigned i = 0; i != Size; ++i) { MCE.emitByte(Val & 255); @@ -285,8 +293,17 @@ static bool isDisp8(int Value) { return Value == (signed char)Value; } -void Emitter::emitDisplacementField(const MachineOperand *RelocOp, - int DispVal, unsigned PCAdj) { +template +bool Emitter::gvNeedsNonLazyPtr(const GlobalValue *GV) { + // For Darwin, simulate the linktime GOT by using the same non-lazy-pointer + // mechanism as 32-bit mode. + return (!Is64BitMode || TM.getSubtarget().isTargetDarwin()) && + TM.getSubtarget().GVRequiresExtraLoad(GV, TM, false); +} + +template +void Emitter::emitDisplacementField(const MachineOperand *RelocOp, + int DispVal, intptr_t PCAdj) { // If this is a simple integer displacement that doesn't require a relocation, // emit it now. if (!RelocOp) { @@ -296,49 +313,52 @@ void Emitter::emitDisplacementField(const MachineOperand *RelocOp, // Otherwise, this is something that requires a relocation. Emit it as such // now. - if (RelocOp->isGlobalAddress()) { + if (RelocOp->isGlobal()) { // In 64-bit static small code model, we could potentially emit absolute. // But it's probably not beneficial. - // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative - // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute - unsigned rt= Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_absolute_word; - emitGlobalAddressForPtr(RelocOp->getGlobal(), rt, - RelocOp->getOffset(), PCAdj); - } else if (RelocOp->isConstantPoolIndex()) { - // Must be in 64-bit mode. - emitConstPoolAddress(RelocOp->getConstantPoolIndex(), X86::reloc_pcrel_word, + // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative + // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute + unsigned rt = Is64BitMode ? X86::reloc_pcrel_word + : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); + bool NeedStub = isa(RelocOp->getGlobal()); + bool Indirect = gvNeedsNonLazyPtr(RelocOp->getGlobal()); + emitGlobalAddress(RelocOp->getGlobal(), rt, RelocOp->getOffset(), + PCAdj, NeedStub, Indirect); + } else if (RelocOp->isCPI()) { + unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word; + emitConstPoolAddress(RelocOp->getIndex(), rt, RelocOp->getOffset(), PCAdj); - } else if (RelocOp->isJumpTableIndex()) { - // Must be in 64-bit mode. - emitJumpTableAddress(RelocOp->getJumpTableIndex(), X86::reloc_pcrel_word, - PCAdj); + } else if (RelocOp->isJTI()) { + unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word; + emitJumpTableAddress(RelocOp->getIndex(), rt, PCAdj); } else { assert(0 && "Unknown value to relocate!"); } } -void Emitter::emitMemModRMByte(const MachineInstr &MI, +template +void Emitter::emitMemModRMByte(const MachineInstr &MI, unsigned Op, unsigned RegOpcodeField, - unsigned PCAdj) { + intptr_t PCAdj) { const MachineOperand &Op3 = MI.getOperand(Op+3); int DispVal = 0; const MachineOperand *DispForReloc = 0; // Figure out what sort of displacement we have to handle here. - if (Op3.isGlobalAddress()) { + if (Op3.isGlobal()) { DispForReloc = &Op3; - } else if (Op3.isConstantPoolIndex()) { - if (Is64BitMode) { + } else if (Op3.isCPI()) { + if (Is64BitMode || IsPIC) { DispForReloc = &Op3; } else { - DispVal += MCE.getConstantPoolEntryAddress(Op3.getConstantPoolIndex()); + DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex()); DispVal += Op3.getOffset(); } - } else if (Op3.isJumpTableIndex()) { - if (Is64BitMode) { + } else if (Op3.isJTI()) { + if (Is64BitMode || IsPIC) { DispForReloc = &Op3; } else { - DispVal += MCE.getJumpTableEntryAddress(Op3.getJumpTableIndex()); + DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex()); } } else { DispVal = Op3.getImm(); @@ -351,9 +371,12 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI, unsigned BaseReg = Base.getReg(); // Is a SIB byte needed? - if (IndexReg.getReg() == 0 && - (BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) { - if (BaseReg == 0) { // Just a displacement? + if ((!Is64BitMode || DispForReloc || BaseReg != 0) && + IndexReg.getReg() == 0 && + (BaseReg == 0 || BaseReg == X86::RIP || + getX86RegNum(BaseReg) != N86::ESP)) { + if (BaseReg == 0 || + BaseReg == X86::RIP) { // Just a displacement? // Emit special case [disp32] encoding MCE.emitByte(ModRMByte(0, RegOpcodeField, 5)); @@ -408,8 +431,12 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI, if (BaseReg == 0) { // Handle the SIB byte for the case where there is no base. The // displacement has already been output. - assert(IndexReg.getReg() && "Index register must be specified!"); - emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5); + unsigned IndexRegNo; + if (IndexReg.getReg()) + IndexRegNo = getX86RegNum(IndexReg.getReg()); + else + IndexRegNo = 4; // For example [ESP+1*+4] + emitSIBByte(SS, IndexRegNo, 5); } else { unsigned BaseRegNo = getX86RegNum(BaseReg); unsigned IndexRegNo; @@ -429,150 +456,28 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI, } } -static unsigned sizeOfImm(const TargetInstrDescriptor *Desc) { - switch (Desc->TSFlags & X86II::ImmMask) { - case X86II::Imm8: return 1; - case X86II::Imm16: return 2; - case X86II::Imm32: return 4; - case X86II::Imm64: return 8; - default: assert(0 && "Immediate size not set!"); - return 0; - } -} - -/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register? -/// e.g. r8, xmm8, etc. -bool Emitter::isX86_64ExtendedReg(const MachineOperand &MO) { - if (!MO.isRegister()) return false; - unsigned RegNo = MO.getReg(); - int DWNum = II->getRegisterInfo().getDwarfRegNum(RegNo); - if (DWNum >= II->getRegisterInfo().getDwarfRegNum(X86::R8) && - DWNum <= II->getRegisterInfo().getDwarfRegNum(X86::R15)) - return true; - if (DWNum >= II->getRegisterInfo().getDwarfRegNum(X86::XMM8) && - DWNum <= II->getRegisterInfo().getDwarfRegNum(X86::XMM15)) - return true; - return false; -} - -inline static bool isX86_64TruncToByte(unsigned oc) { - return (oc == X86::TRUNC_64to8 || oc == X86::TRUNC_32to8 || - oc == X86::TRUNC_16to8); -} - +template +void Emitter::emitInstruction( + const MachineInstr &MI, + const TargetInstrDesc *Desc) { + DOUT << MI; -inline static bool isX86_64NonExtLowByteReg(unsigned reg) { - return (reg == X86::SPL || reg == X86::BPL || - reg == X86::SIL || reg == X86::DIL); -} - -/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64 -/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand -/// size, and 3) use of X86-64 extended registers. -unsigned Emitter::determineREX(const MachineInstr &MI) { - unsigned REX = 0; - const TargetInstrDescriptor *Desc = MI.getInstrDescriptor(); unsigned Opcode = Desc->Opcode; - // Pseudo instructions do not need REX prefix byte. - if ((Desc->TSFlags & X86II::FormMask) == X86II::Pseudo) - return 0; - if (Desc->TSFlags & X86II::REX_W) - REX |= 1 << 3; - - unsigned NumOps = Desc->numOperands; - if (NumOps) { - bool isTwoAddr = NumOps > 1 && - Desc->getOperandConstraint(1, TOI::TIED_TO) != -1; - - // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. - bool isTrunc8 = isX86_64TruncToByte(Opcode); - unsigned i = isTwoAddr ? 1 : 0; - for (unsigned e = NumOps; i != e; ++i) { - const MachineOperand& MO = MI.getOperand(i); - if (MO.isRegister()) { - unsigned Reg = MO.getReg(); - // Trunc to byte are actually movb. The real source operand is the low - // byte of the register. - if (isTrunc8 && i == 1) - Reg = getX86SubSuperRegister(Reg, MVT::i8); - if (isX86_64NonExtLowByteReg(Reg)) - REX |= 0x40; - } - } + // Emit the lock opcode prefix as needed. + if (Desc->TSFlags & X86II::LOCK) MCE.emitByte(0xF0); - switch (Desc->TSFlags & X86II::FormMask) { - case X86II::MRMInitReg: - if (isX86_64ExtendedReg(MI.getOperand(0))) - REX |= (1 << 0) | (1 << 2); - break; - case X86II::MRMSrcReg: { - if (isX86_64ExtendedReg(MI.getOperand(0))) - REX |= 1 << 2; - i = isTwoAddr ? 2 : 1; - for (unsigned e = NumOps; i != e; ++i) { - const MachineOperand& MO = MI.getOperand(i); - if (isX86_64ExtendedReg(MO)) - REX |= 1 << 0; - } - break; - } - case X86II::MRMSrcMem: { - if (isX86_64ExtendedReg(MI.getOperand(0))) - REX |= 1 << 2; - unsigned Bit = 0; - i = isTwoAddr ? 2 : 1; - for (; i != NumOps; ++i) { - const MachineOperand& MO = MI.getOperand(i); - if (MO.isRegister()) { - if (isX86_64ExtendedReg(MO)) - REX |= 1 << Bit; - Bit++; - } - } - break; - } - case X86II::MRM0m: case X86II::MRM1m: - case X86II::MRM2m: case X86II::MRM3m: - case X86II::MRM4m: case X86II::MRM5m: - case X86II::MRM6m: case X86II::MRM7m: - case X86II::MRMDestMem: { - unsigned e = isTwoAddr ? 5 : 4; - i = isTwoAddr ? 1 : 0; - if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e))) - REX |= 1 << 2; - unsigned Bit = 0; - for (; i != e; ++i) { - const MachineOperand& MO = MI.getOperand(i); - if (MO.isRegister()) { - if (isX86_64ExtendedReg(MO)) - REX |= 1 << Bit; - Bit++; - } - } - break; - } - default: { - if (isX86_64ExtendedReg(MI.getOperand(0))) - REX |= 1 << 0; - i = isTwoAddr ? 2 : 1; - for (unsigned e = NumOps; i != e; ++i) { - const MachineOperand& MO = MI.getOperand(i); - if (isX86_64ExtendedReg(MO)) - REX |= 1 << 2; - } - break; - } - } + // Emit segment override opcode prefix as needed. + switch (Desc->TSFlags & X86II::SegOvrMask) { + case X86II::FS: + MCE.emitByte(0x64); + break; + case X86II::GS: + MCE.emitByte(0x65); + break; + default: assert(0 && "Invalid segment!"); + case 0: break; // No segment override! } - return REX; -} - -void Emitter::emitInstruction(const MachineInstr &MI) { - NumEmitted++; // Keep track of the # of mi's emitted - - const TargetInstrDescriptor *Desc = MI.getInstrDescriptor(); - unsigned Opcode = Desc->Opcode; // Emit the repeat opcode prefix as needed. if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3); @@ -585,16 +490,10 @@ void Emitter::emitInstruction(const MachineInstr &MI) { bool Need0FPrefix = false; switch (Desc->TSFlags & X86II::Op0Mask) { - case X86II::TB: - Need0FPrefix = true; // Two-byte opcode prefix - break; - case X86II::T8: - MCE.emitByte(0x0F); - MCE.emitByte(0x38); - break; - case X86II::TA: - MCE.emitByte(0x0F); - MCE.emitByte(0x3A); + case X86II::TB: // Two-byte opcode prefix + case X86II::T8: // 0F 38 + case X86II::TA: // 0F 3A + Need0FPrefix = true; break; case X86II::REP: break; // already handled. case X86II::XS: // F3 0F @@ -617,7 +516,7 @@ void Emitter::emitInstruction(const MachineInstr &MI) { if (Is64BitMode) { // REX prefix - unsigned REX = determineREX(MI); + unsigned REX = X86InstrInfo::determineREX(MI); if (REX) MCE.emitByte(0x40 | REX); } @@ -626,56 +525,97 @@ void Emitter::emitInstruction(const MachineInstr &MI) { if (Need0FPrefix) MCE.emitByte(0x0F); + switch (Desc->TSFlags & X86II::Op0Mask) { + case X86II::T8: // 0F 38 + MCE.emitByte(0x38); + break; + case X86II::TA: // 0F 3A + MCE.emitByte(0x3A); + break; + } + // If this is a two-address instruction, skip one of the register operands. - unsigned NumOps = Desc->numOperands; + unsigned NumOps = Desc->getNumOperands(); unsigned CurOp = 0; if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1) - CurOp++; + ++CurOp; + else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0) + // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32 + --NumOps; unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc); switch (Desc->TSFlags & X86II::FormMask) { default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!"); case X86II::Pseudo: -#ifndef NDEBUG + // Remember the current PC offset, this is the PIC relocation + // base address. switch (Opcode) { default: assert(0 && "psuedo instructions should be removed before code emission"); - case TargetInstrInfo::INLINEASM: - assert(0 && "JIT does not support inline asm!\n"); - case TargetInstrInfo::LABEL: - assert(0 && "JIT does not support meta labels!\n"); - case X86::IMPLICIT_USE: - case X86::IMPLICIT_DEF: - case X86::IMPLICIT_DEF_GR8: - case X86::IMPLICIT_DEF_GR16: - case X86::IMPLICIT_DEF_GR32: - case X86::IMPLICIT_DEF_GR64: - case X86::IMPLICIT_DEF_FR32: - case X86::IMPLICIT_DEF_FR64: - case X86::IMPLICIT_DEF_VR64: - case X86::IMPLICIT_DEF_VR128: + break; + case TargetInstrInfo::INLINEASM: { + // We allow inline assembler nodes with empty bodies - they can + // implicitly define registers, which is ok for JIT. + if (MI.getOperand(0).getSymbolName()[0]) { + llvm_report_error("JIT does not support inline asm!"); + } + break; + } + case TargetInstrInfo::DBG_LABEL: + case TargetInstrInfo::EH_LABEL: + MCE.emitLabel(MI.getOperand(0).getImm()); + break; + case TargetInstrInfo::IMPLICIT_DEF: + case TargetInstrInfo::DECLARE: + case X86::DWARF_LOC: case X86::FP_REG_KILL: break; + case X86::MOVPC32r: { + // This emits the "call" portion of this pseudo instruction. + MCE.emitByte(BaseOpcode); + emitConstant(0, X86InstrInfo::sizeOfImm(Desc)); + // Remember PIC base. + PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset(); + X86JITInfo *JTI = TM.getJITInfo(); + JTI->setPICBase(MCE.getCurrentPCValue()); + break; + } } -#endif CurOp = NumOps; break; - case X86II::RawFrm: MCE.emitByte(BaseOpcode); + if (CurOp != NumOps) { const MachineOperand &MO = MI.getOperand(CurOp++); - if (MO.isMachineBasicBlock()) { - emitPCRelativeBlockAddress(MO.getMachineBasicBlock()); - } else if (MO.isGlobalAddress()) { - bool NeedStub = Is64BitMode || - Opcode == X86::TAILJMPd || - Opcode == X86::TAILJMPr || Opcode == X86::TAILJMPm; - emitGlobalAddressForCall(MO.getGlobal(), !NeedStub); - } else if (MO.isExternalSymbol()) { + + DOUT << "RawFrm CurOp " << CurOp << "\n"; + DOUT << "isMBB " << MO.isMBB() << "\n"; + DOUT << "isGlobal " << MO.isGlobal() << "\n"; + DOUT << "isSymbol " << MO.isSymbol() << "\n"; + DOUT << "isImm " << MO.isImm() << "\n"; + + if (MO.isMBB()) { + emitPCRelativeBlockAddress(MO.getMBB()); + } else if (MO.isGlobal()) { + // Assume undefined functions may be outside the Small codespace. + bool NeedStub = + (Is64BitMode && + (TM.getCodeModel() == CodeModel::Large || + TM.getSubtarget().isTargetDarwin())) || + Opcode == X86::TAILJMPd; + emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word, + MO.getOffset(), 0, NeedStub); + } else if (MO.isSymbol()) { emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word); - } else if (MO.isImmediate()) { - emitConstant(MO.getImm(), sizeOfImm(Desc)); + } else if (MO.isImm()) { + if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) { + // Fix up immediate operand for pc relative calls. + intptr_t Imm = (intptr_t)MO.getImm(); + Imm = Imm - MCE.getCurrentPCValue() - 4; + emitConstant(Imm, X86InstrInfo::sizeOfImm(Desc)); + } else + emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc)); } else { assert(0 && "Unknown RawFrm operand!"); } @@ -687,21 +627,26 @@ void Emitter::emitInstruction(const MachineInstr &MI) { if (CurOp != NumOps) { const MachineOperand &MO1 = MI.getOperand(CurOp++); - unsigned Size = sizeOfImm(Desc); - if (MO1.isImmediate()) + unsigned Size = X86InstrInfo::sizeOfImm(Desc); + if (MO1.isImm()) emitConstant(MO1.getImm(), Size); else { - unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_absolute_word; + unsigned rt = Is64BitMode ? X86::reloc_pcrel_word + : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); + // This should not occur on Darwin for relocatable objects. if (Opcode == X86::MOV64ri) rt = X86::reloc_absolute_dword; // FIXME: add X86II flag? - if (MO1.isGlobalAddress()) - emitGlobalAddressForPtr(MO1.getGlobal(), rt, MO1.getOffset()); - else if (MO1.isExternalSymbol()) + if (MO1.isGlobal()) { + bool NeedStub = isa(MO1.getGlobal()); + bool Indirect = gvNeedsNonLazyPtr(MO1.getGlobal()); + emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0, + NeedStub, Indirect); + } else if (MO1.isSymbol()) emitExternalSymbolAddress(MO1.getSymbolName(), rt); - else if (MO1.isConstantPoolIndex()) - emitConstPoolAddress(MO1.getConstantPoolIndex(), rt); - else if (MO1.isJumpTableIndex()) - emitJumpTableAddress(MO1.getJumpTableIndex(), rt); + else if (MO1.isCPI()) + emitConstPoolAddress(MO1.getIndex(), rt); + else if (MO1.isJTI()) + emitJumpTableAddress(MO1.getIndex(), rt); } } break; @@ -712,15 +657,17 @@ void Emitter::emitInstruction(const MachineInstr &MI) { getX86RegNum(MI.getOperand(CurOp+1).getReg())); CurOp += 2; if (CurOp != NumOps) - emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc)); + emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc)); break; } case X86II::MRMDestMem: { MCE.emitByte(BaseOpcode); - emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(CurOp+4).getReg())); - CurOp += 5; + emitMemModRMByte(MI, CurOp, + getX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands) + .getReg())); + CurOp += X86AddrNumOperands + 1; if (CurOp != NumOps) - emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc)); + emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc)); break; } @@ -730,81 +677,119 @@ void Emitter::emitInstruction(const MachineInstr &MI) { getX86RegNum(MI.getOperand(CurOp).getReg())); CurOp += 2; if (CurOp != NumOps) - emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc)); + emitConstant(MI.getOperand(CurOp++).getImm(), + X86InstrInfo::sizeOfImm(Desc)); break; case X86II::MRMSrcMem: { - unsigned PCAdj = (CurOp+5 != NumOps) ? sizeOfImm(Desc) : 0; + // FIXME: Maybe lea should have its own form? + int AddrOperands; + if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r || + Opcode == X86::LEA16r || Opcode == X86::LEA32r) + AddrOperands = X86AddrNumOperands - 1; // No segment register + else + AddrOperands = X86AddrNumOperands; + + intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ? + X86InstrInfo::sizeOfImm(Desc) : 0; MCE.emitByte(BaseOpcode); emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()), PCAdj); - CurOp += 5; + CurOp += AddrOperands + 1; if (CurOp != NumOps) - emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc)); + emitConstant(MI.getOperand(CurOp++).getImm(), + X86InstrInfo::sizeOfImm(Desc)); break; } case X86II::MRM0r: case X86II::MRM1r: case X86II::MRM2r: case X86II::MRM3r: case X86II::MRM4r: case X86II::MRM5r: - case X86II::MRM6r: case X86II::MRM7r: + case X86II::MRM6r: case X86II::MRM7r: { MCE.emitByte(BaseOpcode); - emitRegModRMByte(MI.getOperand(CurOp++).getReg(), - (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r); + + // Special handling of lfence, mfence, monitor, and mwait. + if (Desc->getOpcode() == X86::LFENCE || + Desc->getOpcode() == X86::MFENCE || + Desc->getOpcode() == X86::MONITOR || + Desc->getOpcode() == X86::MWAIT) { + emitRegModRMByte((Desc->TSFlags & X86II::FormMask)-X86II::MRM0r); + + switch (Desc->getOpcode()) { + default: break; + case X86::MONITOR: + MCE.emitByte(0xC8); + break; + case X86::MWAIT: + MCE.emitByte(0xC9); + break; + } + } else { + emitRegModRMByte(MI.getOperand(CurOp++).getReg(), + (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r); + } if (CurOp != NumOps) { const MachineOperand &MO1 = MI.getOperand(CurOp++); - unsigned Size = sizeOfImm(Desc); - if (MO1.isImmediate()) + unsigned Size = X86InstrInfo::sizeOfImm(Desc); + if (MO1.isImm()) emitConstant(MO1.getImm(), Size); else { unsigned rt = Is64BitMode ? X86::reloc_pcrel_word - : X86::reloc_absolute_word; + : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); if (Opcode == X86::MOV64ri32) rt = X86::reloc_absolute_word; // FIXME: add X86II flag? - if (MO1.isGlobalAddress()) - emitGlobalAddressForPtr(MO1.getGlobal(), rt, MO1.getOffset()); - else if (MO1.isExternalSymbol()) + if (MO1.isGlobal()) { + bool NeedStub = isa(MO1.getGlobal()); + bool Indirect = gvNeedsNonLazyPtr(MO1.getGlobal()); + emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0, + NeedStub, Indirect); + } else if (MO1.isSymbol()) emitExternalSymbolAddress(MO1.getSymbolName(), rt); - else if (MO1.isConstantPoolIndex()) - emitConstPoolAddress(MO1.getConstantPoolIndex(), rt); - else if (MO1.isJumpTableIndex()) - emitJumpTableAddress(MO1.getJumpTableIndex(), rt); + else if (MO1.isCPI()) + emitConstPoolAddress(MO1.getIndex(), rt); + else if (MO1.isJTI()) + emitJumpTableAddress(MO1.getIndex(), rt); } } break; + } case X86II::MRM0m: case X86II::MRM1m: case X86II::MRM2m: case X86II::MRM3m: case X86II::MRM4m: case X86II::MRM5m: case X86II::MRM6m: case X86II::MRM7m: { - unsigned PCAdj = (CurOp+4 != NumOps) ? - (MI.getOperand(CurOp+4).isImmediate() ? sizeOfImm(Desc) : 4) : 0; + intptr_t PCAdj = (CurOp + X86AddrNumOperands != NumOps) ? + (MI.getOperand(CurOp+X86AddrNumOperands).isImm() ? + X86InstrInfo::sizeOfImm(Desc) : 4) : 0; MCE.emitByte(BaseOpcode); emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m, PCAdj); - CurOp += 4; + CurOp += X86AddrNumOperands; if (CurOp != NumOps) { const MachineOperand &MO = MI.getOperand(CurOp++); - unsigned Size = sizeOfImm(Desc); - if (MO.isImmediate()) + unsigned Size = X86InstrInfo::sizeOfImm(Desc); + if (MO.isImm()) emitConstant(MO.getImm(), Size); else { unsigned rt = Is64BitMode ? X86::reloc_pcrel_word - : X86::reloc_absolute_word; + : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); if (Opcode == X86::MOV64mi32) rt = X86::reloc_absolute_word; // FIXME: add X86II flag? - if (MO.isGlobalAddress()) - emitGlobalAddressForPtr(MO.getGlobal(), rt, MO.getOffset()); - else if (MO.isExternalSymbol()) + if (MO.isGlobal()) { + bool NeedStub = isa(MO.getGlobal()); + bool Indirect = gvNeedsNonLazyPtr(MO.getGlobal()); + emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0, + NeedStub, Indirect); + } else if (MO.isSymbol()) emitExternalSymbolAddress(MO.getSymbolName(), rt); - else if (MO.isConstantPoolIndex()) - emitConstPoolAddress(MO.getConstantPoolIndex(), rt); - else if (MO.isJumpTableIndex()) - emitJumpTableAddress(MO.getJumpTableIndex(), rt); + else if (MO.isCPI()) + emitConstPoolAddress(MO.getIndex(), rt); + else if (MO.isJTI()) + emitJumpTableAddress(MO.getIndex(), rt); } } break; @@ -819,6 +804,11 @@ void Emitter::emitInstruction(const MachineInstr &MI) { break; } - assert((Desc->Flags & M_VARIABLE_OPS) != 0 || - CurOp == NumOps && "Unknown encoding!"); + if (!Desc->isVariadic() && CurOp != NumOps) { +#ifndef NDEBUG + cerr << "Cannot encode: " << MI << "\n"; +#endif + llvm_unreachable(); + } } +