X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86CodeEmitter.cpp;h=bbe063b4f821efb2b4b6ce8b150907c122e5c7e2;hb=92722533819ab838d958966d0e40a60030bb3c16;hp=e6cd4123413362aa1508e580b3c583de20b34869;hpb=d18330763965745fea05536939f5aadffcc6a5a6;p=oota-llvm.git diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index e6cd4123413..bbe063b4f82 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -38,20 +38,20 @@ namespace { class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass { const X86InstrInfo *II; const TargetData *TD; - TargetMachine &TM; + X86TargetMachine &TM; MachineCodeEmitter &MCE; intptr_t PICBaseOffset; bool Is64BitMode; bool IsPIC; public: static char ID; - explicit Emitter(TargetMachine &tm, MachineCodeEmitter &mce) - : MachineFunctionPass((intptr_t)&ID), II(0), TD(0), TM(tm), + explicit Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce) + : MachineFunctionPass(&ID), II(0), TD(0), TM(tm), MCE(mce), PICBaseOffset(0), Is64BitMode(false), IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} - Emitter(TargetMachine &tm, MachineCodeEmitter &mce, + Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce, const X86InstrInfo &ii, const TargetData &td, bool is64) - : MachineFunctionPass((intptr_t)&ID), II(&ii), TD(&td), TM(tm), + : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm), MCE(mce), PICBaseOffset(0), Is64BitMode(is64), IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} @@ -72,10 +72,10 @@ namespace { private: void emitPCRelativeBlockAddress(MachineBasicBlock *MBB); void emitGlobalAddress(GlobalValue *GV, unsigned Reloc, - int Disp = 0, intptr_t PCAdj = 0, - bool NeedStub = false, bool IsLazy = false); + intptr_t Disp = 0, intptr_t PCAdj = 0, + bool NeedStub = false, bool Indirect = false); void emitExternalSymbolAddress(const char *ES, unsigned Reloc); - void emitConstPoolAddress(unsigned CPI, unsigned Reloc, int Disp = 0, + void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0, intptr_t PCAdj = 0); void emitJumpTableAddress(unsigned JTI, unsigned Reloc, intptr_t PCAdj = 0); @@ -84,6 +84,7 @@ namespace { intptr_t PCAdj = 0); void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField); + void emitRegModRMByte(unsigned RegOpcodeField); void emitSIBByte(unsigned SS, unsigned Index, unsigned Base); void emitConstant(uint64_t Val, unsigned Size); @@ -92,10 +93,8 @@ namespace { intptr_t PCAdj = 0); unsigned getX86RegNum(unsigned RegNo) const; - bool isX86_64ExtendedReg(const MachineOperand &MO); - unsigned determineREX(const MachineInstr &MI); - bool gvNeedsLazyPtr(const GlobalValue *GV); + bool gvNeedsNonLazyPtr(const GlobalValue *GV); }; char Emitter::ID = 0; } @@ -108,15 +107,13 @@ FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM, } bool Emitter::runOnMachineFunction(MachineFunction &MF) { - assert((MF.getTarget().getRelocationModel() != Reloc::Default || - MF.getTarget().getRelocationModel() != Reloc::Static) && - "JIT relocation model must be set to static or default!"); - + MCE.setModuleInfo(&getAnalysis()); - II = ((X86TargetMachine&)TM).getInstrInfo(); - TD = ((X86TargetMachine&)TM).getTargetData(); + II = TM.getInstrInfo(); + TD = TM.getTargetData(); Is64BitMode = TM.getSubtarget().is64Bit(); + IsPIC = TM.getRelocationModel() == Reloc::PIC_; do { DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n"; @@ -155,23 +152,26 @@ void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) { /// this is part of a "take the address of a global" instruction. /// void Emitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc, - int Disp /* = 0 */, intptr_t PCAdj /* = 0 */, + intptr_t Disp /* = 0 */, + intptr_t PCAdj /* = 0 */, bool NeedStub /* = false */, - bool isLazy /* = false */) { + bool Indirect /* = false */) { intptr_t RelocCST = 0; if (Reloc == X86::reloc_picrel_word) RelocCST = PICBaseOffset; else if (Reloc == X86::reloc_pcrel_word) RelocCST = PCAdj; - MachineRelocation MR = isLazy - ? MachineRelocation::getGVLazyPtr(MCE.getCurrentPCOffset(), Reloc, - GV, RelocCST, NeedStub) + MachineRelocation MR = Indirect + ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc, + GV, RelocCST, NeedStub) : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, GV, RelocCST, NeedStub); MCE.addRelocation(MR); + // The relocated value will be added to the displacement if (Reloc == X86::reloc_absolute_dword) - MCE.emitWordLE(0); - MCE.emitWordLE(Disp); // The relocated value will be added to the displacement + MCE.emitDWordLE(Disp); + else + MCE.emitWordLE((int32_t)Disp); } /// emitExternalSymbolAddress - Arrange for the address of an external symbol to @@ -182,15 +182,16 @@ void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) { MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), Reloc, ES, RelocCST)); if (Reloc == X86::reloc_absolute_dword) + MCE.emitDWordLE(0); + else MCE.emitWordLE(0); - MCE.emitWordLE(0); } /// emitConstPoolAddress - Arrange for the address of an constant pool /// to be emitted to the current location in the function, and allow it to be PC /// relative. void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc, - int Disp /* = 0 */, + intptr_t Disp /* = 0 */, intptr_t PCAdj /* = 0 */) { intptr_t RelocCST = 0; if (Reloc == X86::reloc_picrel_word) @@ -199,9 +200,11 @@ void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc, RelocCST = PCAdj; MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), Reloc, CPI, RelocCST)); + // The relocated value will be added to the displacement if (Reloc == X86::reloc_absolute_dword) - MCE.emitWordLE(0); - MCE.emitWordLE(Disp); // The relocated value will be added to the displacement + MCE.emitDWordLE(Disp); + else + MCE.emitWordLE((int32_t)Disp); } /// emitJumpTableAddress - Arrange for the address of a jump table to @@ -216,13 +219,15 @@ void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc, RelocCST = PCAdj; MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), Reloc, JTI, RelocCST)); + // The relocated value will be added to the displacement if (Reloc == X86::reloc_absolute_dword) + MCE.emitDWordLE(0); + else MCE.emitWordLE(0); - MCE.emitWordLE(0); // The relocated value will be added to the displacement } unsigned Emitter::getX86RegNum(unsigned RegNo) const { - return ((const X86RegisterInfo&)II->getRegisterInfo()).getX86RegNum(RegNo); + return II->getRegisterInfo().getX86RegNum(RegNo); } inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode, @@ -235,6 +240,10 @@ void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){ MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg))); } +void Emitter::emitRegModRMByte(unsigned RegOpcodeFld) { + MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0)); +} + void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) { // SIB byte is in the same format as the ModRMByte... MCE.emitByte(ModRMByte(SS, Index, Base)); @@ -254,8 +263,10 @@ static bool isDisp8(int Value) { return Value == (signed char)Value; } -bool Emitter::gvNeedsLazyPtr(const GlobalValue *GV) { - return !Is64BitMode && +bool Emitter::gvNeedsNonLazyPtr(const GlobalValue *GV) { + // For Darwin, simulate the linktime GOT by using the same non-lazy-pointer + // mechanism as 32-bit mode. + return (!Is64BitMode || TM.getSubtarget().isTargetDarwin()) && TM.getSubtarget().GVRequiresExtraLoad(GV, TM, false); } @@ -270,7 +281,7 @@ void Emitter::emitDisplacementField(const MachineOperand *RelocOp, // Otherwise, this is something that requires a relocation. Emit it as such // now. - if (RelocOp->isGlobalAddress()) { + if (RelocOp->isGlobal()) { // In 64-bit static small code model, we could potentially emit absolute. // But it's probably not beneficial. // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative @@ -278,14 +289,14 @@ void Emitter::emitDisplacementField(const MachineOperand *RelocOp, unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); bool NeedStub = isa(RelocOp->getGlobal()); - bool isLazy = gvNeedsLazyPtr(RelocOp->getGlobal()); + bool Indirect = gvNeedsNonLazyPtr(RelocOp->getGlobal()); emitGlobalAddress(RelocOp->getGlobal(), rt, RelocOp->getOffset(), - PCAdj, NeedStub, isLazy); - } else if (RelocOp->isConstantPoolIndex()) { + PCAdj, NeedStub, Indirect); + } else if (RelocOp->isCPI()) { unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word; emitConstPoolAddress(RelocOp->getIndex(), rt, RelocOp->getOffset(), PCAdj); - } else if (RelocOp->isJumpTableIndex()) { + } else if (RelocOp->isJTI()) { unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word; emitJumpTableAddress(RelocOp->getIndex(), rt, PCAdj); } else { @@ -301,16 +312,16 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI, const MachineOperand *DispForReloc = 0; // Figure out what sort of displacement we have to handle here. - if (Op3.isGlobalAddress()) { + if (Op3.isGlobal()) { DispForReloc = &Op3; - } else if (Op3.isConstantPoolIndex()) { + } else if (Op3.isCPI()) { if (Is64BitMode || IsPIC) { DispForReloc = &Op3; } else { DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex()); DispVal += Op3.getOffset(); } - } else if (Op3.isJumpTableIndex()) { + } else if (Op3.isJTI()) { if (Is64BitMode || IsPIC) { DispForReloc = &Op3; } else { @@ -327,7 +338,7 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI, unsigned BaseReg = Base.getReg(); // Is a SIB byte needed? - if (IndexReg.getReg() == 0 && + if ((!Is64BitMode || DispForReloc) && IndexReg.getReg() == 0 && (BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) { if (BaseReg == 0) { // Just a displacement? // Emit special case [disp32] encoding @@ -384,8 +395,12 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI, if (BaseReg == 0) { // Handle the SIB byte for the case where there is no base. The // displacement has already been output. - assert(IndexReg.getReg() && "Index register must be specified!"); - emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5); + unsigned IndexRegNo; + if (IndexReg.getReg()) + IndexRegNo = getX86RegNum(IndexReg.getReg()); + else + IndexRegNo = 4; // For example [ESP+1*+4] + emitSIBByte(SS, IndexRegNo, 5); } else { unsigned BaseRegNo = getX86RegNum(BaseReg); unsigned IndexRegNo; @@ -405,139 +420,6 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI, } } -static unsigned sizeOfImm(const TargetInstrDesc *Desc) { - switch (Desc->TSFlags & X86II::ImmMask) { - case X86II::Imm8: return 1; - case X86II::Imm16: return 2; - case X86II::Imm32: return 4; - case X86II::Imm64: return 8; - default: assert(0 && "Immediate size not set!"); - return 0; - } -} - -/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register? -/// e.g. r8, xmm8, etc. -bool Emitter::isX86_64ExtendedReg(const MachineOperand &MO) { - if (!MO.isRegister()) return false; - switch (MO.getReg()) { - default: break; - case X86::R8: case X86::R9: case X86::R10: case X86::R11: - case X86::R12: case X86::R13: case X86::R14: case X86::R15: - case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: - case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: - case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: - case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: - case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: - case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: - case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: - case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: - return true; - } - return false; -} - -inline static bool isX86_64NonExtLowByteReg(unsigned reg) { - return (reg == X86::SPL || reg == X86::BPL || - reg == X86::SIL || reg == X86::DIL); -} - -/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64 -/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand -/// size, and 3) use of X86-64 extended registers. -unsigned Emitter::determineREX(const MachineInstr &MI) { - unsigned REX = 0; - const TargetInstrDesc &Desc = MI.getDesc(); - - // Pseudo instructions do not need REX prefix byte. - if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo) - return 0; - if (Desc.TSFlags & X86II::REX_W) - REX |= 1 << 3; - - unsigned NumOps = Desc.getNumOperands(); - if (NumOps) { - bool isTwoAddr = NumOps > 1 && - Desc.getOperandConstraint(1, TOI::TIED_TO) != -1; - - // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. - unsigned i = isTwoAddr ? 1 : 0; - for (unsigned e = NumOps; i != e; ++i) { - const MachineOperand& MO = MI.getOperand(i); - if (MO.isRegister()) { - unsigned Reg = MO.getReg(); - if (isX86_64NonExtLowByteReg(Reg)) - REX |= 0x40; - } - } - - switch (Desc.TSFlags & X86II::FormMask) { - case X86II::MRMInitReg: - if (isX86_64ExtendedReg(MI.getOperand(0))) - REX |= (1 << 0) | (1 << 2); - break; - case X86II::MRMSrcReg: { - if (isX86_64ExtendedReg(MI.getOperand(0))) - REX |= 1 << 2; - i = isTwoAddr ? 2 : 1; - for (unsigned e = NumOps; i != e; ++i) { - const MachineOperand& MO = MI.getOperand(i); - if (isX86_64ExtendedReg(MO)) - REX |= 1 << 0; - } - break; - } - case X86II::MRMSrcMem: { - if (isX86_64ExtendedReg(MI.getOperand(0))) - REX |= 1 << 2; - unsigned Bit = 0; - i = isTwoAddr ? 2 : 1; - for (; i != NumOps; ++i) { - const MachineOperand& MO = MI.getOperand(i); - if (MO.isRegister()) { - if (isX86_64ExtendedReg(MO)) - REX |= 1 << Bit; - Bit++; - } - } - break; - } - case X86II::MRM0m: case X86II::MRM1m: - case X86II::MRM2m: case X86II::MRM3m: - case X86II::MRM4m: case X86II::MRM5m: - case X86II::MRM6m: case X86II::MRM7m: - case X86II::MRMDestMem: { - unsigned e = isTwoAddr ? 5 : 4; - i = isTwoAddr ? 1 : 0; - if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e))) - REX |= 1 << 2; - unsigned Bit = 0; - for (; i != e; ++i) { - const MachineOperand& MO = MI.getOperand(i); - if (MO.isRegister()) { - if (isX86_64ExtendedReg(MO)) - REX |= 1 << Bit; - Bit++; - } - } - break; - } - default: { - if (isX86_64ExtendedReg(MI.getOperand(0))) - REX |= 1 << 0; - i = isTwoAddr ? 2 : 1; - for (unsigned e = NumOps; i != e; ++i) { - const MachineOperand& MO = MI.getOperand(i); - if (isX86_64ExtendedReg(MO)) - REX |= 1 << 2; - } - break; - } - } - } - return REX; -} - void Emitter::emitInstruction(const MachineInstr &MI, const TargetInstrDesc *Desc) { DOUT << MI; @@ -547,6 +429,18 @@ void Emitter::emitInstruction(const MachineInstr &MI, // Emit the lock opcode prefix as needed. if (Desc->TSFlags & X86II::LOCK) MCE.emitByte(0xF0); + // Emit segment override opcode prefix as needed. + switch (Desc->TSFlags & X86II::SegOvrMask) { + case X86II::FS: + MCE.emitByte(0x64); + break; + case X86II::GS: + MCE.emitByte(0x65); + break; + default: assert(0 && "Invalid segment!"); + case 0: break; // No segment override! + } + // Emit the repeat opcode prefix as needed. if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3); @@ -558,16 +452,10 @@ void Emitter::emitInstruction(const MachineInstr &MI, bool Need0FPrefix = false; switch (Desc->TSFlags & X86II::Op0Mask) { - case X86II::TB: - Need0FPrefix = true; // Two-byte opcode prefix - break; - case X86II::T8: - MCE.emitByte(0x0F); - MCE.emitByte(0x38); - break; - case X86II::TA: - MCE.emitByte(0x0F); - MCE.emitByte(0x3A); + case X86II::TB: // Two-byte opcode prefix + case X86II::T8: // 0F 38 + case X86II::TA: // 0F 3A + Need0FPrefix = true; break; case X86II::REP: break; // already handled. case X86II::XS: // F3 0F @@ -590,7 +478,7 @@ void Emitter::emitInstruction(const MachineInstr &MI, if (Is64BitMode) { // REX prefix - unsigned REX = determineREX(MI); + unsigned REX = X86InstrInfo::determineREX(MI); if (REX) MCE.emitByte(0x40 | REX); } @@ -599,11 +487,23 @@ void Emitter::emitInstruction(const MachineInstr &MI, if (Need0FPrefix) MCE.emitByte(0x0F); + switch (Desc->TSFlags & X86II::Op0Mask) { + case X86II::T8: // 0F 38 + MCE.emitByte(0x38); + break; + case X86II::TA: // 0F 3A + MCE.emitByte(0x3A); + break; + } + // If this is a two-address instruction, skip one of the register operands. unsigned NumOps = Desc->getNumOperands(); unsigned CurOp = 0; if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1) - CurOp++; + ++CurOp; + else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0) + // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32 + --NumOps; unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc); switch (Desc->TSFlags & X86II::FormMask) { @@ -615,10 +515,17 @@ void Emitter::emitInstruction(const MachineInstr &MI, default: assert(0 && "psuedo instructions should be removed before code emission"); break; - case TargetInstrInfo::INLINEASM: - assert(0 && "JIT does not support inline asm!\n"); + case TargetInstrInfo::INLINEASM: { + // We allow inline assembler nodes with empty bodies - they can + // implicitly define registers, which is ok for JIT. + if (MI.getOperand(0).getSymbolName()[0]) { + assert(0 && "JIT does not support inline asm!\n"); + abort(); + } break; - case TargetInstrInfo::LABEL: + } + case TargetInstrInfo::DBG_LABEL: + case TargetInstrInfo::EH_LABEL: MCE.emitLabel(MI.getOperand(0).getImm()); break; case TargetInstrInfo::IMPLICIT_DEF: @@ -626,13 +533,30 @@ void Emitter::emitInstruction(const MachineInstr &MI, case X86::DWARF_LOC: case X86::FP_REG_KILL: break; + case X86::TLS_tp: { + MCE.emitByte(BaseOpcode); + unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg()); + MCE.emitByte(ModRMByte(0, RegOpcodeField, 5)); + emitConstant(0, 4); + break; + } + case X86::TLS_gs_ri: { + MCE.emitByte(BaseOpcode); + unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg()); + MCE.emitByte(ModRMByte(0, RegOpcodeField, 5)); + GlobalValue* GV = MI.getOperand(1).getGlobal(); + unsigned rt = Is64BitMode ? X86::reloc_pcrel_word + : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); + emitGlobalAddress(GV, rt); + break; + } case X86::MOVPC32r: { // This emits the "call" portion of this pseudo instruction. MCE.emitByte(BaseOpcode); - emitConstant(0, sizeOfImm(Desc)); + emitConstant(0, X86InstrInfo::sizeOfImm(Desc)); // Remember PIC base. - PICBaseOffset = MCE.getCurrentPCOffset(); - X86JITInfo *JTI = dynamic_cast(TM.getJITInfo()); + PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset(); + X86JITInfo *JTI = TM.getJITInfo(); JTI->setPICBase(MCE.getCurrentPCValue()); break; } @@ -644,17 +568,34 @@ void Emitter::emitInstruction(const MachineInstr &MI, if (CurOp != NumOps) { const MachineOperand &MO = MI.getOperand(CurOp++); - if (MO.isMachineBasicBlock()) { + + DOUT << "RawFrm CurOp " << CurOp << "\n"; + DOUT << "isMBB " << MO.isMBB() << "\n"; + DOUT << "isGlobal " << MO.isGlobal() << "\n"; + DOUT << "isSymbol " << MO.isSymbol() << "\n"; + DOUT << "isImm " << MO.isImm() << "\n"; + + if (MO.isMBB()) { emitPCRelativeBlockAddress(MO.getMBB()); - } else if (MO.isGlobalAddress()) { - bool NeedStub = (Is64BitMode && TM.getCodeModel() == CodeModel::Large) - || Opcode == X86::TAILJMPd; + } else if (MO.isGlobal()) { + // Assume undefined functions may be outside the Small codespace. + bool NeedStub = + (Is64BitMode && + (TM.getCodeModel() == CodeModel::Large || + TM.getSubtarget().isTargetDarwin())) || + Opcode == X86::TAILJMPd; emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word, - 0, 0, NeedStub); - } else if (MO.isExternalSymbol()) { + MO.getOffset(), 0, NeedStub); + } else if (MO.isSymbol()) { emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word); - } else if (MO.isImmediate()) { - emitConstant(MO.getImm(), sizeOfImm(Desc)); + } else if (MO.isImm()) { + if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) { + // Fix up immediate operand for pc relative calls. + intptr_t Imm = (intptr_t)MO.getImm(); + Imm = Imm - MCE.getCurrentPCValue() - 4; + emitConstant(Imm, X86InstrInfo::sizeOfImm(Desc)); + } else + emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc)); } else { assert(0 && "Unknown RawFrm operand!"); } @@ -666,24 +607,25 @@ void Emitter::emitInstruction(const MachineInstr &MI, if (CurOp != NumOps) { const MachineOperand &MO1 = MI.getOperand(CurOp++); - unsigned Size = sizeOfImm(Desc); - if (MO1.isImmediate()) + unsigned Size = X86InstrInfo::sizeOfImm(Desc); + if (MO1.isImm()) emitConstant(MO1.getImm(), Size); else { unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); + // This should not occur on Darwin for relocatable objects. if (Opcode == X86::MOV64ri) rt = X86::reloc_absolute_dword; // FIXME: add X86II flag? - if (MO1.isGlobalAddress()) { + if (MO1.isGlobal()) { bool NeedStub = isa(MO1.getGlobal()); - bool isLazy = gvNeedsLazyPtr(MO1.getGlobal()); + bool Indirect = gvNeedsNonLazyPtr(MO1.getGlobal()); emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0, - NeedStub, isLazy); - } else if (MO1.isExternalSymbol()) + NeedStub, Indirect); + } else if (MO1.isSymbol()) emitExternalSymbolAddress(MO1.getSymbolName(), rt); - else if (MO1.isConstantPoolIndex()) + else if (MO1.isCPI()) emitConstPoolAddress(MO1.getIndex(), rt); - else if (MO1.isJumpTableIndex()) + else if (MO1.isJTI()) emitJumpTableAddress(MO1.getIndex(), rt); } } @@ -695,7 +637,7 @@ void Emitter::emitInstruction(const MachineInstr &MI, getX86RegNum(MI.getOperand(CurOp+1).getReg())); CurOp += 2; if (CurOp != NumOps) - emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc)); + emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc)); break; } case X86II::MRMDestMem: { @@ -703,7 +645,7 @@ void Emitter::emitInstruction(const MachineInstr &MI, emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(CurOp+4).getReg())); CurOp += 5; if (CurOp != NumOps) - emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc)); + emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc)); break; } @@ -713,60 +655,67 @@ void Emitter::emitInstruction(const MachineInstr &MI, getX86RegNum(MI.getOperand(CurOp).getReg())); CurOp += 2; if (CurOp != NumOps) - emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc)); + emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc)); break; case X86II::MRMSrcMem: { - intptr_t PCAdj = (CurOp+5 != NumOps) ? sizeOfImm(Desc) : 0; + intptr_t PCAdj = (CurOp+5 != NumOps) ? X86InstrInfo::sizeOfImm(Desc) : 0; MCE.emitByte(BaseOpcode); emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()), PCAdj); CurOp += 5; if (CurOp != NumOps) - emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc)); + emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc)); break; } case X86II::MRM0r: case X86II::MRM1r: case X86II::MRM2r: case X86II::MRM3r: case X86II::MRM4r: case X86II::MRM5r: - case X86II::MRM6r: case X86II::MRM7r: + case X86II::MRM6r: case X86II::MRM7r: { MCE.emitByte(BaseOpcode); - emitRegModRMByte(MI.getOperand(CurOp++).getReg(), - (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r); + + // Special handling of lfence and mfence. + if (Desc->getOpcode() == X86::LFENCE || + Desc->getOpcode() == X86::MFENCE) + emitRegModRMByte((Desc->TSFlags & X86II::FormMask)-X86II::MRM0r); + else + emitRegModRMByte(MI.getOperand(CurOp++).getReg(), + (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r); if (CurOp != NumOps) { const MachineOperand &MO1 = MI.getOperand(CurOp++); - unsigned Size = sizeOfImm(Desc); - if (MO1.isImmediate()) + unsigned Size = X86InstrInfo::sizeOfImm(Desc); + if (MO1.isImm()) emitConstant(MO1.getImm(), Size); else { unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); if (Opcode == X86::MOV64ri32) rt = X86::reloc_absolute_word; // FIXME: add X86II flag? - if (MO1.isGlobalAddress()) { + if (MO1.isGlobal()) { bool NeedStub = isa(MO1.getGlobal()); - bool isLazy = gvNeedsLazyPtr(MO1.getGlobal()); + bool Indirect = gvNeedsNonLazyPtr(MO1.getGlobal()); emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0, - NeedStub, isLazy); - } else if (MO1.isExternalSymbol()) + NeedStub, Indirect); + } else if (MO1.isSymbol()) emitExternalSymbolAddress(MO1.getSymbolName(), rt); - else if (MO1.isConstantPoolIndex()) + else if (MO1.isCPI()) emitConstPoolAddress(MO1.getIndex(), rt); - else if (MO1.isJumpTableIndex()) + else if (MO1.isJTI()) emitJumpTableAddress(MO1.getIndex(), rt); } } break; + } case X86II::MRM0m: case X86II::MRM1m: case X86II::MRM2m: case X86II::MRM3m: case X86II::MRM4m: case X86II::MRM5m: case X86II::MRM6m: case X86II::MRM7m: { intptr_t PCAdj = (CurOp+4 != NumOps) ? - (MI.getOperand(CurOp+4).isImmediate() ? sizeOfImm(Desc) : 4) : 0; + (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm(Desc) : 4) : 0; MCE.emitByte(BaseOpcode); emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m, @@ -775,24 +724,24 @@ void Emitter::emitInstruction(const MachineInstr &MI, if (CurOp != NumOps) { const MachineOperand &MO = MI.getOperand(CurOp++); - unsigned Size = sizeOfImm(Desc); - if (MO.isImmediate()) + unsigned Size = X86InstrInfo::sizeOfImm(Desc); + if (MO.isImm()) emitConstant(MO.getImm(), Size); else { unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); if (Opcode == X86::MOV64mi32) rt = X86::reloc_absolute_word; // FIXME: add X86II flag? - if (MO.isGlobalAddress()) { + if (MO.isGlobal()) { bool NeedStub = isa(MO.getGlobal()); - bool isLazy = gvNeedsLazyPtr(MO.getGlobal()); + bool Indirect = gvNeedsNonLazyPtr(MO.getGlobal()); emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0, - NeedStub, isLazy); - } else if (MO.isExternalSymbol()) + NeedStub, Indirect); + } else if (MO.isSymbol()) emitExternalSymbolAddress(MO.getSymbolName(), rt); - else if (MO.isConstantPoolIndex()) + else if (MO.isCPI()) emitConstPoolAddress(MO.getIndex(), rt); - else if (MO.isJumpTableIndex()) + else if (MO.isJTI()) emitJumpTableAddress(MO.getIndex(), rt); } }