X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86FloatingPoint.cpp;h=37027ee8bebae506808503a4afa55ded703ba386;hb=d1474d09cbe5fdeec8ba0d6c6b52f316f3422532;hp=9a048ccb728ed35a9ef785ad4c7293bfea68e765;hpb=3e15bf33e024b9df9e89351a165acfdb1dde51ed;p=oota-llvm.git diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp index 9a048ccb728..37027ee8beb 100644 --- a/lib/Target/X86/X86FloatingPoint.cpp +++ b/lib/Target/X86/X86FloatingPoint.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -33,18 +33,18 @@ #include "X86InstrInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/LiveVariables.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" #include "llvm/ADT/DepthFirstIterator.h" +#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/STLExtras.h" #include -#include using namespace llvm; STATISTIC(NumFXCH, "Number of fxch instructions inserted"); @@ -52,20 +52,21 @@ STATISTIC(NumFP , "Number of floating point instructions"); namespace { struct VISIBILITY_HIDDEN FPS : public MachineFunctionPass { - static const char ID; - FPS() : MachineFunctionPass((intptr_t)&ID) {} + static char ID; + FPS() : MachineFunctionPass(&ID) {} + + virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addPreservedID(MachineLoopInfoID); + AU.addPreservedID(MachineDominatorsID); + MachineFunctionPass::getAnalysisUsage(AU); + } virtual bool runOnMachineFunction(MachineFunction &MF); virtual const char *getPassName() const { return "X86 FP Stackifier"; } - virtual void getAnalysisUsage(AnalysisUsage &AU) const { - AU.addRequired(); - MachineFunctionPass::getAnalysisUsage(AU); - } private: const TargetInstrInfo *TII; // Machine instruction info. - LiveVariables *LV; // Live variable info for current function... MachineBasicBlock *MBB; // Current basic block unsigned Stack[8]; // FP Registers in each stack slot... unsigned RegMap[8]; // Track which stack slot contains each register @@ -80,26 +81,31 @@ namespace { cerr << "\n"; } private: + /// isStackEmpty - Return true if the FP stack is empty. + bool isStackEmpty() const { + return StackTop == 0; + } + // getSlot - Return the stack slot number a particular register number is - // in... + // in. unsigned getSlot(unsigned RegNo) const { assert(RegNo < 8 && "Regno out of range!"); return RegMap[RegNo]; } - // getStackEntry - Return the X86::FP register in register ST(i) + // getStackEntry - Return the X86::FP register in register ST(i). unsigned getStackEntry(unsigned STi) const { assert(STi < StackTop && "Access past stack top!"); return Stack[StackTop-1-STi]; } // getSTReg - Return the X86::ST(i) register which contains the specified - // FP register + // FP register. unsigned getSTReg(unsigned RegNo) const { return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0; } - // pushReg - Push the specified FP register onto the stack + // pushReg - Push the specified FP register onto the stack. void pushReg(unsigned Reg) { assert(Reg < 8 && "Register number out of range!"); assert(StackTop < 8 && "Stack overflow!"); @@ -108,29 +114,32 @@ namespace { } bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; } - void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) { - if (!isAtTop(RegNo)) { - unsigned STReg = getSTReg(RegNo); - unsigned RegOnTop = getStackEntry(0); + void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) { + MachineInstr *MI = I; + DebugLoc dl = MI->getDebugLoc(); + if (isAtTop(RegNo)) return; + + unsigned STReg = getSTReg(RegNo); + unsigned RegOnTop = getStackEntry(0); - // Swap the slots the regs are in - std::swap(RegMap[RegNo], RegMap[RegOnTop]); + // Swap the slots the regs are in. + std::swap(RegMap[RegNo], RegMap[RegOnTop]); - // Swap stack slot contents - assert(RegMap[RegOnTop] < StackTop); - std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]); + // Swap stack slot contents. + assert(RegMap[RegOnTop] < StackTop); + std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]); - // Emit an fxch to update the runtime processors version of the state - BuildMI(*MBB, I, TII->get(X86::FXCH)).addReg(STReg); - NumFXCH++; - } + // Emit an fxch to update the runtime processors version of the state. + BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); + NumFXCH++; } void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) { + DebugLoc dl = I->getDebugLoc(); unsigned STReg = getSTReg(RegNo); pushReg(AsReg); // New register on top of stack - BuildMI(*MBB, I, TII->get(X86::FLDrr)).addReg(STReg); + BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); } // popStackAfter - Pop the current value off of the top of the FP stack @@ -154,11 +163,21 @@ namespace { void handleCondMovFP(MachineBasicBlock::iterator &I); void handleSpecialFP(MachineBasicBlock::iterator &I); }; - const char FPS::ID = 0; + char FPS::ID = 0; } FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); } +/// getFPReg - Return the X86::FPx register number for the specified operand. +/// For example, this returns 3 for X86::FP3. +static unsigned getFPReg(const MachineOperand &MO) { + assert(MO.isReg() && "Expected an FP register!"); + unsigned Reg = MO.getReg(); + assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); + return Reg - X86::FP0; +} + + /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP /// register references into FP stack references. /// @@ -169,7 +188,7 @@ bool FPS::runOnMachineFunction(MachineFunction &MF) { assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!"); for (unsigned i = 0; i <= 6; ++i) - if (MF.isPhysRegUsed(X86::FP0+i)) { + if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) { FPIsUsed = true; break; } @@ -178,16 +197,15 @@ bool FPS::runOnMachineFunction(MachineFunction &MF) { if (!FPIsUsed) return false; TII = MF.getTarget().getInstrInfo(); - LV = &getAnalysis(); StackTop = 0; // Process the function in depth first order so that we process at least one // of the predecessors for every reachable block in the function. - std::set Processed; + SmallPtrSet Processed; MachineBasicBlock *Entry = MF.begin(); bool Changed = false; - for (df_ext_iterator > + for (df_ext_iterator > I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed); I != E; ++I) Changed |= processBasicBlock(MF, **I); @@ -204,13 +222,18 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) { for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) { MachineInstr *MI = I; - unsigned Flags = MI->getInstrDescriptor()->TSFlags; - if ((Flags & X86II::FPTypeMask) == X86II::NotFP) + unsigned Flags = MI->getDesc().TSFlags; + + unsigned FPInstClass = Flags & X86II::FPTypeMask; + if (MI->getOpcode() == TargetInstrInfo::INLINEASM) + FPInstClass = X86II::SpecialFP; + + if (FPInstClass == X86II::NotFP) continue; // Efficiently ignore non-fp insts! MachineInstr *PrevMI = 0; if (I != BB.begin()) - PrevMI = prior(I); + PrevMI = prior(I); ++NumFP; // Keep track of # of pseudo instrs DOUT << "\nFPInst:\t" << *MI; @@ -224,7 +247,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) { DeadRegs.push_back(MO.getReg()); } - switch (Flags & X86II::FPTypeMask) { + switch (FPInstClass) { case X86II::ZeroArgFP: handleZeroArgFP(I); break; case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0) case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0)) @@ -256,7 +279,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) { while (Start != BB.begin() && prior(Start) != PrevI) --Start; cerr << "Inserted instructions:\n\t"; Start->print(*cerr.stream(), &MF.getTarget()); - while (++Start != next(I)); + while (++Start != next(I)) {} } dumpStack(); ); @@ -264,7 +287,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) { Changed = true; } - assert(StackTop == 0 && "Stack not empty at end of basic block?"); + assert(isStackEmpty() && "Stack not empty at end of basic block?"); return Changed; } @@ -286,11 +309,13 @@ namespace { }; } +#ifndef NDEBUG static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) { for (unsigned i = 0; i != NumEntries-1; ++i) if (!(Table[i] < Table[i+1])) return false; return true; } +#endif static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) { const TableEntry *I = std::lower_bound(Table, Table+N, Opcode); @@ -299,16 +324,13 @@ static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) { return -1; } -#define ARRAY_SIZE(TABLE) \ - (sizeof(TABLE)/sizeof(TABLE[0])) - #ifdef NDEBUG #define ASSERT_SORTED(TABLE) #else #define ASSERT_SORTED(TABLE) \ { static bool TABLE##Checked = false; \ if (!TABLE##Checked) { \ - assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) && \ + assert(TableIsSorted(TABLE, array_lengthof(TABLE)) && \ "All lookup tables must be sorted for efficient access!"); \ TABLE##Checked = true; \ } \ @@ -324,66 +346,170 @@ static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) { // concrete X86 instruction which uses the register stack. // static const TableEntry OpcodeTable[] = { - { X86::FpABS , X86::FABS }, - { X86::FpADD32m , X86::FADD32m }, - { X86::FpADD64m , X86::FADD64m }, - { X86::FpCHS , X86::FCHS }, - { X86::FpCMOVB , X86::FCMOVB }, - { X86::FpCMOVBE , X86::FCMOVBE }, - { X86::FpCMOVE , X86::FCMOVE }, - { X86::FpCMOVNB , X86::FCMOVNB }, - { X86::FpCMOVNBE , X86::FCMOVNBE }, - { X86::FpCMOVNE , X86::FCMOVNE }, - { X86::FpCMOVNP , X86::FCMOVNP }, - { X86::FpCMOVP , X86::FCMOVP }, - { X86::FpCOS , X86::FCOS }, - { X86::FpDIV32m , X86::FDIV32m }, - { X86::FpDIV64m , X86::FDIV64m }, - { X86::FpDIVR32m , X86::FDIVR32m }, - { X86::FpDIVR64m , X86::FDIVR64m }, - { X86::FpIADD16m , X86::FIADD16m }, - { X86::FpIADD32m , X86::FIADD32m }, - { X86::FpIDIV16m , X86::FIDIV16m }, - { X86::FpIDIV32m , X86::FIDIV32m }, - { X86::FpIDIVR16m, X86::FIDIVR16m}, - { X86::FpIDIVR32m, X86::FIDIVR32m}, - { X86::FpILD16m , X86::FILD16m }, - { X86::FpILD32m , X86::FILD32m }, - { X86::FpILD64m , X86::FILD64m }, - { X86::FpIMUL16m , X86::FIMUL16m }, - { X86::FpIMUL32m , X86::FIMUL32m }, - { X86::FpIST16m , X86::FIST16m }, - { X86::FpIST32m , X86::FIST32m }, - { X86::FpIST64m , X86::FISTP64m }, - { X86::FpISTT16m , X86::FISTTP16m}, - { X86::FpISTT32m , X86::FISTTP32m}, - { X86::FpISTT64m , X86::FISTTP64m}, - { X86::FpISUB16m , X86::FISUB16m }, - { X86::FpISUB32m , X86::FISUB32m }, - { X86::FpISUBR16m, X86::FISUBR16m}, - { X86::FpISUBR32m, X86::FISUBR32m}, - { X86::FpLD0 , X86::FLD0 }, - { X86::FpLD1 , X86::FLD1 }, - { X86::FpLD32m , X86::FLD32m }, - { X86::FpLD64m , X86::FLD64m }, - { X86::FpMUL32m , X86::FMUL32m }, - { X86::FpMUL64m , X86::FMUL64m }, - { X86::FpSIN , X86::FSIN }, - { X86::FpSQRT , X86::FSQRT }, - { X86::FpST32m , X86::FST32m }, - { X86::FpST64m , X86::FST64m }, - { X86::FpSUB32m , X86::FSUB32m }, - { X86::FpSUB64m , X86::FSUB64m }, - { X86::FpSUBR32m , X86::FSUBR32m }, - { X86::FpSUBR64m , X86::FSUBR64m }, - { X86::FpTST , X86::FTST }, - { X86::FpUCOMIr , X86::FUCOMIr }, - { X86::FpUCOMr , X86::FUCOMr }, + { X86::ABS_Fp32 , X86::ABS_F }, + { X86::ABS_Fp64 , X86::ABS_F }, + { X86::ABS_Fp80 , X86::ABS_F }, + { X86::ADD_Fp32m , X86::ADD_F32m }, + { X86::ADD_Fp64m , X86::ADD_F64m }, + { X86::ADD_Fp64m32 , X86::ADD_F32m }, + { X86::ADD_Fp80m32 , X86::ADD_F32m }, + { X86::ADD_Fp80m64 , X86::ADD_F64m }, + { X86::ADD_FpI16m32 , X86::ADD_FI16m }, + { X86::ADD_FpI16m64 , X86::ADD_FI16m }, + { X86::ADD_FpI16m80 , X86::ADD_FI16m }, + { X86::ADD_FpI32m32 , X86::ADD_FI32m }, + { X86::ADD_FpI32m64 , X86::ADD_FI32m }, + { X86::ADD_FpI32m80 , X86::ADD_FI32m }, + { X86::CHS_Fp32 , X86::CHS_F }, + { X86::CHS_Fp64 , X86::CHS_F }, + { X86::CHS_Fp80 , X86::CHS_F }, + { X86::CMOVBE_Fp32 , X86::CMOVBE_F }, + { X86::CMOVBE_Fp64 , X86::CMOVBE_F }, + { X86::CMOVBE_Fp80 , X86::CMOVBE_F }, + { X86::CMOVB_Fp32 , X86::CMOVB_F }, + { X86::CMOVB_Fp64 , X86::CMOVB_F }, + { X86::CMOVB_Fp80 , X86::CMOVB_F }, + { X86::CMOVE_Fp32 , X86::CMOVE_F }, + { X86::CMOVE_Fp64 , X86::CMOVE_F }, + { X86::CMOVE_Fp80 , X86::CMOVE_F }, + { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F }, + { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F }, + { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F }, + { X86::CMOVNB_Fp32 , X86::CMOVNB_F }, + { X86::CMOVNB_Fp64 , X86::CMOVNB_F }, + { X86::CMOVNB_Fp80 , X86::CMOVNB_F }, + { X86::CMOVNE_Fp32 , X86::CMOVNE_F }, + { X86::CMOVNE_Fp64 , X86::CMOVNE_F }, + { X86::CMOVNE_Fp80 , X86::CMOVNE_F }, + { X86::CMOVNP_Fp32 , X86::CMOVNP_F }, + { X86::CMOVNP_Fp64 , X86::CMOVNP_F }, + { X86::CMOVNP_Fp80 , X86::CMOVNP_F }, + { X86::CMOVP_Fp32 , X86::CMOVP_F }, + { X86::CMOVP_Fp64 , X86::CMOVP_F }, + { X86::CMOVP_Fp80 , X86::CMOVP_F }, + { X86::COS_Fp32 , X86::COS_F }, + { X86::COS_Fp64 , X86::COS_F }, + { X86::COS_Fp80 , X86::COS_F }, + { X86::DIVR_Fp32m , X86::DIVR_F32m }, + { X86::DIVR_Fp64m , X86::DIVR_F64m }, + { X86::DIVR_Fp64m32 , X86::DIVR_F32m }, + { X86::DIVR_Fp80m32 , X86::DIVR_F32m }, + { X86::DIVR_Fp80m64 , X86::DIVR_F64m }, + { X86::DIVR_FpI16m32, X86::DIVR_FI16m}, + { X86::DIVR_FpI16m64, X86::DIVR_FI16m}, + { X86::DIVR_FpI16m80, X86::DIVR_FI16m}, + { X86::DIVR_FpI32m32, X86::DIVR_FI32m}, + { X86::DIVR_FpI32m64, X86::DIVR_FI32m}, + { X86::DIVR_FpI32m80, X86::DIVR_FI32m}, + { X86::DIV_Fp32m , X86::DIV_F32m }, + { X86::DIV_Fp64m , X86::DIV_F64m }, + { X86::DIV_Fp64m32 , X86::DIV_F32m }, + { X86::DIV_Fp80m32 , X86::DIV_F32m }, + { X86::DIV_Fp80m64 , X86::DIV_F64m }, + { X86::DIV_FpI16m32 , X86::DIV_FI16m }, + { X86::DIV_FpI16m64 , X86::DIV_FI16m }, + { X86::DIV_FpI16m80 , X86::DIV_FI16m }, + { X86::DIV_FpI32m32 , X86::DIV_FI32m }, + { X86::DIV_FpI32m64 , X86::DIV_FI32m }, + { X86::DIV_FpI32m80 , X86::DIV_FI32m }, + { X86::ILD_Fp16m32 , X86::ILD_F16m }, + { X86::ILD_Fp16m64 , X86::ILD_F16m }, + { X86::ILD_Fp16m80 , X86::ILD_F16m }, + { X86::ILD_Fp32m32 , X86::ILD_F32m }, + { X86::ILD_Fp32m64 , X86::ILD_F32m }, + { X86::ILD_Fp32m80 , X86::ILD_F32m }, + { X86::ILD_Fp64m32 , X86::ILD_F64m }, + { X86::ILD_Fp64m64 , X86::ILD_F64m }, + { X86::ILD_Fp64m80 , X86::ILD_F64m }, + { X86::ISTT_Fp16m32 , X86::ISTT_FP16m}, + { X86::ISTT_Fp16m64 , X86::ISTT_FP16m}, + { X86::ISTT_Fp16m80 , X86::ISTT_FP16m}, + { X86::ISTT_Fp32m32 , X86::ISTT_FP32m}, + { X86::ISTT_Fp32m64 , X86::ISTT_FP32m}, + { X86::ISTT_Fp32m80 , X86::ISTT_FP32m}, + { X86::ISTT_Fp64m32 , X86::ISTT_FP64m}, + { X86::ISTT_Fp64m64 , X86::ISTT_FP64m}, + { X86::ISTT_Fp64m80 , X86::ISTT_FP64m}, + { X86::IST_Fp16m32 , X86::IST_F16m }, + { X86::IST_Fp16m64 , X86::IST_F16m }, + { X86::IST_Fp16m80 , X86::IST_F16m }, + { X86::IST_Fp32m32 , X86::IST_F32m }, + { X86::IST_Fp32m64 , X86::IST_F32m }, + { X86::IST_Fp32m80 , X86::IST_F32m }, + { X86::IST_Fp64m32 , X86::IST_FP64m }, + { X86::IST_Fp64m64 , X86::IST_FP64m }, + { X86::IST_Fp64m80 , X86::IST_FP64m }, + { X86::LD_Fp032 , X86::LD_F0 }, + { X86::LD_Fp064 , X86::LD_F0 }, + { X86::LD_Fp080 , X86::LD_F0 }, + { X86::LD_Fp132 , X86::LD_F1 }, + { X86::LD_Fp164 , X86::LD_F1 }, + { X86::LD_Fp180 , X86::LD_F1 }, + { X86::LD_Fp32m , X86::LD_F32m }, + { X86::LD_Fp32m64 , X86::LD_F32m }, + { X86::LD_Fp32m80 , X86::LD_F32m }, + { X86::LD_Fp64m , X86::LD_F64m }, + { X86::LD_Fp64m80 , X86::LD_F64m }, + { X86::LD_Fp80m , X86::LD_F80m }, + { X86::MUL_Fp32m , X86::MUL_F32m }, + { X86::MUL_Fp64m , X86::MUL_F64m }, + { X86::MUL_Fp64m32 , X86::MUL_F32m }, + { X86::MUL_Fp80m32 , X86::MUL_F32m }, + { X86::MUL_Fp80m64 , X86::MUL_F64m }, + { X86::MUL_FpI16m32 , X86::MUL_FI16m }, + { X86::MUL_FpI16m64 , X86::MUL_FI16m }, + { X86::MUL_FpI16m80 , X86::MUL_FI16m }, + { X86::MUL_FpI32m32 , X86::MUL_FI32m }, + { X86::MUL_FpI32m64 , X86::MUL_FI32m }, + { X86::MUL_FpI32m80 , X86::MUL_FI32m }, + { X86::SIN_Fp32 , X86::SIN_F }, + { X86::SIN_Fp64 , X86::SIN_F }, + { X86::SIN_Fp80 , X86::SIN_F }, + { X86::SQRT_Fp32 , X86::SQRT_F }, + { X86::SQRT_Fp64 , X86::SQRT_F }, + { X86::SQRT_Fp80 , X86::SQRT_F }, + { X86::ST_Fp32m , X86::ST_F32m }, + { X86::ST_Fp64m , X86::ST_F64m }, + { X86::ST_Fp64m32 , X86::ST_F32m }, + { X86::ST_Fp80m32 , X86::ST_F32m }, + { X86::ST_Fp80m64 , X86::ST_F64m }, + { X86::ST_FpP80m , X86::ST_FP80m }, + { X86::SUBR_Fp32m , X86::SUBR_F32m }, + { X86::SUBR_Fp64m , X86::SUBR_F64m }, + { X86::SUBR_Fp64m32 , X86::SUBR_F32m }, + { X86::SUBR_Fp80m32 , X86::SUBR_F32m }, + { X86::SUBR_Fp80m64 , X86::SUBR_F64m }, + { X86::SUBR_FpI16m32, X86::SUBR_FI16m}, + { X86::SUBR_FpI16m64, X86::SUBR_FI16m}, + { X86::SUBR_FpI16m80, X86::SUBR_FI16m}, + { X86::SUBR_FpI32m32, X86::SUBR_FI32m}, + { X86::SUBR_FpI32m64, X86::SUBR_FI32m}, + { X86::SUBR_FpI32m80, X86::SUBR_FI32m}, + { X86::SUB_Fp32m , X86::SUB_F32m }, + { X86::SUB_Fp64m , X86::SUB_F64m }, + { X86::SUB_Fp64m32 , X86::SUB_F32m }, + { X86::SUB_Fp80m32 , X86::SUB_F32m }, + { X86::SUB_Fp80m64 , X86::SUB_F64m }, + { X86::SUB_FpI16m32 , X86::SUB_FI16m }, + { X86::SUB_FpI16m64 , X86::SUB_FI16m }, + { X86::SUB_FpI16m80 , X86::SUB_FI16m }, + { X86::SUB_FpI32m32 , X86::SUB_FI32m }, + { X86::SUB_FpI32m64 , X86::SUB_FI32m }, + { X86::SUB_FpI32m80 , X86::SUB_FI32m }, + { X86::TST_Fp32 , X86::TST_F }, + { X86::TST_Fp64 , X86::TST_F }, + { X86::TST_Fp80 , X86::TST_F }, + { X86::UCOM_FpIr32 , X86::UCOM_FIr }, + { X86::UCOM_FpIr64 , X86::UCOM_FIr }, + { X86::UCOM_FpIr80 , X86::UCOM_FIr }, + { X86::UCOM_Fpr32 , X86::UCOM_Fr }, + { X86::UCOM_Fpr64 , X86::UCOM_Fr }, + { X86::UCOM_Fpr80 , X86::UCOM_Fr }, }; static unsigned getConcreteOpcode(unsigned Opcode) { ASSERT_SORTED(OpcodeTable); - int Opc = Lookup(OpcodeTable, ARRAY_SIZE(OpcodeTable), Opcode); + int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode); assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!"); return Opc; } @@ -396,27 +522,27 @@ static unsigned getConcreteOpcode(unsigned Opcode) { // element is an instruction, the second is the version which pops. // static const TableEntry PopTable[] = { - { X86::FADDrST0 , X86::FADDPrST0 }, + { X86::ADD_FrST0 , X86::ADD_FPrST0 }, - { X86::FDIVRrST0, X86::FDIVRPrST0 }, - { X86::FDIVrST0 , X86::FDIVPrST0 }, + { X86::DIVR_FrST0, X86::DIVR_FPrST0 }, + { X86::DIV_FrST0 , X86::DIV_FPrST0 }, - { X86::FIST16m , X86::FISTP16m }, - { X86::FIST32m , X86::FISTP32m }, + { X86::IST_F16m , X86::IST_FP16m }, + { X86::IST_F32m , X86::IST_FP32m }, - { X86::FMULrST0 , X86::FMULPrST0 }, + { X86::MUL_FrST0 , X86::MUL_FPrST0 }, - { X86::FST32m , X86::FSTP32m }, - { X86::FST64m , X86::FSTP64m }, - { X86::FSTrr , X86::FSTPrr }, + { X86::ST_F32m , X86::ST_FP32m }, + { X86::ST_F64m , X86::ST_FP64m }, + { X86::ST_Frr , X86::ST_FPrr }, - { X86::FSUBRrST0, X86::FSUBRPrST0 }, - { X86::FSUBrST0 , X86::FSUBPrST0 }, + { X86::SUBR_FrST0, X86::SUBR_FPrST0 }, + { X86::SUB_FrST0 , X86::SUB_FPrST0 }, - { X86::FUCOMIr , X86::FUCOMIPr }, + { X86::UCOM_FIr , X86::UCOM_FIPr }, - { X86::FUCOMPr , X86::FUCOMPPr }, - { X86::FUCOMr , X86::FUCOMPr }, + { X86::UCOM_FPr , X86::UCOM_FPPr }, + { X86::UCOM_Fr , X86::UCOM_FPr }, }; /// popStackAfter - Pop the current value off of the top of the FP stack after @@ -426,18 +552,20 @@ static const TableEntry PopTable[] = { /// instruction if it was modified in place. /// void FPS::popStackAfter(MachineBasicBlock::iterator &I) { + MachineInstr* MI = I; + DebugLoc dl = MI->getDebugLoc(); ASSERT_SORTED(PopTable); assert(StackTop > 0 && "Cannot pop empty stack!"); RegMap[Stack[--StackTop]] = ~0; // Update state // Check to see if there is a popping version of this instruction... - int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), I->getOpcode()); + int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode()); if (Opcode != -1) { - I->setInstrDescriptor(TII->get(Opcode)); - if (Opcode == X86::FUCOMPPr) + I->setDesc(TII->get(Opcode)); + if (Opcode == X86::UCOM_FPPr) I->RemoveOperand(0); } else { // Insert an explicit pop - I = BuildMI(*MBB, ++I, TII->get(X86::FSTPrr)).addReg(X86::ST0); + I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0); } } @@ -461,15 +589,9 @@ void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) { RegMap[TopReg] = OldSlot; RegMap[FPRegNo] = ~0; Stack[--StackTop] = ~0; - I = BuildMI(*MBB, ++I, TII->get(X86::FSTPrr)).addReg(STReg); -} - - -static unsigned getFPReg(const MachineOperand &MO) { - assert(MO.isRegister() && "Expected an FP register!"); - unsigned Reg = MO.getReg(); - assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); - return Reg - X86::FP0; + MachineInstr *MI = I; + DebugLoc dl = MI->getDebugLoc(); + I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(STReg); } @@ -485,7 +607,7 @@ void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) { // Change from the pseudo instruction to the concrete instruction. MI->RemoveOperand(0); // Remove the explicit ST(0) operand - MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode()))); + MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); // Result gets pushed on the stack. pushReg(DestReg); @@ -495,25 +617,34 @@ void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) { /// void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) { MachineInstr *MI = I; - unsigned NumOps = MI->getInstrDescriptor()->numOperands; - assert((NumOps == 5 || NumOps == 1) && + unsigned NumOps = MI->getDesc().getNumOperands(); + assert((NumOps == X86AddrNumOperands + 1 || NumOps == 1) && "Can only handle fst* & ftst instructions!"); // Is this the last use of the source register? unsigned Reg = getFPReg(MI->getOperand(NumOps-1)); - bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg); + bool KillsSrc = MI->killsRegister(X86::FP0+Reg); // FISTP64m is strange because there isn't a non-popping versions. // If we have one _and_ we don't want to pop the operand, duplicate the value // on the stack instead of moving it. This ensure that popping the value is // always ok. - // Ditto FISTTP16m, FISTTP32m, FISTTP64m. + // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m. // if (!KillsSrc && - (MI->getOpcode() == X86::FpIST64m || - MI->getOpcode() == X86::FpISTT16m || - MI->getOpcode() == X86::FpISTT32m || - MI->getOpcode() == X86::FpISTT64m)) { + (MI->getOpcode() == X86::IST_Fp64m32 || + MI->getOpcode() == X86::ISTT_Fp16m32 || + MI->getOpcode() == X86::ISTT_Fp32m32 || + MI->getOpcode() == X86::ISTT_Fp64m32 || + MI->getOpcode() == X86::IST_Fp64m64 || + MI->getOpcode() == X86::ISTT_Fp16m64 || + MI->getOpcode() == X86::ISTT_Fp32m64 || + MI->getOpcode() == X86::ISTT_Fp64m64 || + MI->getOpcode() == X86::IST_Fp64m80 || + MI->getOpcode() == X86::ISTT_Fp16m80 || + MI->getOpcode() == X86::ISTT_Fp32m80 || + MI->getOpcode() == X86::ISTT_Fp64m80 || + MI->getOpcode() == X86::ST_FpP80m)) { duplicateToTop(Reg, 7 /*temp register*/, I); } else { moveToTop(Reg, I); // Move to the top of the stack... @@ -521,12 +652,13 @@ void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) { // Convert from the pseudo instruction to the concrete instruction. MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand - MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode()))); + MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); - if (MI->getOpcode() == X86::FISTP64m || - MI->getOpcode() == X86::FISTTP16m || - MI->getOpcode() == X86::FISTTP32m || - MI->getOpcode() == X86::FISTTP64m) { + if (MI->getOpcode() == X86::IST_FP64m || + MI->getOpcode() == X86::ISTT_FP16m || + MI->getOpcode() == X86::ISTT_FP32m || + MI->getOpcode() == X86::ISTT_FP64m || + MI->getOpcode() == X86::ST_FP80m) { assert(StackTop > 0 && "Stack empty??"); --StackTop; } else if (KillsSrc) { // Last use of operand? @@ -545,12 +677,14 @@ void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) { /// void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) { MachineInstr *MI = I; - unsigned NumOps = MI->getInstrDescriptor()->numOperands; +#ifndef NDEBUG + unsigned NumOps = MI->getDesc().getNumOperands(); assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!"); +#endif // Is this the last use of the source register? unsigned Reg = getFPReg(MI->getOperand(1)); - bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg); + bool KillsSrc = MI->killsRegister(X86::FP0+Reg); if (KillsSrc) { // If this is the last use of the source register, just make sure it's on @@ -568,7 +702,7 @@ void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) { // Change from the pseudo instruction to the concrete instruction. MI->RemoveOperand(1); // Drop the source operand. MI->RemoveOperand(0); // Drop the destination operand. - MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode()))); + MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); } @@ -578,34 +712,66 @@ void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) { // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i) static const TableEntry ForwardST0Table[] = { - { X86::FpADD , X86::FADDST0r }, - { X86::FpDIV , X86::FDIVST0r }, - { X86::FpMUL , X86::FMULST0r }, - { X86::FpSUB , X86::FSUBST0r }, + { X86::ADD_Fp32 , X86::ADD_FST0r }, + { X86::ADD_Fp64 , X86::ADD_FST0r }, + { X86::ADD_Fp80 , X86::ADD_FST0r }, + { X86::DIV_Fp32 , X86::DIV_FST0r }, + { X86::DIV_Fp64 , X86::DIV_FST0r }, + { X86::DIV_Fp80 , X86::DIV_FST0r }, + { X86::MUL_Fp32 , X86::MUL_FST0r }, + { X86::MUL_Fp64 , X86::MUL_FST0r }, + { X86::MUL_Fp80 , X86::MUL_FST0r }, + { X86::SUB_Fp32 , X86::SUB_FST0r }, + { X86::SUB_Fp64 , X86::SUB_FST0r }, + { X86::SUB_Fp80 , X86::SUB_FST0r }, }; // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0) static const TableEntry ReverseST0Table[] = { - { X86::FpADD , X86::FADDST0r }, // commutative - { X86::FpDIV , X86::FDIVRST0r }, - { X86::FpMUL , X86::FMULST0r }, // commutative - { X86::FpSUB , X86::FSUBRST0r }, + { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative + { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative + { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative + { X86::DIV_Fp32 , X86::DIVR_FST0r }, + { X86::DIV_Fp64 , X86::DIVR_FST0r }, + { X86::DIV_Fp80 , X86::DIVR_FST0r }, + { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative + { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative + { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative + { X86::SUB_Fp32 , X86::SUBR_FST0r }, + { X86::SUB_Fp64 , X86::SUBR_FST0r }, + { X86::SUB_Fp80 , X86::SUBR_FST0r }, }; // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i) static const TableEntry ForwardSTiTable[] = { - { X86::FpADD , X86::FADDrST0 }, // commutative - { X86::FpDIV , X86::FDIVRrST0 }, - { X86::FpMUL , X86::FMULrST0 }, // commutative - { X86::FpSUB , X86::FSUBRrST0 }, + { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative + { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative + { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative + { X86::DIV_Fp32 , X86::DIVR_FrST0 }, + { X86::DIV_Fp64 , X86::DIVR_FrST0 }, + { X86::DIV_Fp80 , X86::DIVR_FrST0 }, + { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative + { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative + { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative + { X86::SUB_Fp32 , X86::SUBR_FrST0 }, + { X86::SUB_Fp64 , X86::SUBR_FrST0 }, + { X86::SUB_Fp80 , X86::SUBR_FrST0 }, }; // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0) static const TableEntry ReverseSTiTable[] = { - { X86::FpADD , X86::FADDrST0 }, - { X86::FpDIV , X86::FDIVrST0 }, - { X86::FpMUL , X86::FMULrST0 }, - { X86::FpSUB , X86::FSUBrST0 }, + { X86::ADD_Fp32 , X86::ADD_FrST0 }, + { X86::ADD_Fp64 , X86::ADD_FrST0 }, + { X86::ADD_Fp80 , X86::ADD_FrST0 }, + { X86::DIV_Fp32 , X86::DIV_FrST0 }, + { X86::DIV_Fp64 , X86::DIV_FrST0 }, + { X86::DIV_Fp80 , X86::DIV_FrST0 }, + { X86::MUL_Fp32 , X86::MUL_FrST0 }, + { X86::MUL_Fp64 , X86::MUL_FrST0 }, + { X86::MUL_Fp80 , X86::MUL_FrST0 }, + { X86::SUB_Fp32 , X86::SUB_FrST0 }, + { X86::SUB_Fp64 , X86::SUB_FrST0 }, + { X86::SUB_Fp80 , X86::SUB_FrST0 }, }; @@ -622,13 +788,14 @@ void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) { ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); MachineInstr *MI = I; - unsigned NumOperands = MI->getInstrDescriptor()->numOperands; + unsigned NumOperands = MI->getDesc().getNumOperands(); assert(NumOperands == 3 && "Illegal TwoArgFP instruction!"); unsigned Dest = getFPReg(MI->getOperand(0)); unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); - bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0); - bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1); + bool KillsOp0 = MI->killsRegister(X86::FP0+Op0); + bool KillsOp1 = MI->killsRegister(X86::FP0+Op1); + DebugLoc dl = MI->getDebugLoc(); unsigned TOS = getStackEntry(0); @@ -685,7 +852,8 @@ void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) { InstTable = ReverseSTiTable; } - int Opcode = Lookup(InstTable, ARRAY_SIZE(ForwardST0Table), MI->getOpcode()); + int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table), + MI->getOpcode()); assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!"); // NotTOS - The register which is not on the top of stack... @@ -693,7 +861,7 @@ void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) { // Replace the old instruction with a new instruction MBB->remove(I++); - I = BuildMI(*MBB, I, TII->get(Opcode)).addReg(getSTReg(NotTOS)); + I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS)); // If both operands are killed, pop one off of the stack in addition to // overwriting the other one. @@ -708,7 +876,7 @@ void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) { assert(UpdatedSlot < StackTop && Dest < 7); Stack[UpdatedSlot] = Dest; RegMap[Dest] = UpdatedSlot; - delete MI; // Remove the old instruction + MBB->getParent()->DeleteMachineInstr(MI); // Remove the old instruction } /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP @@ -719,12 +887,12 @@ void FPS::handleCompareFP(MachineBasicBlock::iterator &I) { ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); MachineInstr *MI = I; - unsigned NumOperands = MI->getInstrDescriptor()->numOperands; + unsigned NumOperands = MI->getDesc().getNumOperands(); assert(NumOperands == 2 && "Illegal FUCOM* instruction!"); unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); - bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0); - bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1); + bool KillsOp0 = MI->killsRegister(X86::FP0+Op0); + bool KillsOp1 = MI->killsRegister(X86::FP0+Op1); // Make sure the first operand is on the top of stack, the other one can be // anywhere. @@ -733,7 +901,7 @@ void FPS::handleCompareFP(MachineBasicBlock::iterator &I) { // Change from the pseudo instruction to the concrete instruction. MI->getOperand(0).setReg(getSTReg(Op1)); MI->RemoveOperand(1); - MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode()))); + MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); // If any of the operands are killed by this instruction, free them. if (KillsOp0) freeStackSlotAfter(I, Op0); @@ -749,7 +917,7 @@ void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) { unsigned Op0 = getFPReg(MI->getOperand(0)); unsigned Op1 = getFPReg(MI->getOperand(2)); - bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1); + bool KillsOp1 = MI->killsRegister(X86::FP0+Op1); // The first operand *must* be on the top of the stack. moveToTop(Op0, I); @@ -759,7 +927,7 @@ void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) { MI->RemoveOperand(0); MI->RemoveOperand(1); MI->getOperand(0).setReg(getSTReg(Op1)); - MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode()))); + MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); // If we kill the second operand, make sure to pop it from the stack. if (Op0 != Op1 && KillsOp1) { @@ -775,21 +943,122 @@ void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) { /// void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) { MachineInstr *MI = I; + DebugLoc dl = MI->getDebugLoc(); switch (MI->getOpcode()) { default: assert(0 && "Unknown SpecialFP instruction!"); - case X86::FpGETRESULT: // Appears immediately after a call returning FP type! + case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type! + case X86::FpGET_ST0_64:// Appears immediately after a call returning FP type! + case X86::FpGET_ST0_80:// Appears immediately after a call returning FP type! assert(StackTop == 0 && "Stack should be empty after a call!"); pushReg(getFPReg(MI->getOperand(0))); break; - case X86::FpSETRESULT: - assert(StackTop == 1 && "Stack should have one element on it to return!"); + case X86::FpGET_ST1_32:// Appears immediately after a call returning FP type! + case X86::FpGET_ST1_64:// Appears immediately after a call returning FP type! + case X86::FpGET_ST1_80:{// Appears immediately after a call returning FP type! + // FpGET_ST1 should occur right after a FpGET_ST0 for a call or inline asm. + // The pattern we expect is: + // CALL + // FP1 = FpGET_ST0 + // FP4 = FpGET_ST1 + // + // At this point, we've pushed FP1 on the top of stack, so it should be + // present if it isn't dead. If it was dead, we already emitted a pop to + // remove it from the stack and StackTop = 0. + + // Push FP4 as top of stack next. + pushReg(getFPReg(MI->getOperand(0))); + + // If StackTop was 0 before we pushed our operand, then ST(0) must have been + // dead. In this case, the ST(1) value is the only thing that is live, so + // it should be on the TOS (after the pop that was emitted) and is. Just + // continue in this case. + if (StackTop == 1) + break; + + // Because pushReg just pushed ST(1) as TOS, we now have to swap the two top + // elements so that our accounting is correct. + unsigned RegOnTop = getStackEntry(0); + unsigned RegNo = getStackEntry(1); + + // Swap the slots the regs are in. + std::swap(RegMap[RegNo], RegMap[RegOnTop]); + + // Swap stack slot contents. + assert(RegMap[RegOnTop] < StackTop); + std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]); + break; + } + case X86::FpSET_ST0_32: + case X86::FpSET_ST0_64: + case X86::FpSET_ST0_80: { + unsigned Op0 = getFPReg(MI->getOperand(0)); + + // FpSET_ST0_80 is generated by copyRegToReg for both function return + // and inline assembly with the "st" constrain. In the latter case, + // it is possible for ST(0) to be alive after this instruction. + if (!MI->killsRegister(X86::FP0 + Op0)) { + // Duplicate Op0 + duplicateToTop(0, 7 /*temp register*/, I); + } else { + moveToTop(Op0, I); + } --StackTop; // "Forget" we have something on the top of stack! break; - case X86::FpMOV: { - unsigned SrcReg = getFPReg(MI->getOperand(1)); - unsigned DestReg = getFPReg(MI->getOperand(0)); + } + case X86::FpSET_ST1_32: + case X86::FpSET_ST1_64: + case X86::FpSET_ST1_80: + // StackTop can be 1 if a FpSET_ST0_* was before this. Exchange them. + if (StackTop == 1) { + BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(X86::ST1); + NumFXCH++; + StackTop = 0; + break; + } + assert(StackTop == 2 && "Stack should have two element on it to return!"); + --StackTop; // "Forget" we have something on the top of stack! + break; + case X86::MOV_Fp3232: + case X86::MOV_Fp3264: + case X86::MOV_Fp6432: + case X86::MOV_Fp6464: + case X86::MOV_Fp3280: + case X86::MOV_Fp6480: + case X86::MOV_Fp8032: + case X86::MOV_Fp8064: + case X86::MOV_Fp8080: { + const MachineOperand &MO1 = MI->getOperand(1); + unsigned SrcReg = getFPReg(MO1); + + const MachineOperand &MO0 = MI->getOperand(0); + // These can be created due to inline asm. Two address pass can introduce + // copies from RFP registers to virtual registers. + if (MO0.getReg() == X86::ST0 && SrcReg == 0) { + assert(MO1.isKill()); + // Treat %ST0 = MOV_Fp8080 %FP0 + // like FpSET_ST0_80 %FP0, %ST0 + assert((StackTop == 1 || StackTop == 2) + && "Stack should have one or two element on it to return!"); + --StackTop; // "Forget" we have something on the top of stack! + break; + } else if (MO0.getReg() == X86::ST1 && SrcReg == 1) { + assert(MO1.isKill()); + // Treat %ST1 = MOV_Fp8080 %FP1 + // like FpSET_ST1_80 %FP0, %ST1 + // StackTop can be 1 if a FpSET_ST0_* was before this. Exchange them. + if (StackTop == 1) { + BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(X86::ST1); + NumFXCH++; + StackTop = 0; + break; + } + assert(StackTop == 2 && "Stack should have two element on it to return!"); + --StackTop; // "Forget" we have something on the top of stack! + break; + } - if (LV->KillsRegister(MI, X86::FP0+SrcReg)) { + unsigned DestReg = getFPReg(MO0); + if (MI->killsRegister(X86::FP0+SrcReg)) { // If the input operand is killed, we can just change the owner of the // incoming stack slot into the result. unsigned Slot = getSlot(SrcReg); @@ -802,8 +1071,125 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) { // This could be made better, but would require substantial changes. duplicateToTop(SrcReg, DestReg, I); } + } break; + case TargetInstrInfo::INLINEASM: { + // The inline asm MachineInstr currently only *uses* FP registers for the + // 'f' constraint. These should be turned into the current ST(x) register + // in the machine instr. Also, any kills should be explicitly popped after + // the inline asm. + unsigned Kills[7]; + unsigned NumKills = 0; + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand &Op = MI->getOperand(i); + if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) + continue; + assert(Op.isUse() && "Only handle inline asm uses right now"); + + unsigned FPReg = getFPReg(Op); + Op.setReg(getSTReg(FPReg)); + + // If we kill this operand, make sure to pop it from the stack after the + // asm. We just remember it for now, and pop them all off at the end in + // a batch. + if (Op.isKill()) + Kills[NumKills++] = FPReg; + } + + // If this asm kills any FP registers (is the last use of them) we must + // explicitly emit pop instructions for them. Do this now after the asm has + // executed so that the ST(x) numbers are not off (which would happen if we + // did this inline with operand rewriting). + // + // Note: this might be a non-optimal pop sequence. We might be able to do + // better by trying to pop in stack order or something. + MachineBasicBlock::iterator InsertPt = MI; + while (NumKills) + freeStackSlotAfter(InsertPt, Kills[--NumKills]); + + // Don't delete the inline asm! + return; } + + case X86::RET: + case X86::RETI: + // If RET has an FP register use operand, pass the first one in ST(0) and + // the second one in ST(1). + if (isStackEmpty()) return; // Quick check to see if any are possible. + + // Find the register operands. + unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U; + + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand &Op = MI->getOperand(i); + if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) + continue; + // FP Register uses must be kills unless there are two uses of the same + // register, in which case only one will be a kill. + assert(Op.isUse() && + (Op.isKill() || // Marked kill. + getFPReg(Op) == FirstFPRegOp || // Second instance. + MI->killsRegister(Op.getReg())) && // Later use is marked kill. + "Ret only defs operands, and values aren't live beyond it"); + + if (FirstFPRegOp == ~0U) + FirstFPRegOp = getFPReg(Op); + else { + assert(SecondFPRegOp == ~0U && "More than two fp operands!"); + SecondFPRegOp = getFPReg(Op); + } + + // Remove the operand so that later passes don't see it. + MI->RemoveOperand(i); + --i, --e; + } + + // There are only four possibilities here: + // 1) we are returning a single FP value. In this case, it has to be in + // ST(0) already, so just declare success by removing the value from the + // FP Stack. + if (SecondFPRegOp == ~0U) { + // Assert that the top of stack contains the right FP register. + assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) && + "Top of stack not the right register for RET!"); + + // Ok, everything is good, mark the value as not being on the stack + // anymore so that our assertion about the stack being empty at end of + // block doesn't fire. + StackTop = 0; + return; + } + + // Otherwise, we are returning two values: + // 2) If returning the same value for both, we only have one thing in the FP + // stack. Consider: RET FP1, FP1 + if (StackTop == 1) { + assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&& + "Stack misconfiguration for RET!"); + + // Duplicate the TOS so that we return it twice. Just pick some other FPx + // register to hold it. + unsigned NewReg = (FirstFPRegOp+1)%7; + duplicateToTop(FirstFPRegOp, NewReg, MI); + FirstFPRegOp = NewReg; + } + + /// Okay we know we have two different FPx operands now: + assert(StackTop == 2 && "Must have two values live!"); + + /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently + /// in ST(1). In this case, emit an fxch. + if (getStackEntry(0) == SecondFPRegOp) { + assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live"); + moveToTop(FirstFPRegOp, MI); + } + + /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in + /// ST(1). Just remove both from our understanding of the stack and return. + assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live"); + assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live"); + StackTop = 0; + return; } I = MBB->erase(I); // Remove the pseudo instruction