X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86ISelSimple.cpp;h=a8ed6f69c0e6d74e329d4d51a954a47ab38ce472;hb=7d25589ee19747720a6cdb045ae442332f90bbcf;hp=40d757b645af08b77d53a2cf64f455e05f39e66c;hpb=95780cccef3f6630a912aba9e2241819d7a00ba4;p=oota-llvm.git diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp index 40d757b645a..a8ed6f69c0e 100644 --- a/lib/Target/X86/X86ISelSimple.cpp +++ b/lib/Target/X86/X86ISelSimple.cpp @@ -26,6 +26,32 @@ using namespace MOTy; // Get Use, Def, UseAndDef + +/// BMI - A special BuildMI variant that takes an iterator to insert the +/// instruction at as well as a basic block. +/// this is the version for when you have a destination register in mind. +inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB, + MachineBasicBlock::iterator &I, + MachineOpCode Opcode, + unsigned NumOperands, + unsigned DestReg) { + MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true); + I = ++MBB->insert(I, MI); + return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def); +} + +/// BMI - A special BuildMI variant that takes an iterator to insert the +/// instruction at as well as a basic block. +inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB, + MachineBasicBlock::iterator &I, + MachineOpCode Opcode, + unsigned NumOperands) { + MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true); + I = ++MBB->insert(I, MI); + return MachineInstrBuilder(MI); +} + + namespace { struct ISel : public FunctionPass, InstVisitor { TargetMachine &TM; @@ -35,6 +61,9 @@ namespace { unsigned CurReg; std::map RegMap; // Mapping between Val's and SSA Regs + // MBBMap - Mapping between LLVM BB -> Machine BB + std::map MBBMap; + ISel(TargetMachine &tm) : TM(tm), F(0), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {} @@ -43,8 +72,18 @@ namespace { /// bool runOnFunction(Function &Fn) { F = &MachineFunction::construct(&Fn, TM); + + for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) + F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I)); + + // Instruction select everything except PHI nodes visit(Fn); + + // Select the PHI nodes + SelectPHINodes(); + RegMap.clear(); + MBBMap.clear(); CurReg = MRegisterInfo::FirstVirtualRegister; F = 0; return false; // We never modify the LLVM itself. @@ -56,11 +95,16 @@ namespace { /// instructions will be invoked for all instructions in the basic block. /// void visitBasicBlock(BasicBlock &LLVM_BB) { - BB = new MachineBasicBlock(&LLVM_BB); - // FIXME: Use the auto-insert form when it's available - F->getBasicBlockList().push_back(BB); + BB = MBBMap[&LLVM_BB]; } + + /// SelectPHINodes - Insert machine code to generate phis. This is tricky + /// because we have to generate our sources into the source basic blocks, + /// not the current one. + /// + void SelectPHINodes(); + // Visitation methods for various instructions. These methods simply emit // fixed X86 code for each instruction. // @@ -75,7 +119,9 @@ namespace { void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); } void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); } void doMultiply(unsigned destReg, const Type *resultType, - unsigned op0Reg, unsigned op1Reg); + unsigned op0Reg, unsigned op1Reg, + MachineBasicBlock *MBB, + MachineBasicBlock::iterator &MBBI); void visitMul(BinaryOperator &B); void visitDiv(BinaryOperator &B) { visitDivRem(B); } @@ -106,7 +152,7 @@ namespace { // Other operators void visitShiftInst(ShiftInst &I); - void visitPHINode(PHINode &I); + void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass void visitCastInst(CastInst &I); void visitInstruction(Instruction &I) { @@ -120,13 +166,16 @@ namespace { // emitGEPOperation - Common code shared between visitGetElementPtrInst and // constant expression GEP support. // - void emitGEPOperation(Value *Src, User::op_iterator IdxBegin, + void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator&IP, + Value *Src, User::op_iterator IdxBegin, User::op_iterator IdxEnd, unsigned TargetReg); /// copyConstantToRegister - Output the instructions required to put the /// specified constant into the specified register. /// - void copyConstantToRegister(Constant *C, unsigned Reg); + void copyConstantToRegister(Constant *C, unsigned Reg, + MachineBasicBlock *MBB, + MachineBasicBlock::iterator &MBBI); /// makeAnotherReg - This method returns the next register number /// we haven't yet used. @@ -142,6 +191,12 @@ namespace { /// unsigned getReg(Value &V) { return getReg(&V); } // Allow references unsigned getReg(Value *V) { + // Just append to the end of the current bb. + MachineBasicBlock::iterator It = BB->end(); + return getReg(V, BB, It); + } + unsigned getReg(Value *V, MachineBasicBlock *MBB, + MachineBasicBlock::iterator &IPt) { unsigned &Reg = RegMap[V]; if (Reg == 0) { Reg = makeAnotherReg(V->getType()); @@ -152,30 +207,31 @@ namespace { // the register here... // if (Constant *C = dyn_cast(V)) { - copyConstantToRegister(C, Reg); + copyConstantToRegister(C, Reg, BB, IPt); } else if (GlobalValue *GV = dyn_cast(V)) { // Move the address of the global into the register - BuildMI(BB, X86::MOVir32, 1, Reg).addReg(GV); + BMI(MBB, IPt, X86::MOVir32, 1, Reg).addReg(GV); } else if (Argument *A = dyn_cast(V)) { // Find the position of the argument in the argument list. const Function *f = F->getFunction (); - int counter = 0, argPosition = -1; + // The function's arguments look like this: + // [EBP] -- copy of old EBP + // [EBP + 4] -- return address + // [EBP + 8] -- first argument (leftmost lexically) + // So we want to start with counter = 2. + int counter = 2, argPos = -1; for (Function::const_aiterator ai = f->abegin (), ae = f->aend (); ai != ae; ++ai) { - ++counter; if (&(*ai) == A) { - argPosition = counter; + argPos = counter; + break; // Only need to find it once. ;-) } + ++counter; } - assert (argPosition != -1 + assert (argPos != -1 && "Argument not found in current function's argument list"); - // Load it out of the stack frame at EBP + 4*argPosition. - // (First, load Reg with argPosition, then load Reg with DWORD - // PTR [EBP + 4*Reg].) - BuildMI (BB, X86::MOVir32, 1, Reg).addZImm (argPosition); - BuildMI (BB, X86::MOVmr32, 4, - Reg).addReg (X86::EBP).addZImm (4).addReg (Reg).addSImm (0); - // std::cerr << "ERROR: Arguments not implemented in SimpleInstSel\n"; + // Load it out of the stack frame at EBP + 4*argPos. + addRegOffset(BMI(MBB, IPt, X86::MOVmr32, 4, Reg), X86::EBP, 4*argPos); } return Reg; @@ -219,10 +275,13 @@ static inline TypeClass getClass(const Type *Ty) { /// copyConstantToRegister - Output the instructions required to put the /// specified constant into the specified register. /// -void ISel::copyConstantToRegister(Constant *C, unsigned R) { +void ISel::copyConstantToRegister(Constant *C, unsigned R, + MachineBasicBlock *MBB, + MachineBasicBlock::iterator &IP) { if (ConstantExpr *CE = dyn_cast(C)) { if (CE->getOpcode() == Instruction::GetElementPtr) { - emitGEPOperation(CE->getOperand(0), CE->op_begin()+1, CE->op_end(), R); + emitGEPOperation(BB, IP, CE->getOperand(0), + CE->op_begin()+1, CE->op_end(), R); return; } @@ -240,23 +299,59 @@ void ISel::copyConstantToRegister(Constant *C, unsigned R) { if (C->getType()->isSigned()) { ConstantSInt *CSI = cast(C); - BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addSImm(CSI->getValue()); + BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addSImm(CSI->getValue()); } else { ConstantUInt *CUI = cast(C); - BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue()); + BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue()); } - } else if (isa (C)) { + } else if (isa(C)) { // Copy zero (null pointer) to the register. - BuildMI (BB, X86::MOVir32, 1, R).addZImm(0); + BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(0); } else if (ConstantPointerRef *CPR = dyn_cast(C)) { - unsigned SrcReg = getReg(CPR->getValue()); - BuildMI (BB, X86::MOVrr32, 1, R).addReg(SrcReg); + unsigned SrcReg = getReg(CPR->getValue(), BB, IP); + BMI(MBB, IP, X86::MOVrr32, 1, R).addReg(SrcReg); } else { std::cerr << "Offending constant: " << C << "\n"; assert(0 && "Type not handled yet!"); } } +/// SelectPHINodes - Insert machine code to generate phis. This is tricky +/// because we have to generate our sources into the source basic blocks, not +/// the current one. +/// +void ISel::SelectPHINodes() { + const Function &LF = *F->getFunction(); // The LLVM function... + for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) { + const BasicBlock *BB = I; + MachineBasicBlock *MBB = MBBMap[I]; + + // Loop over all of the PHI nodes in the LLVM basic block... + unsigned NumPHIs = 0; + for (BasicBlock::const_iterator I = BB->begin(); + PHINode *PN = (PHINode*)dyn_cast(&*I); ++I) { + // Create a new machine instr PHI node, and insert it. + MachineInstr *MI = BuildMI(X86::PHI, PN->getNumOperands(), getReg(*PN)); + MBB->insert(MBB->begin()+NumPHIs++, MI); // Insert it at the top of the BB + + for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { + MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)]; + + // Get the incoming value into a virtual register. If it is not already + // available in a virtual register, insert the computation code into + // PredMBB + MachineBasicBlock::iterator PI = PredMBB->end()-1; + MI->addRegOperand(getReg(PN->getIncomingValue(i), PredMBB, PI)); + + + // FIXME: Pass in the MachineBasicBlocks instead of the basic blocks... + MI->addPCDispOperand(PN->getIncomingBlock(i)); // PredMBB + } + } + } +} + + /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized /// register, then move it to wherever the result should be. @@ -555,7 +650,8 @@ void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) { /// The type of the result should be given as resultType. void ISel::doMultiply(unsigned destReg, const Type *resultType, - unsigned op0Reg, unsigned op1Reg) + unsigned op0Reg, unsigned op1Reg, + MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI) { unsigned Class = getClass (resultType); @@ -570,21 +666,23 @@ ISel::doMultiply(unsigned destReg, const Type *resultType, // Emit a MOV to put the first operand into the appropriately-sized // subreg of EAX. - BuildMI (BB, MovOpcode[Class], 1, Reg).addReg (op0Reg); + BMI(MBB, MBBI, MovOpcode[Class], 1, Reg).addReg (op0Reg); // Emit the appropriate multiply instruction. - BuildMI (BB, MulOpcode[Class], 1).addReg (op1Reg); + BMI(MBB, MBBI, MulOpcode[Class], 1).addReg (op1Reg); // Emit another MOV to put the result into the destination register. - BuildMI (BB, MovOpcode[Class], 1, destReg).addReg (Reg); + BMI(MBB, MBBI, MovOpcode[Class], 1, destReg).addReg (Reg); } /// visitMul - Multiplies are not simple binary operators because they must deal /// with the EAX register explicitly. /// void ISel::visitMul(BinaryOperator &I) { + MachineBasicBlock::iterator MBBI = BB->end(); doMultiply (getReg (I), I.getType (), - getReg (I.getOperand (0)), getReg (I.getOperand (1))); + getReg (I.getOperand (0)), getReg (I.getOperand (1)), + BB, MBBI); } @@ -730,20 +828,6 @@ void ISel::visitStoreInst(StoreInst &I) { } -/// visitPHINode - Turn an LLVM PHI node into an X86 PHI node... -/// -void ISel::visitPHINode(PHINode &PN) { - MachineInstr *MI = BuildMI(BB, X86::PHI, PN.getNumOperands(), getReg(PN)); - - for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) { - // FIXME: This will put constants after the PHI nodes in the block, which - // is invalid. They should be put inline into the PHI node eventually. - // - MI->addRegOperand(getReg(PN.getIncomingValue(i))); - MI->addPCDispOperand(PN.getIncomingBlock(i)); - } -} - /// visitCastInst - Here we have various kinds of copying with or without /// sign extension going on. void @@ -770,7 +854,7 @@ ISel::visitCastInst (CastInst &CI) // 4) cast {int, uint, ptr} to {short, ushort} // cast {int, uint, ptr} to {sbyte, ubyte} // cast {short, ushort} to {sbyte, ubyte} - // + // 1) Implement casts to bool by using compare on the operand followed // by set if not zero on the result. if (targetType == Type::BoolTy) @@ -779,10 +863,11 @@ ISel::visitCastInst (CastInst &CI) BuildMI (BB, X86::SETNEr, 1, destReg); return; } + // 2) Implement casts between values of the same type class (as determined // by getClass) by using a register-to-register move. - unsigned int srcClass = getClass (sourceType); - unsigned int targClass = getClass (targetType); + unsigned srcClass = sourceType == Type::BoolTy ? cByte : getClass(sourceType); + unsigned targClass = getClass (targetType); static const unsigned regRegMove[] = { X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 }; @@ -836,14 +921,18 @@ ISel::visitCastInst (CastInst &CI) void ISel::visitGetElementPtrInst (GetElementPtrInst &I) { - emitGEPOperation(I.getOperand(0), I.op_begin()+1, I.op_end(), getReg(I)); + MachineBasicBlock::iterator MI = BB->end(); + emitGEPOperation(BB, MI, I.getOperand(0), + I.op_begin()+1, I.op_end(), getReg(I)); } -void ISel::emitGEPOperation(Value *Src, User::op_iterator IdxBegin, +void ISel::emitGEPOperation(MachineBasicBlock *MBB, + MachineBasicBlock::iterator &IP, + Value *Src, User::op_iterator IdxBegin, User::op_iterator IdxEnd, unsigned TargetReg) { const TargetData &TD = TM.getTargetData(); const Type *Ty = Src->getType(); - unsigned basePtrReg = getReg(Src); + unsigned basePtrReg = getReg(Src, BB, IP); // GEPs have zero or more indices; we must perform a struct access // or array access for each one. @@ -866,8 +955,8 @@ void ISel::emitGEPOperation(Value *Src, User::op_iterator IdxBegin, unsigned memberOffset = TD.getStructLayout (StTy)->MemberOffsets[idxValue]; // Emit an ADD to add memberOffset to the basePtr. - BuildMI (BB, X86::ADDri32, 2, - nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset); + BMI(MBB, IP, X86::ADDri32, 2, + nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset); // The next type is the member of the structure selected by the // index. Ty = StTy->getElementTypes ()[idxValue]; @@ -885,19 +974,20 @@ void ISel::emitGEPOperation(Value *Src, User::op_iterator IdxBegin, // elements in the array.) Ty = SqTy->getElementType (); unsigned elementSize = TD.getTypeSize (Ty); - unsigned elementSizeReg = makeAnotherReg(Type::UIntTy); - copyConstantToRegister (ConstantInt::get (typeOfSequentialTypeIndex, - elementSize), - elementSizeReg); - unsigned idxReg = getReg (idx); + unsigned elementSizeReg = makeAnotherReg(typeOfSequentialTypeIndex); + copyConstantToRegister(ConstantSInt::get(typeOfSequentialTypeIndex, + elementSize), elementSizeReg, + BB, IP); + + unsigned idxReg = getReg(idx, BB, IP); // Emit a MUL to multiply the register holding the index by // elementSize, putting the result in memberOffsetReg. unsigned memberOffsetReg = makeAnotherReg(Type::UIntTy); doMultiply (memberOffsetReg, typeOfSequentialTypeIndex, - elementSizeReg, idxReg); + elementSizeReg, idxReg, BB, IP); // Emit an ADD to add memberOffsetReg to the basePtr. - BuildMI (BB, X86::ADDrr32, 2, - nextBasePtrReg).addReg (basePtrReg).addReg (memberOffsetReg); + BMI(MBB, IP, X86::ADDrr32, 2, + nextBasePtrReg).addReg (basePtrReg).addReg (memberOffsetReg); } // Now that we are here, further indices refer to subtypes of this // one, so we don't need to worry about basePtrReg itself, anymore. @@ -907,7 +997,7 @@ void ISel::emitGEPOperation(Value *Src, User::op_iterator IdxBegin, // basePtrReg. Move it to the register where we were expected to // put the answer. A 32-bit move should do it, because we are in // ILP32 land. - BuildMI (BB, X86::MOVrr32, 1, TargetReg).addReg (basePtrReg); + BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg (basePtrReg); }