X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86ISelSimple.cpp;h=e88354a6ad18aca591b9457deb5ac8e03c54d01a;hb=5000e43809947222b416caf6cb265d7d2b3b5e13;hp=d74bfd4912e9151fa33b4af6ae36aa794b46c96a;hpb=71e83caecd0ea8cd0dea214e0d2091709aabf665;p=oota-llvm.git diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp index d74bfd4912e..e88354a6ad1 100644 --- a/lib/Target/X86/X86ISelSimple.cpp +++ b/lib/Target/X86/X86ISelSimple.cpp @@ -14,10 +14,16 @@ #include "llvm/iPHINode.h" #include "llvm/iMemory.h" #include "llvm/Type.h" +#include "llvm/DerivedTypes.h" #include "llvm/Constants.h" #include "llvm/Pass.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/Target/TargetMachine.h" #include "llvm/Support/InstVisitor.h" +#include "llvm/Target/MRegisterInfo.h" +#include +#include using namespace MOTy; // Get Use, Def, UseAndDef @@ -40,6 +46,7 @@ namespace { F = &MachineFunction::construct(&Fn, TM); visit(Fn); RegMap.clear(); + CurReg = MRegisterInfo::FirstVirtualRegister; F = 0; return false; // We never modify the LLVM itself. } @@ -58,13 +65,18 @@ namespace { // Visitation methods for various instructions. These methods simply emit // fixed X86 code for each instruction. // + + // Control flow operators void visitReturnInst(ReturnInst &RI); void visitBranchInst(BranchInst &BI); + void visitCallInst(CallInst &I); // Arithmetic operators void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass); void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); } void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); } + void doMultiply(unsigned destReg, const Type *resultType, + unsigned op0Reg, unsigned op1Reg); void visitMul(BinaryOperator &B); void visitDiv(BinaryOperator &B) { visitDivRem(B); } @@ -77,27 +89,45 @@ namespace { void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); } // Binary comparison operators - void visitSetCondInst(SetCondInst &I); + void visitSetCCInst(SetCondInst &I, unsigned OpNum); + void visitSetEQ(SetCondInst &I) { visitSetCCInst(I, 0); } + void visitSetNE(SetCondInst &I) { visitSetCCInst(I, 1); } + void visitSetLT(SetCondInst &I) { visitSetCCInst(I, 2); } + void visitSetGT(SetCondInst &I) { visitSetCCInst(I, 3); } + void visitSetLE(SetCondInst &I) { visitSetCCInst(I, 4); } + void visitSetGE(SetCondInst &I) { visitSetCCInst(I, 5); } // Memory Instructions void visitLoadInst(LoadInst &I); void visitStoreInst(StoreInst &I); - + void visitGetElementPtrInst(GetElementPtrInst &I); + void visitMallocInst(MallocInst &I); + void visitAllocaInst(AllocaInst &I); + // Other operators void visitShiftInst(ShiftInst &I); void visitPHINode(PHINode &I); + void visitCastInst(CastInst &I); void visitInstruction(Instruction &I) { std::cerr << "Cannot instruction select: " << I; abort(); } + void promote32 (const unsigned targetReg, Value *v); /// copyConstantToRegister - Output the instructions required to put the /// specified constant into the specified register. /// void copyConstantToRegister(Constant *C, unsigned Reg); + /// makeAnotherReg - This method returns the next register number + /// we haven't yet used. + unsigned makeAnotherReg (void) { + unsigned Reg = CurReg++; + return Reg; + } + /// getReg - This method turns an LLVM value into a register number. This /// is guaranteed to produce the same register number for a particular value /// every time it is queried. @@ -105,14 +135,26 @@ namespace { unsigned getReg(Value &V) { return getReg(&V); } // Allow references unsigned getReg(Value *V) { unsigned &Reg = RegMap[V]; - if (Reg == 0) - Reg = CurReg++; + if (Reg == 0) { + Reg = makeAnotherReg (); + RegMap[V] = Reg; + + // Add the mapping of regnumber => reg class to MachineFunction + F->addRegMap(Reg, + TM.getRegisterInfo()->getRegClassForType(V->getType())); + } // If this operand is a constant, emit the code to copy the constant into // the register here... // - if (Constant *C = dyn_cast(V)) + if (Constant *C = dyn_cast(V)) { copyConstantToRegister(C, Reg); + } else if (GlobalValue *GV = dyn_cast(V)) { + // Move the address of the global into the register + BuildMI(BB, X86::MOVir32, 1, Reg).addReg(GV); + } else if (Argument *A = dyn_cast(V)) { + std::cerr << "ERROR: Arguments not implemented in SimpleInstSel\n"; + } return Reg; } @@ -154,6 +196,11 @@ static inline TypeClass getClass(const Type *Ty) { /// specified constant into the specified register. /// void ISel::copyConstantToRegister(Constant *C, unsigned R) { + if (isa (C)) { + // FIXME: We really need to handle getelementptr exprs, among + // other things. + std::cerr << "Offending expr: " << C << "\n"; + } assert (!isa(C) && "Constant expressions not yet handled!\n"); if (C->getType()->isIntegral()) { @@ -171,7 +218,11 @@ void ISel::copyConstantToRegister(Constant *C, unsigned R) { ConstantUInt *CUI = cast(C); BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue()); } + } else if (isa (C)) { + // Copy zero (null pointer) to the register. + BuildMI (BB, X86::MOVir32, 1, R).addZImm(0); } else { + std::cerr << "Offending constant: " << C << "\n"; assert(0 && "Type not handled yet!"); } } @@ -183,80 +234,52 @@ void ISel::copyConstantToRegister(Constant *C, unsigned R) { /// compare-and-pop-twice, and then copying the concodes to the main /// processor's concodes (I didn't make this up, it's in the Intel manual) /// -void -ISel::visitSetCondInst (SetCondInst & I) -{ +void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) { // The arguments are already supposed to be of the same type. - Value *var1 = I.getOperand (0); - Value *var2 = I.getOperand (1); - unsigned reg1 = getReg (var1); - unsigned reg2 = getReg (var2); - unsigned resultReg = getReg (I); - unsigned comparisonWidth = var1->getType ()->getPrimitiveSize (); - unsigned unsignedComparison = var1->getType ()->isUnsigned (); - unsigned resultWidth = I.getType ()->getPrimitiveSize (); - bool fpComparison = var1->getType ()->isFloatingPoint (); - if (fpComparison) - { - // Push the variables on the stack with fldl opcodes. - // FIXME: assuming var1, var2 are in memory, if not, spill to - // stack first - switch (comparisonWidth) - { - case 4: - BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg1); - break; - case 8: - BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg1); - break; - default: - visitInstruction (I); - break; - } - switch (comparisonWidth) - { - case 4: - BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg2); - break; - case 8: - BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg2); - break; - default: - visitInstruction (I); - break; - } - // (Non-trapping) compare and pop twice. - BuildMI (BB, X86::FUCOMPP, 0); - // Move fp status word (concodes) to ax. - BuildMI (BB, X86::FNSTSWr8, 1, X86::AX); - // Load real concodes from ax. - BuildMI (BB, X86::SAHF, 1, X86::EFLAGS).addReg(X86::AH); - } - else - { // integer comparison - // Emit: cmp , (do the comparison). We can - // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with - // 32-bit. - switch (comparisonWidth) - { - case 1: - BuildMI (BB, X86::CMPrr8, 2, - X86::EFLAGS).addReg (reg1).addReg (reg2); - break; - case 2: - BuildMI (BB, X86::CMPrr16, 2, - X86::EFLAGS).addReg (reg1).addReg (reg2); - break; - case 4: - BuildMI (BB, X86::CMPrr32, 2, - X86::EFLAGS).addReg (reg1).addReg (reg2); - break; - case 8: - default: - visitInstruction (I); - break; - } - } + const Type *CompTy = I.getOperand(0)->getType(); + unsigned reg1 = getReg(I.getOperand(0)); + unsigned reg2 = getReg(I.getOperand(1)); + + unsigned Class = getClass(CompTy); + switch (Class) { + // Emit: cmp , (do the comparison). We can + // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with + // 32-bit. + case cByte: + BuildMI (BB, X86::CMPrr8, 2).addReg (reg1).addReg (reg2); + break; + case cShort: + BuildMI (BB, X86::CMPrr16, 2).addReg (reg1).addReg (reg2); + break; + case cInt: + BuildMI (BB, X86::CMPrr32, 2).addReg (reg1).addReg (reg2); + break; + + // Push the variables on the stack with fldl opcodes. + // FIXME: assuming var1, var2 are in memory, if not, spill to + // stack first + case cFloat: // Floats + BuildMI (BB, X86::FLDr32, 1).addReg (reg1); + BuildMI (BB, X86::FLDr32, 1).addReg (reg2); + break; + case cDouble: // Doubles + BuildMI (BB, X86::FLDr64, 1).addReg (reg1); + BuildMI (BB, X86::FLDr64, 1).addReg (reg2); + break; + case cLong: + default: + visitInstruction(I); + } + + if (CompTy->isFloatingPoint()) { + // (Non-trapping) compare and pop twice. + BuildMI (BB, X86::FUCOMPP, 0); + // Move fp status word (concodes) to ax. + BuildMI (BB, X86::FNSTSWr8, 1, X86::AX); + // Load real concodes from ax. + BuildMI (BB, X86::SAHF, 1).addReg(X86::AH); + } + // Emit setOp instruction (extract concode; clobbers ax), // using the following mapping: // LLVM -> X86 signed X86 unsigned @@ -267,62 +290,51 @@ ISel::visitSetCondInst (SetCondInst & I) // setgt -> setg seta // setle -> setle setbe // setge -> setge setae - switch (I.getOpcode ()) - { - case Instruction::SetEQ: - BuildMI (BB, X86::SETE, 0, X86::AL); - break; - case Instruction::SetGE: - if (unsignedComparison) - BuildMI (BB, X86::SETAE, 0, X86::AL); - else - BuildMI (BB, X86::SETGE, 0, X86::AL); - break; - case Instruction::SetGT: - if (unsignedComparison) - BuildMI (BB, X86::SETA, 0, X86::AL); - else - BuildMI (BB, X86::SETG, 0, X86::AL); - break; - case Instruction::SetLE: - if (unsignedComparison) - BuildMI (BB, X86::SETBE, 0, X86::AL); - else - BuildMI (BB, X86::SETLE, 0, X86::AL); - break; - case Instruction::SetLT: - if (unsignedComparison) - BuildMI (BB, X86::SETB, 0, X86::AL); - else - BuildMI (BB, X86::SETL, 0, X86::AL); - break; - case Instruction::SetNE: - BuildMI (BB, X86::SETNE, 0, X86::AL); - break; - default: - visitInstruction (I); - break; - } + + static const unsigned OpcodeTab[2][6] = { + {X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAr, X86::SETBEr, X86::SETAEr}, + {X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGr, X86::SETLEr, X86::SETGEr}, + }; + + BuildMI(BB, OpcodeTab[CompTy->isSigned()][OpNum], 0, X86::AL); + // Put it in the result using a move. - switch (resultWidth) + BuildMI (BB, X86::MOVrr8, 1, getReg(I)).addReg(X86::AL); +} + +/// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide +/// operand, in the specified target register. +void +ISel::promote32 (const unsigned targetReg, Value *v) +{ + unsigned vReg = getReg (v); + unsigned Class = getClass (v->getType ()); + bool isUnsigned = v->getType ()->isUnsigned (); + assert (((Class == cByte) || (Class == cShort) || (Class == cInt)) + && "Unpromotable operand class in promote32"); + switch (Class) { - case 1: - BuildMI (BB, X86::MOVrr8, 1, resultReg).addReg (X86::AL); + case cByte: + // Extend value into target register (8->32) + if (isUnsigned) + BuildMI (BB, X86::MOVZXr32r8, 1, targetReg).addReg (vReg); + else + BuildMI (BB, X86::MOVSXr32r8, 1, targetReg).addReg (vReg); break; - case 2: - BuildMI (BB, X86::MOVZXr16r8, 1, resultReg).addReg (X86::AL); + case cShort: + // Extend value into target register (16->32) + if (isUnsigned) + BuildMI (BB, X86::MOVZXr32r16, 1, targetReg).addReg (vReg); + else + BuildMI (BB, X86::MOVSXr32r16, 1, targetReg).addReg (vReg); break; - case 4: - BuildMI (BB, X86::MOVZXr32r8, 1, resultReg).addReg (X86::AL); - break; - case 8: - default: - visitInstruction (I); + case cInt: + // Move value into target register (32->32) + BuildMI (BB, X86::MOVrr32, 1, targetReg).addReg (vReg); break; } } - /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such, /// we have the following possibilities: /// @@ -334,71 +346,150 @@ ISel::visitSetCondInst (SetCondInst & I) /// ret long, ulong : Move value into EAX/EDX and return /// ret float/double : Top of FP stack /// -void ISel::visitReturnInst (ReturnInst &I) { - if (I.getNumOperands() == 0) { - // Emit a 'ret' instruction - BuildMI(BB, X86::RET, 0); - return; - } - - unsigned val = getReg(I.getOperand(0)); - unsigned Class = getClass(I.getOperand(0)->getType()); - bool isUnsigned = I.getOperand(0)->getType()->isUnsigned(); - switch (Class) { - case cByte: - // ret sbyte, ubyte: Extend value into EAX and return - if (isUnsigned) - BuildMI (BB, X86::MOVZXr32r8, 1, X86::EAX).addReg (val); - else - BuildMI (BB, X86::MOVSXr32r8, 1, X86::EAX).addReg (val); - break; - case cShort: - // ret short, ushort: Extend value into EAX and return - if (isUnsigned) - BuildMI (BB, X86::MOVZXr32r16, 1, X86::EAX).addReg (val); - else - BuildMI (BB, X86::MOVSXr32r16, 1, X86::EAX).addReg (val); - break; - case cInt: - // ret int, uint, ptr: Move value into EAX and return - // MOV EAX, - BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(val); - break; - - // ret float/double: top of FP stack - // FLD - case cFloat: // Floats - BuildMI(BB, X86::FLDr4, 1).addReg(val); - break; - case cDouble: // Doubles - BuildMI(BB, X86::FLDr8, 1).addReg(val); - break; - case cLong: - // ret long: use EAX(least significant 32 bits)/EDX (most - // significant 32)...uh, I think so Brain, but how do i call - // up the two parts of the value from inside this mouse - // cage? *zort* - default: - visitInstruction(I); - } - +void +ISel::visitReturnInst (ReturnInst &I) +{ + if (I.getNumOperands () == 0) + { + // Emit a 'ret' instruction + BuildMI (BB, X86::RET, 0); + return; + } + Value *rv = I.getOperand (0); + unsigned Class = getClass (rv->getType ()); + switch (Class) + { + // integral return values: extend or move into EAX and return. + case cByte: + case cShort: + case cInt: + promote32 (X86::EAX, rv); + break; + // ret float/double: top of FP stack + // FLD + case cFloat: // Floats + BuildMI (BB, X86::FLDr32, 1).addReg (getReg (rv)); + break; + case cDouble: // Doubles + BuildMI (BB, X86::FLDr64, 1).addReg (getReg (rv)); + break; + case cLong: + // ret long: use EAX(least significant 32 bits)/EDX (most + // significant 32)...uh, I think so Brain, but how do i call + // up the two parts of the value from inside this mouse + // cage? *zort* + default: + visitInstruction (I); + } // Emit a 'ret' instruction - BuildMI(BB, X86::RET, 0); + BuildMI (BB, X86::RET, 0); } - /// visitBranchInst - Handle conditional and unconditional branches here. Note /// that since code layout is frozen at this point, that if we are trying to /// jump to a block that is the immediate successor of the current block, we can /// just make a fall-through. (but we don't currently). /// -void ISel::visitBranchInst(BranchInst &BI) { - if (BI.isConditional()) // Only handles unconditional branches so far... - visitInstruction(BI); - - BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0)); +void +ISel::visitBranchInst (BranchInst & BI) +{ + if (BI.isConditional ()) + { + BasicBlock *ifTrue = BI.getSuccessor (0); + BasicBlock *ifFalse = BI.getSuccessor (1); // this is really unobvious + + // simplest thing I can think of: compare condition with zero, + // followed by jump-if-equal to ifFalse, and jump-if-nonequal to + // ifTrue + unsigned int condReg = getReg (BI.getCondition ()); + BuildMI (BB, X86::CMPri8, 2).addReg (condReg).addZImm (0); + BuildMI (BB, X86::JNE, 1).addPCDisp (BI.getSuccessor (0)); + BuildMI (BB, X86::JE, 1).addPCDisp (BI.getSuccessor (1)); + } + else // unconditional branch + { + BuildMI (BB, X86::JMP, 1).addPCDisp (BI.getSuccessor (0)); + } } +/// visitCallInst - Push args on stack and do a procedure call instruction. +void +ISel::visitCallInst (CallInst & CI) +{ + // keep a counter of how many bytes we pushed on the stack + unsigned bytesPushed = 0; + + // Push the arguments on the stack in reverse order, as specified by + // the ABI. + for (unsigned i = CI.getNumOperands()-1; i >= 1; --i) + { + Value *v = CI.getOperand (i); + switch (getClass (v->getType ())) + { + case cByte: + case cShort: + // Promote V to 32 bits wide, and move the result into EAX, + // then push EAX. + promote32 (X86::EAX, v); + BuildMI (BB, X86::PUSHr32, 1).addReg (X86::EAX); + bytesPushed += 4; + break; + case cInt: + case cFloat: { + unsigned Reg = getReg(v); + BuildMI (BB, X86::PUSHr32, 1).addReg(Reg); + bytesPushed += 4; + break; + } + default: + // FIXME: long/ulong/double args not handled. + visitInstruction (CI); + break; + } + } + // Emit a CALL instruction with PC-relative displacement. + BuildMI (BB, X86::CALLpcrel32, 1).addPCDisp (CI.getCalledValue ()); + + // Adjust the stack by `bytesPushed' amount if non-zero + if (bytesPushed > 0) + BuildMI (BB, X86::ADDri32, 2).addReg(X86::ESP).addZImm(bytesPushed); + + // If there is a return value, scavenge the result from the location the call + // leaves it in... + // + if (CI.getType() != Type::VoidTy) { + unsigned resultTypeClass = getClass (CI.getType ()); + switch (resultTypeClass) { + case cByte: + case cShort: + case cInt: { + // Integral results are in %eax, or the appropriate portion + // thereof. + static const unsigned regRegMove[] = { + X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 + }; + static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX }; + BuildMI (BB, regRegMove[resultTypeClass], 1, + getReg (CI)).addReg (AReg[resultTypeClass]); + break; + } + case cFloat: + // Floating-point return values live in %st(0) (i.e., the top of + // the FP stack.) The general way to approach this is to do a + // FSTP to save the top of the FP stack on the real stack, then + // do a MOV to load the top of the real stack into the target + // register. + visitInstruction (CI); // FIXME: add the right args for the calls below + // BuildMI (BB, X86::FSTPm32, 0); + // BuildMI (BB, X86::MOVmr32, 0); + break; + default: + std::cerr << "Cannot get return value for call of type '" + << *CI.getType() << "'\n"; + visitInstruction(CI); + } + } +} /// visitSimpleBinary - Implement simple binary operators for integral types... /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, @@ -429,33 +520,41 @@ void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) { BuildMI(BB, Opcode, 2, getReg(B)).addReg(Op0r).addReg(Op1r); } -/// visitMul - Multiplies are not simple binary operators because they must deal -/// with the EAX register explicitly. -/// -void ISel::visitMul(BinaryOperator &I) { - unsigned Class = getClass(I.getType()); - if (Class > 2) // FIXME: Handle longs - visitInstruction(I); +/// doMultiply - Emit appropriate instructions to multiply together +/// the registers op0Reg and op1Reg, and put the result in destReg. +/// The type of the result should be given as resultType. +void +ISel::doMultiply(unsigned destReg, const Type *resultType, + unsigned op0Reg, unsigned op1Reg) +{ + unsigned Class = getClass (resultType); + // FIXME: + assert (Class <= 2 && "Someday, we will learn how to multiply" + "longs and floating-point numbers. This is not that day."); + static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX }; - static const unsigned Clobbers[] ={ X86::AH , X86::DX , X86::EDX }; static const unsigned MulOpcode[]={ X86::MULrr8, X86::MULrr16, X86::MULrr32 }; static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 }; - unsigned Reg = Regs[Class]; - unsigned Clobber = Clobbers[Class]; - unsigned Op0Reg = getReg(I.getOperand(0)); - unsigned Op1Reg = getReg(I.getOperand(1)); - // Put the first operand into one of the A registers... - BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg); + // Emit a MOV to put the first operand into the appropriately-sized + // subreg of EAX. + BuildMI (BB, MovOpcode[Class], 1, Reg).addReg (op0Reg); - // Emit the appropriate multiply instruction... - BuildMI(BB, MulOpcode[Class], 3) - .addReg(Reg, UseAndDef).addReg(Op1Reg).addClobber(Clobber); + // Emit the appropriate multiply instruction. + BuildMI (BB, MulOpcode[Class], 1).addReg (op1Reg); - // Put the result into the destination register... - BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(Reg); + // Emit another MOV to put the result into the destination register. + BuildMI (BB, MovOpcode[Class], 1, destReg).addReg (Reg); +} + +/// visitMul - Multiplies are not simple binary operators because they must deal +/// with the EAX register explicitly. +/// +void ISel::visitMul(BinaryOperator &I) { + doMultiply (getReg (I), I.getType (), + getReg (I.getOperand (0)), getReg (I.getOperand (1))); } @@ -491,15 +590,14 @@ void ISel::visitDivRem(BinaryOperator &I) { if (isSigned) { // Emit a sign extension instruction... - BuildMI(BB, ExtOpcode[Class], 1, ExtReg).addReg(Reg); + BuildMI(BB, ExtOpcode[Class], 0); } else { // If unsigned, emit a zeroing instruction... (reg = xor reg, reg) BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg); } // Emit the appropriate divide or remainder instruction... - BuildMI(BB, DivOpcode[isSigned][Class], 2) - .addReg(Reg, UseAndDef).addReg(ExtReg, UseAndDef).addReg(Op1Reg); + BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg); // Figure out which register we want to pick the result out of... unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg; @@ -566,7 +664,7 @@ void ISel::visitShiftInst (ShiftInst &I) { const unsigned *OpTab = // Figure out the operand table to use NonConstantOperand[isLeftShift*2+isOperandSigned]; - BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addReg(X86::CL); + BuildMI(BB, OpTab[OperandClass], 1, DestReg).addReg(Op0r); } } @@ -616,6 +714,190 @@ void ISel::visitPHINode(PHINode &PN) { } } +/// visitCastInst - Here we have various kinds of copying with or without +/// sign extension going on. +void +ISel::visitCastInst (CastInst &CI) +{ + const Type *targetType = CI.getType (); + Value *operand = CI.getOperand (0); + unsigned int operandReg = getReg (operand); + const Type *sourceType = operand->getType (); + unsigned int destReg = getReg (CI); + // + // Currently we handle: + // + // 1) cast * to bool + // + // 2) cast {sbyte, ubyte} to {sbyte, ubyte} + // cast {short, ushort} to {ushort, short} + // cast {int, uint, ptr} to {int, uint, ptr} + // + // 3) cast {sbyte, ubyte} to {ushort, short} + // cast {sbyte, ubyte} to {int, uint, ptr} + // cast {short, ushort} to {int, uint, ptr} + // + // 4) cast {int, uint, ptr} to {short, ushort} + // cast {int, uint, ptr} to {sbyte, ubyte} + // cast {short, ushort} to {sbyte, ubyte} + // + // 1) Implement casts to bool by using compare on the operand followed + // by set if not zero on the result. + if (targetType == Type::BoolTy) + { + BuildMI (BB, X86::CMPri8, 2).addReg (operandReg).addZImm (0); + BuildMI (BB, X86::SETNEr, 1, destReg); + return; + } + // 2) Implement casts between values of the same type class (as determined + // by getClass) by using a register-to-register move. + unsigned int srcClass = getClass (sourceType); + unsigned int targClass = getClass (targetType); + static const unsigned regRegMove[] = { + X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 + }; + if ((srcClass < 3) && (targClass < 3) && (srcClass == targClass)) + { + BuildMI (BB, regRegMove[srcClass], 1, destReg).addReg (operandReg); + return; + } + // 3) Handle cast of SMALLER int to LARGER int using a move with sign + // extension or zero extension, depending on whether the source type + // was signed. + if ((srcClass < 3) && (targClass < 3) && (srcClass < targClass)) + { + static const unsigned ops[] = { + X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16, + X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16 + }; + unsigned srcSigned = sourceType->isSigned (); + BuildMI (BB, ops[3 * srcSigned + srcClass + targClass - 1], 1, + destReg).addReg (operandReg); + return; + } + // 4) Handle cast of LARGER int to SMALLER int using a move to EAX + // followed by a move out of AX or AL. + if ((srcClass < 3) && (targClass < 3) && (srcClass > targClass)) + { + static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX }; + BuildMI (BB, regRegMove[srcClass], 1, + AReg[srcClass]).addReg (operandReg); + BuildMI (BB, regRegMove[targClass], 1, destReg).addReg (AReg[srcClass]); + return; + } + // Anything we haven't handled already, we can't (yet) handle at all. + // + // FP to integral casts can be handled with FISTP to store onto the + // stack while converting to integer, followed by a MOV to load from + // the stack into the result register. Integral to FP casts can be + // handled with MOV to store onto the stack, followed by a FILD to + // load from the stack while converting to FP. For the moment, I + // can't quite get straight in my head how to borrow myself some + // stack space and write on it. Otherwise, this would be trivial. + visitInstruction (CI); +} + +/// visitGetElementPtrInst - I don't know, most programs don't have +/// getelementptr instructions, right? That means we can put off +/// implementing this, right? Right. This method emits machine +/// instructions to perform type-safe pointer arithmetic. I am +/// guessing this could be cleaned up somewhat to use fewer temporary +/// registers. +void +ISel::visitGetElementPtrInst (GetElementPtrInst &I) +{ + Value *basePtr = I.getPointerOperand (); + const TargetData &TD = TM.DataLayout; + unsigned basePtrReg = getReg (basePtr); + unsigned resultReg = getReg (I); + const Type *Ty = basePtr->getType(); + // GEPs have zero or more indices; we must perform a struct access + // or array access for each one. + for (GetElementPtrInst::op_iterator oi = I.idx_begin (), + oe = I.idx_end (); oi != oe; ++oi) { + Value *idx = *oi; + unsigned nextBasePtrReg = makeAnotherReg (); + if (const StructType *StTy = dyn_cast (Ty)) { + // It's a struct access. idx is the index into the structure, + // which names the field. This index must have ubyte type. + const ConstantUInt *CUI = cast (idx); + assert (CUI->getType () == Type::UByteTy + && "Funny-looking structure index in GEP"); + // Use the TargetData structure to pick out what the layout of + // the structure is in memory. Since the structure index must + // be constant, we can get its value and use it to find the + // right byte offset from the StructLayout class's list of + // structure member offsets. + unsigned idxValue = CUI->getValue (); + unsigned memberOffset = + TD.getStructLayout (StTy)->MemberOffsets[idxValue]; + // Emit an ADD to add memberOffset to the basePtr. + BuildMI (BB, X86::ADDri32, 2, + nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset); + // The next type is the member of the structure selected by the + // index. + Ty = StTy->getElementTypes ()[idxValue]; + } else if (const SequentialType *SqTy = cast (Ty)) { + // It's an array or pointer access: [ArraySize x ElementType]. + // The documentation does not seem to match the code on the type + // of array indices. The code seems to use long, and the docs + // (and the comments) say uint. If it is long, I don't know what + // we are going to do, because the X86 loves 64-bit types. + const Type *typeOfSequentialTypeIndex = SqTy->getIndexType (); + // idx is the index into the array. Unlike with structure + // indices, we may not know its actual value at code-generation + // time. + assert (idx->getType () == typeOfSequentialTypeIndex + && "Funny-looking array index in GEP"); + // We want to add basePtrReg to (idxReg * sizeof + // ElementType). First, we must find the size of the pointed-to + // type. (Not coincidentally, the next type is the type of the + // elements in the array.) + Ty = SqTy->getElementType (); + unsigned elementSize = TD.getTypeSize (Ty); + unsigned elementSizeReg = makeAnotherReg (); + copyConstantToRegister (ConstantInt::get (typeOfSequentialTypeIndex, + elementSize), + elementSizeReg); + unsigned idxReg = getReg (idx); + // Emit a MUL to multiply the register holding the index by + // elementSize, putting the result in memberOffsetReg. + unsigned memberOffsetReg = makeAnotherReg (); + doMultiply (memberOffsetReg, typeOfSequentialTypeIndex, + elementSizeReg, idxReg); + // Emit an ADD to add memberOffsetReg to the basePtr. + BuildMI (BB, X86::ADDrr32, 2, + nextBasePtrReg).addReg (basePtrReg).addReg (memberOffsetReg); + } + // Now that we are here, further indices refer to subtypes of this + // one, so we don't need to worry about basePtrReg itself, anymore. + basePtrReg = nextBasePtrReg; + } + // After we have processed all the indices, the result is left in + // basePtrReg. Move it to the register where we were expected to + // put the answer. A 32-bit move should do it, because we are in + // ILP32 land. + BuildMI (BB, X86::MOVrr32, 1, getReg (I)).addReg (basePtrReg); +} + + +/// visitMallocInst - I know that personally, whenever I want to remember +/// something, I have to clear off some space in my brain. +void +ISel::visitMallocInst (MallocInst &I) +{ + visitInstruction (I); +} + + +/// visitAllocaInst - I want some stack space. Come on, man, I said I +/// want some freakin' stack space. +void +ISel::visitAllocaInst (AllocaInst &I) +{ + visitInstruction (I); +} + /// createSimpleX86InstructionSelector - This pass converts an LLVM function /// into a machine code representation is a very simple peep-hole fashion. The