X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86InstrArithmetic.td;h=d86a4065a7a3e8b6f688375105b8e8a9fb6ecbd4;hb=d056dc0aae141d79131c6d537cf2add42922fb97;hp=d56763ea9d266b675beceb43dc872da8e357e226;hpb=766cbae4b1abcaf451949370c2fae8b339a4dca8;p=oota-llvm.git diff --git a/lib/Target/X86/X86InstrArithmetic.td b/lib/Target/X86/X86InstrArithmetic.td index d56763ea9d2..d86a4065a7a 100644 --- a/lib/Target/X86/X86InstrArithmetic.td +++ b/lib/Target/X86/X86InstrArithmetic.td @@ -29,11 +29,11 @@ def LEA32r : I<0x8D, MRMSrcMem, def LEA64_32r : I<0x8D, MRMSrcMem, (outs GR32:$dst), (ins lea64_32mem:$src), "lea{l}\t{$src|$dst}, {$dst|$src}", - [(set GR32:$dst, lea32addr:$src)], IIC_LEA>, + [(set GR32:$dst, lea64_32addr:$src)], IIC_LEA>, Requires<[In64BitMode]>; let isReMaterializable = 1 in -def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), +def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src), "lea{q}\t{$src|$dst}, {$dst|$src}", [(set GR64:$dst, lea64addr:$src)], IIC_LEA>; @@ -266,7 +266,7 @@ def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8 // unsigned division/remainder -let hasSideEffects = 0 in { +let hasSideEffects = 1 in { // so that we don't speculatively execute let Defs = [AL,EFLAGS,AX], Uses = [AX] in def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH "div{b}\t$src", [], IIC_DIV8_REG>; @@ -933,60 +933,60 @@ multiclass ArithBinOp_RF BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, let Constraints = "$src1 = $dst" in { let isCommutable = CommutableRR, isConvertibleToThreeAddress = ConvertibleToThreeAddress in { - def #NAME#8rr : BinOpRR_RF; - def #NAME#16rr : BinOpRR_RF; - def #NAME#32rr : BinOpRR_RF; - def #NAME#64rr : BinOpRR_RF; + def NAME#8rr : BinOpRR_RF; + def NAME#16rr : BinOpRR_RF; + def NAME#32rr : BinOpRR_RF; + def NAME#64rr : BinOpRR_RF; } // isCommutable - def #NAME#8rr_REV : BinOpRR_Rev; - def #NAME#16rr_REV : BinOpRR_Rev; - def #NAME#32rr_REV : BinOpRR_Rev; - def #NAME#64rr_REV : BinOpRR_Rev; + def NAME#8rr_REV : BinOpRR_Rev; + def NAME#16rr_REV : BinOpRR_Rev; + def NAME#32rr_REV : BinOpRR_Rev; + def NAME#64rr_REV : BinOpRR_Rev; - def #NAME#8rm : BinOpRM_RF; - def #NAME#16rm : BinOpRM_RF; - def #NAME#32rm : BinOpRM_RF; - def #NAME#64rm : BinOpRM_RF; + def NAME#8rm : BinOpRM_RF; + def NAME#16rm : BinOpRM_RF; + def NAME#32rm : BinOpRM_RF; + def NAME#64rm : BinOpRM_RF; let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { // NOTE: These are order specific, we want the ri8 forms to be listed // first so that they are slightly preferred to the ri forms. - def #NAME#16ri8 : BinOpRI8_RF<0x82, mnemonic, Xi16, opnodeflag, RegMRM>; - def #NAME#32ri8 : BinOpRI8_RF<0x82, mnemonic, Xi32, opnodeflag, RegMRM>; - def #NAME#64ri8 : BinOpRI8_RF<0x82, mnemonic, Xi64, opnodeflag, RegMRM>; - - def #NAME#8ri : BinOpRI_RF<0x80, mnemonic, Xi8 , opnodeflag, RegMRM>; - def #NAME#16ri : BinOpRI_RF<0x80, mnemonic, Xi16, opnodeflag, RegMRM>; - def #NAME#32ri : BinOpRI_RF<0x80, mnemonic, Xi32, opnodeflag, RegMRM>; - def #NAME#64ri32: BinOpRI_RF<0x80, mnemonic, Xi64, opnodeflag, RegMRM>; + def NAME#16ri8 : BinOpRI8_RF<0x82, mnemonic, Xi16, opnodeflag, RegMRM>; + def NAME#32ri8 : BinOpRI8_RF<0x82, mnemonic, Xi32, opnodeflag, RegMRM>; + def NAME#64ri8 : BinOpRI8_RF<0x82, mnemonic, Xi64, opnodeflag, RegMRM>; + + def NAME#8ri : BinOpRI_RF<0x80, mnemonic, Xi8 , opnodeflag, RegMRM>; + def NAME#16ri : BinOpRI_RF<0x80, mnemonic, Xi16, opnodeflag, RegMRM>; + def NAME#32ri : BinOpRI_RF<0x80, mnemonic, Xi32, opnodeflag, RegMRM>; + def NAME#64ri32: BinOpRI_RF<0x80, mnemonic, Xi64, opnodeflag, RegMRM>; } } // Constraints = "$src1 = $dst" - def #NAME#8mr : BinOpMR_RMW; - def #NAME#16mr : BinOpMR_RMW; - def #NAME#32mr : BinOpMR_RMW; - def #NAME#64mr : BinOpMR_RMW; + def NAME#8mr : BinOpMR_RMW; + def NAME#16mr : BinOpMR_RMW; + def NAME#32mr : BinOpMR_RMW; + def NAME#64mr : BinOpMR_RMW; // NOTE: These are order specific, we want the mi8 forms to be listed // first so that they are slightly preferred to the mi forms. - def #NAME#16mi8 : BinOpMI8_RMW; - def #NAME#32mi8 : BinOpMI8_RMW; - def #NAME#64mi8 : BinOpMI8_RMW; - - def #NAME#8mi : BinOpMI_RMW; - def #NAME#16mi : BinOpMI_RMW; - def #NAME#32mi : BinOpMI_RMW; - def #NAME#64mi32 : BinOpMI_RMW; - - def #NAME#8i8 : BinOpAI; - def #NAME#16i16 : BinOpAI; - def #NAME#32i32 : BinOpAI; - def #NAME#64i32 : BinOpAI; + def NAME#16mi8 : BinOpMI8_RMW; + def NAME#32mi8 : BinOpMI8_RMW; + def NAME#64mi8 : BinOpMI8_RMW; + + def NAME#8mi : BinOpMI_RMW; + def NAME#16mi : BinOpMI_RMW; + def NAME#32mi : BinOpMI_RMW; + def NAME#64mi32 : BinOpMI_RMW; + + def NAME#8i8 : BinOpAI; + def NAME#16i16 : BinOpAI; + def NAME#32i32 : BinOpAI; + def NAME#64i32 : BinOpAI; } } @@ -1004,60 +1004,60 @@ multiclass ArithBinOp_RFF BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, let Constraints = "$src1 = $dst" in { let isCommutable = CommutableRR, isConvertibleToThreeAddress = ConvertibleToThreeAddress in { - def #NAME#8rr : BinOpRR_RFF; - def #NAME#16rr : BinOpRR_RFF; - def #NAME#32rr : BinOpRR_RFF; - def #NAME#64rr : BinOpRR_RFF; + def NAME#8rr : BinOpRR_RFF; + def NAME#16rr : BinOpRR_RFF; + def NAME#32rr : BinOpRR_RFF; + def NAME#64rr : BinOpRR_RFF; } // isCommutable - def #NAME#8rr_REV : BinOpRR_Rev; - def #NAME#16rr_REV : BinOpRR_Rev; - def #NAME#32rr_REV : BinOpRR_Rev; - def #NAME#64rr_REV : BinOpRR_Rev; + def NAME#8rr_REV : BinOpRR_Rev; + def NAME#16rr_REV : BinOpRR_Rev; + def NAME#32rr_REV : BinOpRR_Rev; + def NAME#64rr_REV : BinOpRR_Rev; - def #NAME#8rm : BinOpRM_RFF; - def #NAME#16rm : BinOpRM_RFF; - def #NAME#32rm : BinOpRM_RFF; - def #NAME#64rm : BinOpRM_RFF; + def NAME#8rm : BinOpRM_RFF; + def NAME#16rm : BinOpRM_RFF; + def NAME#32rm : BinOpRM_RFF; + def NAME#64rm : BinOpRM_RFF; let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { // NOTE: These are order specific, we want the ri8 forms to be listed // first so that they are slightly preferred to the ri forms. - def #NAME#16ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi16, opnode, RegMRM>; - def #NAME#32ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi32, opnode, RegMRM>; - def #NAME#64ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi64, opnode, RegMRM>; - - def #NAME#8ri : BinOpRI_RFF<0x80, mnemonic, Xi8 , opnode, RegMRM>; - def #NAME#16ri : BinOpRI_RFF<0x80, mnemonic, Xi16, opnode, RegMRM>; - def #NAME#32ri : BinOpRI_RFF<0x80, mnemonic, Xi32, opnode, RegMRM>; - def #NAME#64ri32: BinOpRI_RFF<0x80, mnemonic, Xi64, opnode, RegMRM>; + def NAME#16ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi16, opnode, RegMRM>; + def NAME#32ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi32, opnode, RegMRM>; + def NAME#64ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi64, opnode, RegMRM>; + + def NAME#8ri : BinOpRI_RFF<0x80, mnemonic, Xi8 , opnode, RegMRM>; + def NAME#16ri : BinOpRI_RFF<0x80, mnemonic, Xi16, opnode, RegMRM>; + def NAME#32ri : BinOpRI_RFF<0x80, mnemonic, Xi32, opnode, RegMRM>; + def NAME#64ri32: BinOpRI_RFF<0x80, mnemonic, Xi64, opnode, RegMRM>; } } // Constraints = "$src1 = $dst" - def #NAME#8mr : BinOpMR_RMW_FF; - def #NAME#16mr : BinOpMR_RMW_FF; - def #NAME#32mr : BinOpMR_RMW_FF; - def #NAME#64mr : BinOpMR_RMW_FF; + def NAME#8mr : BinOpMR_RMW_FF; + def NAME#16mr : BinOpMR_RMW_FF; + def NAME#32mr : BinOpMR_RMW_FF; + def NAME#64mr : BinOpMR_RMW_FF; // NOTE: These are order specific, we want the mi8 forms to be listed // first so that they are slightly preferred to the mi forms. - def #NAME#16mi8 : BinOpMI8_RMW_FF; - def #NAME#32mi8 : BinOpMI8_RMW_FF; - def #NAME#64mi8 : BinOpMI8_RMW_FF; - - def #NAME#8mi : BinOpMI_RMW_FF; - def #NAME#16mi : BinOpMI_RMW_FF; - def #NAME#32mi : BinOpMI_RMW_FF; - def #NAME#64mi32 : BinOpMI_RMW_FF; - - def #NAME#8i8 : BinOpAI; - def #NAME#16i16 : BinOpAI; - def #NAME#32i32 : BinOpAI; - def #NAME#64i32 : BinOpAI; + def NAME#16mi8 : BinOpMI8_RMW_FF; + def NAME#32mi8 : BinOpMI8_RMW_FF; + def NAME#64mi8 : BinOpMI8_RMW_FF; + + def NAME#8mi : BinOpMI_RMW_FF; + def NAME#16mi : BinOpMI_RMW_FF; + def NAME#32mi : BinOpMI_RMW_FF; + def NAME#64mi32 : BinOpMI_RMW_FF; + + def NAME#8i8 : BinOpAI; + def NAME#16i16 : BinOpAI; + def NAME#32i32 : BinOpAI; + def NAME#64i32 : BinOpAI; } } @@ -1072,59 +1072,59 @@ multiclass ArithBinOp_F BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, let Defs = [EFLAGS] in { let isCommutable = CommutableRR, isConvertibleToThreeAddress = ConvertibleToThreeAddress in { - def #NAME#8rr : BinOpRR_F; - def #NAME#16rr : BinOpRR_F; - def #NAME#32rr : BinOpRR_F; - def #NAME#64rr : BinOpRR_F; + def NAME#8rr : BinOpRR_F; + def NAME#16rr : BinOpRR_F; + def NAME#32rr : BinOpRR_F; + def NAME#64rr : BinOpRR_F; } // isCommutable - def #NAME#8rr_REV : BinOpRR_F_Rev; - def #NAME#16rr_REV : BinOpRR_F_Rev; - def #NAME#32rr_REV : BinOpRR_F_Rev; - def #NAME#64rr_REV : BinOpRR_F_Rev; + def NAME#8rr_REV : BinOpRR_F_Rev; + def NAME#16rr_REV : BinOpRR_F_Rev; + def NAME#32rr_REV : BinOpRR_F_Rev; + def NAME#64rr_REV : BinOpRR_F_Rev; - def #NAME#8rm : BinOpRM_F; - def #NAME#16rm : BinOpRM_F; - def #NAME#32rm : BinOpRM_F; - def #NAME#64rm : BinOpRM_F; + def NAME#8rm : BinOpRM_F; + def NAME#16rm : BinOpRM_F; + def NAME#32rm : BinOpRM_F; + def NAME#64rm : BinOpRM_F; let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { // NOTE: These are order specific, we want the ri8 forms to be listed // first so that they are slightly preferred to the ri forms. - def #NAME#16ri8 : BinOpRI8_F<0x82, mnemonic, Xi16, opnode, RegMRM>; - def #NAME#32ri8 : BinOpRI8_F<0x82, mnemonic, Xi32, opnode, RegMRM>; - def #NAME#64ri8 : BinOpRI8_F<0x82, mnemonic, Xi64, opnode, RegMRM>; - - def #NAME#8ri : BinOpRI_F<0x80, mnemonic, Xi8 , opnode, RegMRM>; - def #NAME#16ri : BinOpRI_F<0x80, mnemonic, Xi16, opnode, RegMRM>; - def #NAME#32ri : BinOpRI_F<0x80, mnemonic, Xi32, opnode, RegMRM>; - def #NAME#64ri32: BinOpRI_F<0x80, mnemonic, Xi64, opnode, RegMRM>; + def NAME#16ri8 : BinOpRI8_F<0x82, mnemonic, Xi16, opnode, RegMRM>; + def NAME#32ri8 : BinOpRI8_F<0x82, mnemonic, Xi32, opnode, RegMRM>; + def NAME#64ri8 : BinOpRI8_F<0x82, mnemonic, Xi64, opnode, RegMRM>; + + def NAME#8ri : BinOpRI_F<0x80, mnemonic, Xi8 , opnode, RegMRM>; + def NAME#16ri : BinOpRI_F<0x80, mnemonic, Xi16, opnode, RegMRM>; + def NAME#32ri : BinOpRI_F<0x80, mnemonic, Xi32, opnode, RegMRM>; + def NAME#64ri32: BinOpRI_F<0x80, mnemonic, Xi64, opnode, RegMRM>; } - def #NAME#8mr : BinOpMR_F; - def #NAME#16mr : BinOpMR_F; - def #NAME#32mr : BinOpMR_F; - def #NAME#64mr : BinOpMR_F; + def NAME#8mr : BinOpMR_F; + def NAME#16mr : BinOpMR_F; + def NAME#32mr : BinOpMR_F; + def NAME#64mr : BinOpMR_F; // NOTE: These are order specific, we want the mi8 forms to be listed // first so that they are slightly preferred to the mi forms. - def #NAME#16mi8 : BinOpMI8_F; - def #NAME#32mi8 : BinOpMI8_F; - def #NAME#64mi8 : BinOpMI8_F; - - def #NAME#8mi : BinOpMI_F; - def #NAME#16mi : BinOpMI_F; - def #NAME#32mi : BinOpMI_F; - def #NAME#64mi32 : BinOpMI_F; - - def #NAME#8i8 : BinOpAI; - def #NAME#16i16 : BinOpAI; - def #NAME#32i32 : BinOpAI; - def #NAME#64i32 : BinOpAI; + def NAME#16mi8 : BinOpMI8_F; + def NAME#32mi8 : BinOpMI8_F; + def NAME#64mi8 : BinOpMI8_F; + + def NAME#8mi : BinOpMI_F; + def NAME#16mi : BinOpMI_F; + def NAME#32mi : BinOpMI_F; + def NAME#64mi32 : BinOpMI_F; + + def NAME#8i8 : BinOpAI; + def NAME#16i16 : BinOpAI; + def NAME#32i32 : BinOpAI; + def NAME#64i32 : BinOpAI; } } @@ -1256,3 +1256,49 @@ let Predicates = [HasBMI2] in { let Uses = [RDX] in defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem>, VEX_W; } + +//===----------------------------------------------------------------------===// +// ADCX Instruction +// +let hasSideEffects = 0, Predicates = [HasADX], Defs = [EFLAGS] in { + def ADCX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "adcx{l}\t{$src, $dst|$dst, $src}", + [], IIC_BIN_NONMEM>, T8, OpSize; + + def ADCX64rr : I<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "adcx{q}\t{$src, $dst|$dst, $src}", + [], IIC_BIN_NONMEM>, T8, OpSize, REX_W, Requires<[In64BitMode]>; + + let mayLoad = 1 in { + def ADCX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "adcx{l}\t{$src, $dst|$dst, $src}", + [], IIC_BIN_MEM>, T8, OpSize; + + def ADCX64rm : I<0xF6, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "adcx{q}\t{$src, $dst|$dst, $src}", + [], IIC_BIN_MEM>, T8, OpSize, REX_W, Requires<[In64BitMode]>; + } +} + +//===----------------------------------------------------------------------===// +// ADOX Instruction +// +let hasSideEffects = 0, Predicates = [HasADX], Defs = [EFLAGS] in { + def ADOX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), + "adox{l}\t{$src, $dst|$dst, $src}", + [], IIC_BIN_NONMEM>, T8XS; + + def ADOX64rr : I<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), + "adox{q}\t{$src, $dst|$dst, $src}", + [], IIC_BIN_NONMEM>, T8XS, REX_W, Requires<[In64BitMode]>; + + let mayLoad = 1 in { + def ADOX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), + "adox{l}\t{$src, $dst|$dst, $src}", + [], IIC_BIN_MEM>, T8XS; + + def ADOX64rm : I<0xF6, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), + "adox{q}\t{$src, $dst|$dst, $src}", + [], IIC_BIN_MEM>, T8XS, REX_W, Requires<[In64BitMode]>; + } +}