X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86InstrFormats.td;h=adc24e23182c7eecd41430b314dcf0e4ceb64adc;hb=ff500303705159a86b182f0794c830376ed7c127;hp=b50706c360fcad32d31e2ecfd6e026190c019fad;hpb=3491d67d3a50e81e3f65c1bdf01dd7962dc10c46;p=oota-llvm.git diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td index b50706c360f..adc24e23182 100644 --- a/lib/Target/X86/X86InstrFormats.td +++ b/lib/Target/X86/X86InstrFormats.td @@ -21,14 +21,15 @@ class Format val> { def Pseudo : Format<0>; def RawFrm : Format<1>; def AddRegFrm : Format<2>; def MRMDestReg : Format<3>; def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>; -def MRMSrcMem : Format<6>; +def MRMSrcMem : Format<6>; def RawFrmMemOffs : Format<7>; +def RawFrmSrc : Format<8>; def RawFrmDst : Format<9>; +def RawFrmDstSrc: Format<10>; def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>; def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>; def MRM6r : Format<22>; def MRM7r : Format<23>; def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>; def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>; def MRM6m : Format<30>; def MRM7m : Format<31>; -def MRMInitReg : Format<32>; def MRM_C1 : Format<33>; def MRM_C2 : Format<34>; def MRM_C3 : Format<35>; @@ -113,11 +114,10 @@ def CD8VT8 : CD8VForm<7>; // v := 8 // Prefix byte classes which are used to indicate to the ad-hoc machine code // emitter that various prefix bytes are required. class OpSize { bit hasOpSizePrefix = 1; } +class OpSize16 { bit hasOpSize16Prefix = 1; } class AdSize { bit hasAdSizePrefix = 1; } class REX_W { bit hasREX_WPrefix = 1; } class LOCK { bit hasLockPrefix = 1; } -class SegFS { bits<2> SegOvrBits = 1; } -class SegGS { bits<2> SegOvrBits = 2; } class TB { bits<5> Prefix = 1; } class REP { bits<5> Prefix = 2; } class D8 { bits<5> Prefix = 3; } @@ -139,6 +139,10 @@ class T8XS { bits<5> Prefix = 18; } class TAXD { bits<5> Prefix = 19; } class XOP8 { bits<5> Prefix = 20; } class XOP9 { bits<5> Prefix = 21; } +class XOPA { bits<5> Prefix = 22; } +class PD { bits<5> Prefix = 23; } +class T8PD { bits<5> Prefix = 24; } +class TAPD { bits<5> Prefix = 25; } class VEX { bit hasVEXPrefix = 1; } class VEX_W { bit hasVEX_WPrefix = 1; } class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; } @@ -151,6 +155,7 @@ class EVEX_4V : VEX_4V { bit hasEVEXPrefix = 1; } class EVEX_K { bit hasEVEX_K = 1; } class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; } class EVEX_B { bit hasEVEX_B = 1; } +class EVEX_RC { bit hasEVEX_RC = 1; } class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; } class EVEX_CD8 { bits<2> EVEX_CD8E = !if(!eq(esize, 8), 0b00, @@ -186,14 +191,18 @@ class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, // // Attributes specific to X86 instructions... // + bit ForceDisassemble = 0; // Force instruction to disassemble even though it's + // isCodeGenonly. Needed to hide an ambiguous + // AsmString from the parser, but still disassemble. + bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix? + bit hasOpSize16Prefix = 0;// Does this inst have a 0x66 prefix in 16-bit mode? bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix? bits<5> Prefix = 0; // Which prefix byte does this inst have? bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix? FPFormat FPForm = NotFP; // What flavor of FP instruction is this? bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix? - bits<2> SegOvrBits = 0; // Segment override prefix. Domain ExeDomain = d; bit hasVEXPrefix = 0; // Does this inst require a VEX prefix? bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field? @@ -214,36 +223,38 @@ class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding? bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix? + bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction. // TSFlags layout should be kept in sync with X86InstrInfo.h. let TSFlags{5-0} = FormBits; let TSFlags{6} = hasOpSizePrefix; - let TSFlags{7} = hasAdSizePrefix; - let TSFlags{12-8} = Prefix; - let TSFlags{13} = hasREX_WPrefix; - let TSFlags{16-14} = ImmT.Value; - let TSFlags{19-17} = FPForm.Value; - let TSFlags{20} = hasLockPrefix; - let TSFlags{22-21} = SegOvrBits; - let TSFlags{24-23} = ExeDomain.Value; - let TSFlags{32-25} = Opcode; - let TSFlags{33} = hasVEXPrefix; - let TSFlags{34} = hasVEX_WPrefix; - let TSFlags{35} = hasVEX_4VPrefix; - let TSFlags{36} = hasVEX_4VOp3Prefix; - let TSFlags{37} = hasVEX_i8ImmReg; - let TSFlags{38} = hasVEX_L; - let TSFlags{39} = ignoresVEX_L; - let TSFlags{40} = hasEVEXPrefix; - let TSFlags{41} = hasEVEX_K; - let TSFlags{42} = hasEVEX_Z; - let TSFlags{43} = hasEVEX_L2; - let TSFlags{44} = hasEVEX_B; - let TSFlags{46-45} = EVEX_CD8E; - let TSFlags{49-47} = EVEX_CD8V; - let TSFlags{50} = has3DNow0F0FOpcode; - let TSFlags{51} = hasMemOp4Prefix; - let TSFlags{52} = hasXOP_Prefix; + let TSFlags{7} = hasOpSize16Prefix; + let TSFlags{8} = hasAdSizePrefix; + let TSFlags{13-9} = Prefix; + let TSFlags{14} = hasREX_WPrefix; + let TSFlags{17-15} = ImmT.Value; + let TSFlags{20-18} = FPForm.Value; + let TSFlags{21} = hasLockPrefix; + let TSFlags{23-22} = ExeDomain.Value; + let TSFlags{31-24} = Opcode; + let TSFlags{32} = hasVEXPrefix; + let TSFlags{33} = hasVEX_WPrefix; + let TSFlags{34} = hasVEX_4VPrefix; + let TSFlags{35} = hasVEX_4VOp3Prefix; + let TSFlags{36} = hasVEX_i8ImmReg; + let TSFlags{37} = hasVEX_L; + let TSFlags{38} = ignoresVEX_L; + let TSFlags{39} = hasEVEXPrefix; + let TSFlags{40} = hasEVEX_K; + let TSFlags{41} = hasEVEX_Z; + let TSFlags{42} = hasEVEX_L2; + let TSFlags{43} = hasEVEX_B; + let TSFlags{45-44} = EVEX_CD8E; + let TSFlags{48-46} = EVEX_CD8V; + let TSFlags{49} = has3DNow0F0FOpcode; + let TSFlags{50} = hasMemOp4Prefix; + let TSFlags{51} = hasXOP_Prefix; + let TSFlags{52} = hasEVEX_RC; } class PseudoI pattern> @@ -334,6 +345,7 @@ class Iseg32 o, Format f, dag outs, dag ins, string asm, def __xs : XS; def __xd : XD; +def __pd : PD; // SI - SSE 1 & 2 scalar instructions class SI o, Format F, dag outs, dag ins, string asm, @@ -343,7 +355,7 @@ class SI o, Format F, dag outs, dag ins, string asm, !if(hasVEXPrefix /* VEX */, [UseAVX], !if(!eq(Prefix, __xs.Prefix), [UseSSE1], !if(!eq(Prefix, __xd.Prefix), [UseSSE2], - !if(hasOpSizePrefix, [UseSSE2], [UseSSE1]))))); + !if(!eq(Prefix, __pd.Prefix), [UseSSE2], [UseSSE1]))))); // AVX instructions have a 'v' prefix in the mnemonic let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm); @@ -367,7 +379,7 @@ class PI o, Format F, dag outs, dag ins, string asm, list pattern, : I { let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512], !if(hasVEXPrefix /* VEX */, [HasAVX], - !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1]))); + !if(!eq(Prefix, __pd.Prefix), [UseSSE2], [UseSSE1]))); // AVX instructions have a 'v' prefix in the mnemonic let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm); @@ -377,7 +389,7 @@ class PI o, Format F, dag outs, dag ins, string asm, list pattern, class MMXPI o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin, Domain d> : I { - let Predicates = !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]); + let Predicates = !if(!eq(Prefix, __pd.Prefix), [HasSSE2], [HasSSE1]); } // PIi8 - SSE 1 & 2 packed instructions with immediate @@ -386,7 +398,7 @@ class PIi8 o, Format F, dag outs, dag ins, string asm, : Ii8 { let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512], !if(hasVEXPrefix /* VEX */, [HasAVX], - !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1]))); + !if(!eq(Prefix, __pd.Prefix), [UseSSE2], [UseSSE1]))); // AVX instructions have a 'v' prefix in the mnemonic let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm); @@ -429,13 +441,13 @@ class VPSI o, Format F, dag outs, dag ins, string asm, // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix. // S2SI - SSE2 instructions with XS prefix. // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix. -// PDI - SSE2 instructions with TB and OpSize prefixes, packed double domain. -// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes. +// PDI - SSE2 instructions with PD prefix, packed double domain. +// PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix. // VSDI - SSE2 scalar instructions with XD prefix in AVX form. -// VPDI - SSE2 vector instructions with TB and OpSize prefixes in AVX form, +// VPDI - SSE2 vector instructions with PD prefix in AVX form, // packed double domain. -// VS2I - SSE2 scalar instructions with TB and OpSize prefixes in AVX form. -// S2I - SSE2 scalar instructions with TB and OpSize prefixes. +// VS2I - SSE2 scalar instructions with PD prefix in AVX form. +// S2I - SSE2 scalar instructions with PD prefix. // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as // MMX operands. // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as @@ -455,11 +467,11 @@ class S2SIi8 o, Format F, dag outs, dag ins, string asm, : Ii8, XS, Requires<[UseSSE2]>; class PDI o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, TB, OpSize, + : I, PD, Requires<[UseSSE2]>; class PDIi8 o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : Ii8, TB, OpSize, + : Ii8, PD, Requires<[UseSSE2]>; class VSDI o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> @@ -471,16 +483,15 @@ class VS2SI o, Format F, dag outs, dag ins, string asm, Requires<[HasAVX]>; class VPDI o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, TB, - OpSize, Requires<[HasAVX]>; + : I, + PD, Requires<[HasAVX]>; class VS2I o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, TB, - OpSize, Requires<[UseAVX]>; + : I, PD, + Requires<[UseAVX]>; class S2I o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, TB, - OpSize, Requires<[UseSSE2]>; + : I, PD, Requires<[UseSSE2]>; class MMXSDIi8 o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> : Ii8, XD, Requires<[HasSSE2]>; @@ -490,7 +501,7 @@ class MMXS2SIi8 o, Format F, dag outs, dag ins, string asm, // SSE3 Instruction Templates: // -// S3I - SSE3 instructions with TB and OpSize prefixes. +// S3I - SSE3 instructions with PD prefixes. // S3SI - SSE3 instructions with XS prefix. // S3DI - SSE3 instructions with XD prefix. @@ -504,7 +515,7 @@ class S3DI o, Format F, dag outs, dag ins, string asm, Requires<[UseSSE3]>; class S3I o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, TB, OpSize, + : I, PD, Requires<[UseSSE3]>; @@ -521,11 +532,11 @@ class S3I o, Format F, dag outs, dag ins, string asm, class SS38I o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, T8, + : I, T8PD, Requires<[UseSSSE3]>; class SS3AI o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : Ii8, TA, + : Ii8, TAPD, Requires<[UseSSSE3]>; class MMXSS38I o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> @@ -543,11 +554,11 @@ class MMXSS3AI o, Format F, dag outs, dag ins, string asm, // class SS48I o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, T8, + : I, T8PD, Requires<[UseSSE41]>; class SS4AIi8 o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : Ii8, TA, + : Ii8, TAPD, Requires<[UseSSE41]>; // SSE4.2 Instruction Templates: @@ -555,7 +566,7 @@ class SS4AIi8 o, Format F, dag outs, dag ins, string asm, // SS428I - SSE 4.2 instructions with T8 prefix. class SS428I o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, T8, + : I, T8PD, Requires<[UseSSE42]>; // SS42FI - SSE 4.2 instructions with T8XD prefix. @@ -567,53 +578,53 @@ class SS42FI o, Format F, dag outs, dag ins, string asm, // SS42AI = SSE 4.2 instructions with TA prefix class SS42AI o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : Ii8, TA, + : Ii8, TAPD, Requires<[UseSSE42]>; // AVX Instruction Templates: // Instructions introduced in AVX (no SSE equivalent forms) // -// AVX8I - AVX instructions with T8 and OpSize prefix. -// AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8. +// AVX8I - AVX instructions with T8PD prefix. +// AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8. class AVX8I o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, T8, OpSize, + : I, T8PD, Requires<[HasAVX]>; class AVXAIi8 o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : Ii8, TA, OpSize, + : Ii8, TAPD, Requires<[HasAVX]>; // AVX2 Instruction Templates: // Instructions introduced in AVX2 (no SSE equivalent forms) // -// AVX28I - AVX2 instructions with T8 and OpSize prefix. -// AVX2AIi8 - AVX2 instructions with TA, OpSize prefix and ImmT = Imm8. +// AVX28I - AVX2 instructions with T8PD prefix. +// AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8. class AVX28I o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, T8, OpSize, + : I, T8PD, Requires<[HasAVX2]>; class AVX2AIi8 o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : Ii8, TA, OpSize, + : Ii8, TAPD, Requires<[HasAVX2]>; // AVX-512 Instruction Templates: // Instructions introduced in AVX-512 (no SSE equivalent forms) // -// AVX5128I - AVX-512 instructions with T8 and OpSize prefix. -// AVX512AIi8 - AVX-512 instructions with TA, OpSize prefix and ImmT = Imm8. -// AVX512PDI - AVX-512 instructions with TB, OpSize, double packed. +// AVX5128I - AVX-512 instructions with T8PD prefix. +// AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8. +// AVX512PDI - AVX-512 instructions with PD, double packed. // AVX512PSI - AVX-512 instructions with TB, single packed. // AVX512XS8I - AVX-512 instructions with T8 and XS prefixes. // AVX512XSI - AVX-512 instructions with XS prefix, generic domain. -// AVX512BI - AVX-512 instructions with TB, OpSize, int packed domain. -// AVX512SI - AVX-512 scalar instructions with TB and OpSize prefixes. +// AVX512BI - AVX-512 instructions with PD, int packed domain. +// AVX512SI - AVX-512 scalar instructions with PD prefix. class AVX5128I o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, T8, OpSize, + : I, T8PD, Requires<[HasAVX512]>; class AVX512XS8I o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> @@ -629,79 +640,75 @@ class AVX512XDI o, Format F, dag outs, dag ins, string asm, Requires<[HasAVX512]>; class AVX512BI o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, TB, OpSize, + : I, PD, Requires<[HasAVX512]>; class AVX512BIi8 o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : Ii8, TB, OpSize, - Requires<[HasAVX512]>; -class AVX512SI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, TB, OpSize, + : Ii8, PD, Requires<[HasAVX512]>; class AVX512AIi8 o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : Ii8, TA, OpSize, + : Ii8, TAPD, Requires<[HasAVX512]>; class AVX512Ii8 o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : Ii8, - Requires<[HasAVX512]>; + : Ii8, TB, + Requires<[HasAVX512]>; class AVX512PDI o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, TB, - OpSize, Requires<[HasAVX512]>; + : I, PD, + Requires<[HasAVX512]>; class AVX512PSI o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> : I, TB, Requires<[HasAVX512]>; class AVX512PIi8 o, Format F, dag outs, dag ins, string asm, list pattern, Domain d, InstrItinClass itin = NoItinerary> - : Ii8, Requires<[HasAVX512]>; + : Ii8, TB, Requires<[HasAVX512]>; class AVX512PI o, Format F, dag outs, dag ins, string asm, list pattern, Domain d, InstrItinClass itin = NoItinerary> - : I, Requires<[HasAVX512]>; + : I, TB, Requires<[HasAVX512]>; class AVX512FMA3 o, Format F, dag outs, dag ins, string asm, listpattern, InstrItinClass itin = NoItinerary> - : I, T8, - OpSize, EVEX_4V, Requires<[HasAVX512]>; + : I, T8PD, + EVEX_4V, Requires<[HasAVX512]>; // AES Instruction Templates: // // AES8I // These use the same encoding as the SSE4.2 T8 and TA encodings. class AES8I o, Format F, dag outs, dag ins, string asm, - listpattern, InstrItinClass itin = NoItinerary> - : I, T8, + listpattern, InstrItinClass itin = IIC_AES> + : I, T8PD, Requires<[HasAES]>; class AESAI o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : Ii8, TA, + : Ii8, TAPD, Requires<[HasAES]>; // PCLMUL Instruction Templates class PCLMULIi8 o, Format F, dag outs, dag ins, string asm, listpattern, InstrItinClass itin = NoItinerary> - : Ii8, TA, - OpSize, Requires<[HasPCLMUL]>; + : Ii8, TAPD, + Requires<[HasPCLMUL]>; class AVXPCLMULIi8 o, Format F, dag outs, dag ins, string asm, listpattern, InstrItinClass itin = NoItinerary> - : Ii8, TA, - OpSize, VEX_4V, Requires<[HasAVX, HasPCLMUL]>; + : Ii8, TAPD, + VEX_4V, Requires<[HasAVX, HasPCLMUL]>; // FMA3 Instruction Templates class FMA3 o, Format F, dag outs, dag ins, string asm, listpattern, InstrItinClass itin = NoItinerary> - : I, T8, - OpSize, VEX_4V, FMASC, Requires<[HasFMA]>; + : I, T8PD, + VEX_4V, FMASC, Requires<[HasFMA]>; // FMA4 Instruction Templates class FMA4 o, Format F, dag outs, dag ins, string asm, listpattern, InstrItinClass itin = NoItinerary> - : Ii8, TA, - OpSize, VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>; + : Ii8, TAPD, + VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>; // XOP 2, 3 and 4 Operand Instruction Template class IXOP o, Format F, dag outs, dag ins, string asm, @@ -718,8 +725,8 @@ class IXOPi8 o, Format F, dag outs, dag ins, string asm, // XOP 5 operand instruction (VEX encoding!) class IXOP5 o, Format F, dag outs, dag ins, string asm, listpattern, InstrItinClass itin = NoItinerary> - : Ii8, TA, - OpSize, VEX_4V, VEX_I8IMM, Requires<[HasXOP]>; + : Ii8, TAPD, + VEX_4V, VEX_I8IMM, Requires<[HasXOP]>; // X86-64 Instruction templates... // @@ -730,6 +737,9 @@ class RI o, Format F, dag outs, dag ins, string asm, class RIi8 o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> : Ii8, REX_W; +class RIi16 o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : Ii16, REX_W; class RIi32 o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> : Ii32, REX_W; @@ -771,8 +781,9 @@ class VRS2I o, Format F, dag outs, dag ins, string asm, // // MMXI - MMX instructions with TB prefix. +// MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode. // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode. -// MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes. +// MMX2I - MMX / SSE2 instructions with PD prefix. // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix. // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix. // MMXID - MMX instructions with XD prefix. @@ -780,6 +791,9 @@ class VRS2I o, Format F, dag outs, dag ins, string asm, class MMXI o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> : I, TB, Requires<[HasMMX]>; +class MMXI32 o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : I, TB, Requires<[HasMMX,Not64BitMode]>; class MMXI64 o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> : I, TB, Requires<[HasMMX,In64BitMode]>; @@ -788,7 +802,7 @@ class MMXRI o, Format F, dag outs, dag ins, string asm, : I, TB, REX_W, Requires<[HasMMX]>; class MMX2I o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : I, TB, OpSize, Requires<[HasMMX]>; + : I, PD, Requires<[HasMMX]>; class MMXIi8 o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> : Ii8, TB, Requires<[HasMMX]>;