X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86InstrInfo.cpp;h=caffe62867b1d1c8d0de3fe86e1ce4155c635c78;hb=8dd8d261a48049a372ae285733c5b62ac7dbb5cb;hp=c81ddb19003ee82dbdc1d170a177b211a695eb05;hpb=b752e9a2aee4165ab07f39a16bbc304e84451e01;p=oota-llvm.git

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index c81ddb19003..caffe62867b 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -1,33 +1,69 @@
-//===- X86InstrInfo.cpp - X86 Instruction Information ---------------===//
+//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
+// 
+//                     The LLVM Compiler Infrastructure
 //
-// This file contains the X86 implementation of the MachineInstrInfo class.
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
+//
+// This file contains the X86 implementation of the TargetInstrInfo class.
 //
 //===----------------------------------------------------------------------===//
 
 #include "X86InstrInfo.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include <iostream>
+#include "X86.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
 
-// X86Insts - Turn the InstrInfo.def file into a bunch of instruction
-// descriptors
-//
-static const MachineInstrDescriptor X86Insts[] = {
-#define I(ENUM, NAME, FLAGS, TSFLAGS)   \
-             { NAME,                    \
-               -1, /* Always vararg */  \
-               ((TSFLAGS) & X86II::Void) ? -1 : 0,  /* Result is in 0 */ \
-               0, false, 0, 0, TSFLAGS, FLAGS, TSFLAGS },
-#include "X86InstrInfo.def"
-};
+#include "X86GenInstrInfo.inc"
+
+using namespace llvm;
 
 X86InstrInfo::X86InstrInfo()
-  : MachineInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) {
+  : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) {
+}
+
+
+// createNOPinstr - returns the target's implementation of NOP, which is
+// usually a pseudo-instruction, implemented by a degenerate version of
+// another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0'
+//
+MachineInstr* X86InstrInfo::createNOPinstr() const {
+  return BuildMI(X86::XCHGrr16, 2).addReg(X86::AX, MachineOperand::UseAndDef)
+                                  .addReg(X86::AX, MachineOperand::UseAndDef);
 }
 
 
-// print - Print out an x86 instruction in GAS syntax
-void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O) const {
-  // FIXME: This sucks.
-  O << getName(MI->getOpCode()) << "\n";
+/// isNOPinstr - not having a special NOP opcode, we need to know if a given
+/// instruction is interpreted as an `official' NOP instr, i.e., there may be
+/// more than one way to `do nothing' but only one canonical way to slack off.
+//
+bool X86InstrInfo::isNOPinstr(const MachineInstr &MI) const {
+  // Make sure the instruction is EXACTLY `xchg ax, ax'
+  if (MI.getOpcode() == X86::XCHGrr16) {
+    const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
+    if (op0.isRegister() && op0.getReg() == X86::AX &&
+        op1.isRegister() && op1.getReg() == X86::AX) {
+      return true;
+    }
+  }
+  // FIXME: there are several NOOP instructions, we should check for them here.
+  return false;
 }
 
+bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
+                               unsigned& sourceReg,
+                               unsigned& destReg) const {
+  MachineOpCode oc = MI.getOpcode();
+  if (oc == X86::MOVrr8 || oc == X86::MOVrr16 || oc == X86::MOVrr32 ||
+      oc == X86::FpMOV) {
+      assert(MI.getNumOperands() == 2 &&
+             MI.getOperand(0).isRegister() &&
+             MI.getOperand(1).isRegister() &&
+             "invalid register-register move instruction");
+      sourceReg = MI.getOperand(1).getReg();
+      destReg = MI.getOperand(0).getReg();
+      return true;
+  }
+  return false;
+}